* [PATCH 2/7] drm/i915/icl: apply Display WA #1178 to fix type C dongles
2018-09-28 16:47 [PATCH 1/7] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
@ 2018-09-28 16:47 ` Radhakrishna Sripada
2018-09-28 16:47 ` [PATCH 3/7] drm/i915/icl: Implement Display WA_1405510057 Radhakrishna Sripada
` (7 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Radhakrishna Sripada @ 2018-09-28 16:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Paulo Zanoni, Rodrigo Vivi
From: Lucas De Marchi <lucas.demarchi@intel.com>
Display WA #1178 is meant to fix Aux channel voltage swing too low with
some type C dongles. Although it is for type C, of ICL it only applies
to combo phy and not to eDP. This means we need to apply the WA only on
Aux B.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 263de5b54d69..4b472bc2d26d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8929,6 +8929,10 @@ enum skl_power_gate {
#define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
+#define ICL_AUX_ANAOVRD1_B _MMIO(0x6C398)
+#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
+#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
+
/* HDCP Key Registers */
#define HDCP_KEY_CONF _MMIO(0x66c00)
#define HDCP_AKSV_SEND_TRIGGER BIT(31)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 3cf8533e0834..292076330b95 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -436,6 +436,13 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
hsw_wait_for_power_well_enable(dev_priv, power_well);
+
+ /* Display WA #1178: icl */
+ if (IS_ICELAKE(dev_priv) && pw_idx == ICL_PW_CTL_IDX_AUX_B) {
+ val = I915_READ(ICL_AUX_ANAOVRD1_B);
+ val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
+ I915_WRITE(ICL_AUX_ANAOVRD1_B, val);
+ }
}
static void
--
2.9.3
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 3/7] drm/i915/icl: Implement Display WA_1405510057
2018-09-28 16:47 [PATCH 1/7] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
2018-09-28 16:47 ` [PATCH 2/7] drm/i915/icl: apply Display WA #1178 to fix type C dongles Radhakrishna Sripada
@ 2018-09-28 16:47 ` Radhakrishna Sripada
2018-09-28 16:47 ` [PATCH 4/7] drm/i915/icl: WaSendPushConstantsFromMMIO Radhakrishna Sripada
` (6 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Radhakrishna Sripada @ 2018-09-28 16:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi, Paulo Zanoni
Display WA_1405510057 asks to not enable YUV 420 HDMI
10bpc when horizontal blank size mod 8 reminder is 2.
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index a2dab0b6bde6..569583232d0b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1597,6 +1597,8 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
struct drm_atomic_state *state = crtc_state->base.state;
struct drm_connector_state *connector_state;
struct drm_connector *connector;
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
int i;
if (HAS_GMCH_DISPLAY(dev_priv))
@@ -1645,7 +1647,13 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
/* Display WA #1139: glk */
if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
- crtc_state->base.adjusted_mode.htotal > 5460)
+ adjusted_mode->htotal > 5460)
+ return false;
+
+ /* Display Wa_1405510057:icl */
+ if (crtc_state->ycbcr420 && bpc == 10 && IS_ICELAKE(dev_priv) &&
+ (adjusted_mode->crtc_hblank_end -
+ adjusted_mode->crtc_hblank_start) % 8 == 2)
return false;
return true;
--
2.9.3
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 4/7] drm/i915/icl: WaSendPushConstantsFromMMIO
2018-09-28 16:47 [PATCH 1/7] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
2018-09-28 16:47 ` [PATCH 2/7] drm/i915/icl: apply Display WA #1178 to fix type C dongles Radhakrishna Sripada
2018-09-28 16:47 ` [PATCH 3/7] drm/i915/icl: Implement Display WA_1405510057 Radhakrishna Sripada
@ 2018-09-28 16:47 ` Radhakrishna Sripada
2018-09-28 16:53 ` Chris Wilson
2018-10-01 10:48 ` Joonas Lahtinen
2018-09-28 16:47 ` [PATCH 5/7] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2 Radhakrishna Sripada
` (5 subsequent siblings)
8 siblings, 2 replies; 17+ messages in thread
From: Radhakrishna Sripada @ 2018-09-28 16:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Oscar Mateo
From: Oscar Mateo <oscar.mateo@intel.com>
Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ba4009b4ad2c..d0a982868964 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1013,6 +1013,8 @@ static void cnl_whitelist_build(struct whitelist *w)
static void icl_whitelist_build(struct whitelist *w)
{
+ /* WaSendPushConstantsFromMMIO:icl */
+ whitelist_reg(w, COMMON_SLICE_CHICKEN2);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
2.9.3
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 4/7] drm/i915/icl: WaSendPushConstantsFromMMIO
2018-09-28 16:47 ` [PATCH 4/7] drm/i915/icl: WaSendPushConstantsFromMMIO Radhakrishna Sripada
@ 2018-09-28 16:53 ` Chris Wilson
2018-10-01 10:40 ` Mika Kuoppala
2018-10-01 10:48 ` Joonas Lahtinen
1 sibling, 1 reply; 17+ messages in thread
From: Chris Wilson @ 2018-09-28 16:53 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx; +Cc: Oscar Mateo
Quoting Radhakrishna Sripada (2018-09-28 17:47:35)
> From: Oscar Mateo <oscar.mateo@intel.com>
>
> Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.
Question for reviewers is what other bits are exposed here?
-Chris
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/7] drm/i915/icl: WaSendPushConstantsFromMMIO
2018-09-28 16:47 ` [PATCH 4/7] drm/i915/icl: WaSendPushConstantsFromMMIO Radhakrishna Sripada
2018-09-28 16:53 ` Chris Wilson
@ 2018-10-01 10:48 ` Joonas Lahtinen
1 sibling, 0 replies; 17+ messages in thread
From: Joonas Lahtinen @ 2018-10-01 10:48 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx; +Cc: Oscar Mateo
Why is this mixed with display workarounds?
These were already once on the list and were decided not to be included
as there are no known users.
Regards, Joonas
Quoting Radhakrishna Sripada (2018-09-28 19:47:35)
> From: Oscar Mateo <oscar.mateo@intel.com>
>
> Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.
>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ba4009b4ad2c..d0a982868964 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -1013,6 +1013,8 @@ static void cnl_whitelist_build(struct whitelist *w)
>
> static void icl_whitelist_build(struct whitelist *w)
> {
> + /* WaSendPushConstantsFromMMIO:icl */
> + whitelist_reg(w, COMMON_SLICE_CHICKEN2);
> }
>
> static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
> --
> 2.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/7] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
2018-09-28 16:47 [PATCH 1/7] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
` (2 preceding siblings ...)
2018-09-28 16:47 ` [PATCH 4/7] drm/i915/icl: WaSendPushConstantsFromMMIO Radhakrishna Sripada
@ 2018-09-28 16:47 ` Radhakrishna Sripada
2018-09-28 16:53 ` Chris Wilson
2018-09-28 16:47 ` [PATCH 6/7] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Radhakrishna Sripada
` (4 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Radhakrishna Sripada @ 2018-09-28 16:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Oscar Mateo
From: Oscar Mateo <oscar.mateo@intel.com>
Required to dinamically set 'Small PL Lossless Fix Enable'
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index d0a982868964..ffddb3b769d5 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1015,6 +1015,9 @@ static void icl_whitelist_build(struct whitelist *w)
{
/* WaSendPushConstantsFromMMIO:icl */
whitelist_reg(w, COMMON_SLICE_CHICKEN2);
+
+ /* WaAllowUMDToModifyHalfSliceChicken2:icl */
+ whitelist_reg(w, HALF_SLICE_CHICKEN2);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
2.9.3
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 6/7] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
2018-09-28 16:47 [PATCH 1/7] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
` (3 preceding siblings ...)
2018-09-28 16:47 ` [PATCH 5/7] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2 Radhakrishna Sripada
@ 2018-09-28 16:47 ` Radhakrishna Sripada
2018-09-28 16:47 ` [PATCH 7/7] drm/i915/icl: Add Wa_1406609255 Radhakrishna Sripada
` (3 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Radhakrishna Sripada @ 2018-09-28 16:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Oscar Mateo
From: Oscar Mateo <oscar.mateo@intel.com>
Required to dinamically set 'Trilinear Filter Quality Mode'
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ffddb3b769d5..54a63c9b694f 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1018,6 +1018,9 @@ static void icl_whitelist_build(struct whitelist *w)
/* WaAllowUMDToModifyHalfSliceChicken2:icl */
whitelist_reg(w, HALF_SLICE_CHICKEN2);
+
+ /* WaAllowUMDToModifyHalfSliceChicken7:icl */
+ whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
2.9.3
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 7/7] drm/i915/icl: Add Wa_1406609255
2018-09-28 16:47 [PATCH 1/7] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
` (4 preceding siblings ...)
2018-09-28 16:47 ` [PATCH 6/7] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Radhakrishna Sripada
@ 2018-09-28 16:47 ` Radhakrishna Sripada
2018-09-28 22:19 ` Anuj Phogat
` (2 more replies)
2018-09-28 16:51 ` [PATCH 1/7] drm/i915/icl: Add WaEnable32PlaneMode Chris Wilson
` (2 subsequent siblings)
8 siblings, 3 replies; 17+ messages in thread
From: Radhakrishna Sripada @ 2018-09-28 16:47 UTC (permalink / raw)
To: intel-gfx
Shader feature to prefetch binding tables does not support 16:6 18:8 BTP
formats. Enabling fault handling could result in hangs with faults.
Disabling demand prefetch would disable binding table prefetch.
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b472bc2d26d..117ae5bf647c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7411,6 +7411,9 @@ enum {
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
+#define GEN7_SARCHKMD _MMIO(0xB000)
+#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
+
#define GEN7_L3SQCREG1 _MMIO(0xB010)
#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 54a63c9b694f..9d5f48b98803 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -909,6 +909,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
/* WaEnable32PlaneMode:icl */
I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
_MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
+
+ /* Wa_1406609255:icl (pre-prod) */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0))
+ I915_WRITE(GEN7_SARCHKMD,
+ I915_READ(GEN7_SARCHKMD) |
+ GEN7_DISABLE_DEMAND_PREFETCH);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
2.9.3
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 7/7] drm/i915/icl: Add Wa_1406609255
2018-09-28 16:47 ` [PATCH 7/7] drm/i915/icl: Add Wa_1406609255 Radhakrishna Sripada
@ 2018-09-28 22:19 ` Anuj Phogat
2018-10-01 10:36 ` Mika Kuoppala
2018-10-01 11:05 ` Mika Kuoppala
2 siblings, 0 replies; 17+ messages in thread
From: Anuj Phogat @ 2018-09-28 22:19 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: Intel GFX
On Fri, Sep 28, 2018 at 9:50 AM Radhakrishna Sripada
<radhakrishna.sripada@intel.com> wrote:
>
> Shader feature to prefetch binding tables does not support 16:6 18:8 BTP
> formats. Enabling fault handling could result in hangs with faults.
> Disabling demand prefetch would disable binding table prefetch.
>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4b472bc2d26d..117ae5bf647c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7411,6 +7411,9 @@ enum {
> #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
>
> +#define GEN7_SARCHKMD _MMIO(0xB000)
> +#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
> +
> #define GEN7_L3SQCREG1 _MMIO(0xB010)
> #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 54a63c9b694f..9d5f48b98803 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -909,6 +909,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> /* WaEnable32PlaneMode:icl */
> I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
> _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
> +
> + /* Wa_1406609255:icl (pre-prod) */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0))
> + I915_WRITE(GEN7_SARCHKMD,
> + I915_READ(GEN7_SARCHKMD) |
> + GEN7_DISABLE_DEMAND_PREFETCH);
> }
>
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> --
> 2.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Tested and Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
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^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 7/7] drm/i915/icl: Add Wa_1406609255
2018-09-28 16:47 ` [PATCH 7/7] drm/i915/icl: Add Wa_1406609255 Radhakrishna Sripada
2018-09-28 22:19 ` Anuj Phogat
@ 2018-10-01 10:36 ` Mika Kuoppala
2018-10-01 11:05 ` Mika Kuoppala
2 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2018-10-01 10:36 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx
Radhakrishna Sripada <radhakrishna.sripada@intel.com> writes:
> Shader feature to prefetch binding tables does not support 16:6 18:8 BTP
> formats. Enabling fault handling could result in hangs with faults.
> Disabling demand prefetch would disable binding table prefetch.
>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4b472bc2d26d..117ae5bf647c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7411,6 +7411,9 @@ enum {
> #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
>
> +#define GEN7_SARCHKMD _MMIO(0xB000)
> +#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
> +
> #define GEN7_L3SQCREG1 _MMIO(0xB010)
> #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 54a63c9b694f..9d5f48b98803 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -909,6 +909,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> /* WaEnable32PlaneMode:icl */
> I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
> _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
> +
> + /* Wa_1406609255:icl (pre-prod) */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0))
This is fixed on C0.
-Mika
> + I915_WRITE(GEN7_SARCHKMD,
> + I915_READ(GEN7_SARCHKMD) |
> + GEN7_DISABLE_DEMAND_PREFETCH);
> }
>
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> --
> 2.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 7/7] drm/i915/icl: Add Wa_1406609255
2018-09-28 16:47 ` [PATCH 7/7] drm/i915/icl: Add Wa_1406609255 Radhakrishna Sripada
2018-09-28 22:19 ` Anuj Phogat
2018-10-01 10:36 ` Mika Kuoppala
@ 2018-10-01 11:05 ` Mika Kuoppala
2 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2018-10-01 11:05 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx
Radhakrishna Sripada <radhakrishna.sripada@intel.com> writes:
> Shader feature to prefetch binding tables does not support 16:6 18:8 BTP
> formats.
s/formats./,causing lower performance if used. And with fault
handling enabled can cause gpu hangs.
> Disabling demand prefetch would disable binding table prefetch.
>
Also please add:
References: HSDES#1406609255, HSDES#1406573985
And as mentioned earlied, this is fixed on C0 so limit
range to ICL_REVID_B0.
Thanks,
-Mika
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4b472bc2d26d..117ae5bf647c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7411,6 +7411,9 @@ enum {
> #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
>
> +#define GEN7_SARCHKMD _MMIO(0xB000)
> +#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
> +
> #define GEN7_L3SQCREG1 _MMIO(0xB010)
> #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 54a63c9b694f..9d5f48b98803 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -909,6 +909,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> /* WaEnable32PlaneMode:icl */
> I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
> _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
> +
> + /* Wa_1406609255:icl (pre-prod) */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0))
> + I915_WRITE(GEN7_SARCHKMD,
> + I915_READ(GEN7_SARCHKMD) |
> + GEN7_DISABLE_DEMAND_PREFETCH);
> }
>
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> --
> 2.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/7] drm/i915/icl: Add WaEnable32PlaneMode
2018-09-28 16:47 [PATCH 1/7] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
` (5 preceding siblings ...)
2018-09-28 16:47 ` [PATCH 7/7] drm/i915/icl: Add Wa_1406609255 Radhakrishna Sripada
@ 2018-09-28 16:51 ` Chris Wilson
2018-10-01 11:52 ` ✓ Fi.CI.BAT: success for series starting with [1/7] " Patchwork
2018-10-01 13:15 ` ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 17+ messages in thread
From: Chris Wilson @ 2018-09-28 16:51 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx; +Cc: Oscar Mateo Lozano, Michel Thierry
Quoting Radhakrishna Sripada (2018-09-28 17:47:32)
> Gen11 Display suports 32 planes in total. Enable the new format in context
> status to be used and expanded to 32 planes.
>
> Cc: Oscar Mateo Lozano <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 27e650fe591b..263de5b54d69 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2573,6 +2573,7 @@ enum i915_power_well_id {
> /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
> #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
> #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
> +#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
>
> /* WaClearTdlStateAckDirtyBits */
> #define GEN8_STATE_ACK _MMIO(0x20F0)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 4bcdeaf8d98f..ba4009b4ad2c 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -905,6 +905,10 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> I915_WRITE(GAMT_CHKN_BIT_REG,
> I915_READ(GAMT_CHKN_BIT_REG) |
> GAMT_CHKN_DISABLE_L3_COH_PIPE);
> +
> + /* WaEnable32PlaneMode:icl */
> + I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
> + _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
gt_wa for display? Odd choice of location.
-Chris
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [1/7] drm/i915/icl: Add WaEnable32PlaneMode
2018-09-28 16:47 [PATCH 1/7] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
` (6 preceding siblings ...)
2018-09-28 16:51 ` [PATCH 1/7] drm/i915/icl: Add WaEnable32PlaneMode Chris Wilson
@ 2018-10-01 11:52 ` Patchwork
2018-10-01 13:15 ` ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-10-01 11:52 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/7] drm/i915/icl: Add WaEnable32PlaneMode
URL : https://patchwork.freedesktop.org/series/50340/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4906 -> Patchwork_10303 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/50340/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10303 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_module_reload@basic-reload:
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-bdw-samus: NOTRUN -> INCOMPLETE (fdo#107773)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-icl-u: PASS -> INCOMPLETE (fdo#107713)
igt@pm_rpm@basic-pci-d3-state:
fi-skl-6600u: PASS -> FAIL (fdo#107707)
==== Possible fixes ====
igt@gem_exec_suspend@basic-s3:
fi-bdw-samus: INCOMPLETE (fdo#107773) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107707 https://bugs.freedesktop.org/show_bug.cgi?id=107707
fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
== Participating hosts (50 -> 45) ==
Additional (2): fi-skl-caroline fi-snb-2520m
Missing (7): fi-hsw-4770r fi-ilk-m540 fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4906 -> Patchwork_10303
CI_DRM_4906: 187637a6495f71dd240d02badbf2fecc1e3c1bb2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4658: cab89ce2c5da684d01deff402d4e8e11441beadb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10303: 701c41d934c219edba293256032e0262e7e7fb0c @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
701c41d934c2 drm/i915/icl: Add Wa_1406609255
6782832c3e2f drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
592a1d4a7b2a drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
06b0334e7372 drm/i915/icl: WaSendPushConstantsFromMMIO
91f7b4d05da2 drm/i915/icl: Implement Display WA_1405510057
73f64ac7335e drm/i915/icl: apply Display WA #1178 to fix type C dongles
0d6df61c673c drm/i915/icl: Add WaEnable32PlaneMode
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10303/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [1/7] drm/i915/icl: Add WaEnable32PlaneMode
2018-09-28 16:47 [PATCH 1/7] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
` (7 preceding siblings ...)
2018-10-01 11:52 ` ✓ Fi.CI.BAT: success for series starting with [1/7] " Patchwork
@ 2018-10-01 13:15 ` Patchwork
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-10-01 13:15 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/7] drm/i915/icl: Add WaEnable32PlaneMode
URL : https://patchwork.freedesktop.org/series/50340/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4906_full -> Patchwork_10303_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10303_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_suspend@shrink:
shard-snb: PASS -> INCOMPLETE (fdo#106886, fdo#105411)
igt@gem_exec_await@wide-contexts:
shard-kbl: PASS -> FAIL (fdo#100007)
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665)
igt@kms_setmode@basic:
shard-apl: PASS -> FAIL (fdo#99912)
==== Possible fixes ====
igt@kms_color@pipe-c-ctm-blue-to-red:
shard-kbl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +24
igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
shard-glk: DMESG-WARN (fdo#105763, fdo#106538) -> PASS +1
igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled:
shard-glk: FAIL (fdo#103232) -> PASS
==== Warnings ====
igt@kms_available_modes_crc@available_mode_test_crc:
shard-kbl: DMESG-WARN (fdo#103558, fdo#105602) -> FAIL (fdo#106641)
fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (6 -> 5) ==
Missing (1): shard-skl
== Build changes ==
* Linux: CI_DRM_4906 -> Patchwork_10303
CI_DRM_4906: 187637a6495f71dd240d02badbf2fecc1e3c1bb2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4658: cab89ce2c5da684d01deff402d4e8e11441beadb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10303: 701c41d934c219edba293256032e0262e7e7fb0c @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10303/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread