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From: Julien Thierry <julien.thierry@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org,
	joel@joelfernandes.org, marc.zyngier@arm.com,
	christoffer.dall@arm.com, james.morse@arm.com,
	catalin.marinas@arm.com, will.deacon@arm.com,
	mark.rutland@arm.com, Julien Thierry <julien.thierry@arm.com>
Subject: [PATCH v7 25/25] arm64: Enable the support of pseudo-NMIs
Date: Wed, 12 Dec 2018 16:47:25 +0000	[thread overview]
Message-ID: <1544633245-6036-26-git-send-email-julien.thierry@arm.com> (raw)
In-Reply-To: <1544633245-6036-1-git-send-email-julien.thierry@arm.com>

Add a build option and a command line parameter to build and enable the
support of pseudo-NMIs.

Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Suggested-by: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
---
 Documentation/admin-guide/kernel-parameters.txt |  6 ++++++
 arch/arm64/Kconfig                              | 14 ++++++++++++++
 arch/arm64/kernel/cpufeature.c                  | 11 ++++++++++-
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index aefd358..0e6628d 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -1184,6 +1184,12 @@
 			to discrete, to make X server driver able to add WB
 			entry later. This parameter enables that.
 
+	enable_pseudo_nmi [ARM64]
+			Enables support for pseudo-NMIs in the kernel. This
+			requires both the kernel to be built with
+			CONFIG_ARM64_PSEUDO_NMI and to be running on a
+			platform with GICv3.
+
 	enable_timer_pin_1 [X86]
 			Enable PIN 1 of APIC timer
 			Can be useful to work around chipset bugs
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index ea2ab03..3c294f6 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -983,6 +983,20 @@ config ARM64_SSBD
 
 	  If unsure, say Y.
 
+config ARM64_PSEUDO_NMI
+	bool "Support for NMI-like interrupts"
+	select CONFIG_ARM_GIC_V3
+	help
+	  Adds support for mimicking Non-Maskable Interrupts through the use of
+	  GIC interrupt priority. This support requires version 3 or later of
+	  Arm GIC.
+
+	  This high priority configuration for interrupts need to be
+	  explicitly enabled through the new kernel parameter
+	  "enable_pseudo_nmi".
+
+	  If unsure, say N
+
 menuconfig ARMV8_DEPRECATED
 	bool "Emulate deprecated/obsolete ARMv8 instructions"
 	depends on COMPAT
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index b78205a..7f03f0b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1149,10 +1149,19 @@ static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
 #endif /* CONFIG_ARM64_RAS_EXTN */
 
 #ifdef CONFIG_ARM64_PSEUDO_NMI
+static bool enable_pseudo_nmi;
+
+static int __init early_enable_pseudo_nmi(char *p)
+{
+	enable_pseudo_nmi = true;
+	return 0;
+}
+early_param("enable_pseudo_nmi", early_enable_pseudo_nmi);
+
 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
 				   int scope)
 {
-	return false;
+	return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
 }
 #endif
 
-- 
1.9.1


WARNING: multiple messages have this Message-ID (diff)
From: Julien Thierry <julien.thierry@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: mark.rutland@arm.com, daniel.thompson@linaro.org,
	Julien Thierry <julien.thierry@arm.com>,
	marc.zyngier@arm.com, catalin.marinas@arm.com,
	will.deacon@arm.com, linux-kernel@vger.kernel.org,
	christoffer.dall@arm.com, james.morse@arm.com,
	joel@joelfernandes.org
Subject: [PATCH v7 25/25] arm64: Enable the support of pseudo-NMIs
Date: Wed, 12 Dec 2018 16:47:25 +0000	[thread overview]
Message-ID: <1544633245-6036-26-git-send-email-julien.thierry@arm.com> (raw)
In-Reply-To: <1544633245-6036-1-git-send-email-julien.thierry@arm.com>

Add a build option and a command line parameter to build and enable the
support of pseudo-NMIs.

Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Suggested-by: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
---
 Documentation/admin-guide/kernel-parameters.txt |  6 ++++++
 arch/arm64/Kconfig                              | 14 ++++++++++++++
 arch/arm64/kernel/cpufeature.c                  | 11 ++++++++++-
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index aefd358..0e6628d 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -1184,6 +1184,12 @@
 			to discrete, to make X server driver able to add WB
 			entry later. This parameter enables that.
 
+	enable_pseudo_nmi [ARM64]
+			Enables support for pseudo-NMIs in the kernel. This
+			requires both the kernel to be built with
+			CONFIG_ARM64_PSEUDO_NMI and to be running on a
+			platform with GICv3.
+
 	enable_timer_pin_1 [X86]
 			Enable PIN 1 of APIC timer
 			Can be useful to work around chipset bugs
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index ea2ab03..3c294f6 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -983,6 +983,20 @@ config ARM64_SSBD
 
 	  If unsure, say Y.
 
+config ARM64_PSEUDO_NMI
+	bool "Support for NMI-like interrupts"
+	select CONFIG_ARM_GIC_V3
+	help
+	  Adds support for mimicking Non-Maskable Interrupts through the use of
+	  GIC interrupt priority. This support requires version 3 or later of
+	  Arm GIC.
+
+	  This high priority configuration for interrupts need to be
+	  explicitly enabled through the new kernel parameter
+	  "enable_pseudo_nmi".
+
+	  If unsure, say N
+
 menuconfig ARMV8_DEPRECATED
 	bool "Emulate deprecated/obsolete ARMv8 instructions"
 	depends on COMPAT
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index b78205a..7f03f0b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1149,10 +1149,19 @@ static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
 #endif /* CONFIG_ARM64_RAS_EXTN */
 
 #ifdef CONFIG_ARM64_PSEUDO_NMI
+static bool enable_pseudo_nmi;
+
+static int __init early_enable_pseudo_nmi(char *p)
+{
+	enable_pseudo_nmi = true;
+	return 0;
+}
+early_param("enable_pseudo_nmi", early_enable_pseudo_nmi);
+
 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
 				   int scope)
 {
-	return false;
+	return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
 }
 #endif
 
-- 
1.9.1


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  parent reply	other threads:[~2018-12-12 16:48 UTC|newest]

Thread overview: 91+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-12 16:47 [PATCH v7 00/25] arm64: provide pseudo NMI with GICv3 Julien Thierry
2018-12-12 16:47 ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 01/25] arm64: Fix HCR.TGE status for NMI contexts Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 21:39   ` Sasha Levin
2018-12-12 21:39     ` Sasha Levin
2018-12-17  8:49   ` Julien Thierry
2018-12-17  8:49     ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 02/25] arm64: Remove unused daif related functions/macros Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 03/25] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 04/25] arm64: cpufeature: Add cpufeature for IRQ priority masking Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 05/25] arm/arm64: gic-v3: Add PMR and RPR accessors Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 06/25] irqchip/gic-v3: Switch to PMR masking before calling IRQ handler Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 07/25] arm64: ptrace: Provide definitions for PMR values Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 08/25] arm64: Make PMR part of task context Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 09/25] arm64: Unmask PMR before going idle Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 10/25] arm64: kvm: Unmask PMR before entering guest Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 11/25] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 17:27   ` Ard Biesheuvel
2018-12-12 17:27     ` Ard Biesheuvel
2018-12-12 17:59     ` Julien Thierry
2018-12-12 17:59       ` Julien Thierry
2018-12-12 18:10       ` Ard Biesheuvel
2018-12-12 18:10         ` Ard Biesheuvel
2018-12-13  8:54         ` Julien Thierry
2018-12-13  8:54           ` Julien Thierry
2018-12-13 11:35           ` Ard Biesheuvel
2018-12-13 11:35             ` Ard Biesheuvel
2018-12-13 12:02             ` Julien Thierry
2018-12-13 12:02               ` Julien Thierry
2018-12-13 15:03               ` Julien Thierry
2018-12-13 15:03                 ` Julien Thierry
2018-12-14 15:23                 ` Julien Thierry
2018-12-14 15:23                   ` Julien Thierry
2018-12-14 15:49                   ` Ard Biesheuvel
2018-12-14 15:49                     ` Ard Biesheuvel
2018-12-14 16:40                     ` Julien Thierry
2018-12-14 16:40                       ` Julien Thierry
2018-12-19 17:01                       ` Julien Thierry
2018-12-19 17:01                         ` Julien Thierry
2018-12-20 17:53                         ` Ard Biesheuvel
2018-12-20 17:53                           ` Ard Biesheuvel
2018-12-21 10:25                           ` Julien Thierry
2018-12-21 10:25                             ` Julien Thierry
2018-12-16 14:47   ` Jian-Lin Chen
2018-12-16 14:47     ` Jian-Lin Chen
2018-12-17  9:26     ` Julien Thierry
2018-12-17  9:26       ` Julien Thierry
2018-12-18  8:36       ` Jian-Lin Chen
2018-12-18  8:36         ` Jian-Lin Chen
2018-12-12 16:47 ` [PATCH v7 12/25] arm64: daifflags: Include PMR in daifflags restore operations Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 13/25] arm64: alternative: Allow alternative status checking per cpufeature Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 14/25] arm64: alternative: Apply alternatives early in boot process Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 15/25] irqchip/gic-v3: Factor group0 detection into functions Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 16/25] arm64: Switch to PMR masking when starting CPUs Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 17/25] arm64: gic-v3: Implement arch support for priority masking Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 18/25] irqchip/gic-v3: Detect if GIC can support pseudo-NMIs Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 19/25] irqchip/gic-v3: Handle pseudo-NMIs Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 20/25] irqchip/gic: Add functions to access irq priorities Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 21/25] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 22/25] arm64: Handle serror in NMI context Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 23/25] arm64: Skip preemption when exiting an NMI Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` [PATCH v7 24/25] arm64: Skip irqflags tracing for NMI in IRQs disabled context Julien Thierry
2018-12-12 16:47   ` Julien Thierry
2018-12-12 16:47 ` Julien Thierry [this message]
2018-12-12 16:47   ` [PATCH v7 25/25] arm64: Enable the support of pseudo-NMIs Julien Thierry
2018-12-12 16:52 ` [PATCH v7 00/25] arm64: provide pseudo NMI with GICv3 Julien Thierry
2018-12-12 16:52   ` Julien Thierry

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