* [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2
@ 2019-01-18 16:59 Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 01/12] target/mips: Move comment containing summary of CP0 registers Aleksandar Markovic
` (12 more replies)
0 siblings, 13 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-01-18 16:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
The following changes since commit 681d61362d3f766a00806b89d6581869041f73cb:
Merge remote-tracking branch 'remotes/jnsnow/tags/bitmaps-pull-request' into staging (2019-01-17 12:48:42 +0000)
are available in the git repository at:
https://github.com/AMarkovic/qemu tags/mips-queue-january-17-2019-v2
for you to fetch changes up to a168a796e1c251787fcdf2d9ca1e9e69cb86ffcd:
target/mips: Introduce 32 R5900 multimedia registers (2019-01-18 16:53:28 +0100)
----------------------------------------------------------------
MIPS queue for January 17, 2019 - v2
v1->v2:
- fixed "make check" error
content:
- provide access to configuration registers SAARI, SAAR, and
MemoryMapID
- update Inter-Thread Communication Unit
- CP0-related cleanups
- introduce R5900 multimedia registers
----------------------------------------------------------------
Aleksandar Markovic (6):
target/mips: Move comment containing summary of CP0 registers
target/mips: Add preprocessor constants for 32 major CP0 registers
target/mips: Use preprocessor constants for 32 major CP0 registers
target/mips: Amend preprocessor constants for CP0 registers
target/mips: Add CP0 register MemoryMapID
target/mips: Rename 'rn' to 'register_name'
Fredrik Noring (1):
target/mips: Introduce 32 R5900 multimedia registers
Yongbok Kim (5):
target/mips: Add fields for SAARI and SAAR CP0 registers
target/mips: Provide R/W access to SAARI and SAAR CP0 registers
target/mips: Add field and R/W access to ITU control register ICR0
target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
target/mips: Update ITU to handle bus errors
hw/mips/cps.c | 8 +
hw/misc/mips_itu.c | 73 ++-
include/hw/misc/mips_itu.h | 8 +
target/mips/cpu.h | 331 +++++++++---
target/mips/helper.h | 6 +
target/mips/internal.h | 1 +
target/mips/machine.c | 7 +-
target/mips/op_helper.c | 64 +++
target/mips/translate.c | 1192 +++++++++++++++++++++++---------------------
9 files changed, 1042 insertions(+), 648 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PULL v2 01/12] target/mips: Move comment containing summary of CP0 registers
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
@ 2019-01-18 16:59 ` Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 02/12] target/mips: Add preprocessor constants for 32 major " Aleksandar Markovic
` (11 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-01-18 16:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Move comment containing summary of CP0 registers. Checkpatch
script reported some tabs in the resutling diff, so convert
these tabs to spaces too.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 165 +++++++++++++++++++++++++++---------------------------
1 file changed, 84 insertions(+), 81 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 03c03fd..6c2a7e4 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -123,87 +123,6 @@ typedef struct mips_def_t mips_def_t;
#define MIPS_KSCRATCH_NUM 6
#define MIPS_MAAR_MAX 16 /* Must be an even number. */
-typedef struct TCState TCState;
-struct TCState {
- target_ulong gpr[32];
- target_ulong PC;
- target_ulong HI[MIPS_DSP_ACC];
- target_ulong LO[MIPS_DSP_ACC];
- target_ulong ACX[MIPS_DSP_ACC];
- target_ulong DSPControl;
- int32_t CP0_TCStatus;
-#define CP0TCSt_TCU3 31
-#define CP0TCSt_TCU2 30
-#define CP0TCSt_TCU1 29
-#define CP0TCSt_TCU0 28
-#define CP0TCSt_TMX 27
-#define CP0TCSt_RNST 23
-#define CP0TCSt_TDS 21
-#define CP0TCSt_DT 20
-#define CP0TCSt_DA 15
-#define CP0TCSt_A 13
-#define CP0TCSt_TKSU 11
-#define CP0TCSt_IXMT 10
-#define CP0TCSt_TASID 0
- int32_t CP0_TCBind;
-#define CP0TCBd_CurTC 21
-#define CP0TCBd_TBE 17
-#define CP0TCBd_CurVPE 0
- target_ulong CP0_TCHalt;
- target_ulong CP0_TCContext;
- target_ulong CP0_TCSchedule;
- target_ulong CP0_TCScheFBack;
- int32_t CP0_Debug_tcstatus;
- target_ulong CP0_UserLocal;
-
- int32_t msacsr;
-
-#define MSACSR_FS 24
-#define MSACSR_FS_MASK (1 << MSACSR_FS)
-#define MSACSR_NX 18
-#define MSACSR_NX_MASK (1 << MSACSR_NX)
-#define MSACSR_CEF 2
-#define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
-#define MSACSR_RM 0
-#define MSACSR_RM_MASK (0x3 << MSACSR_RM)
-#define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
- MSACSR_FS_MASK)
-
- float_status msa_fp_status;
-
-#define NUMBER_OF_MXU_REGISTERS 16
- target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
- target_ulong mxu_cr;
-#define MXU_CR_LC 31
-#define MXU_CR_RC 30
-#define MXU_CR_BIAS 2
-#define MXU_CR_RD_EN 1
-#define MXU_CR_MXU_EN 0
-
-};
-
-typedef struct CPUMIPSState CPUMIPSState;
-struct CPUMIPSState {
- TCState active_tc;
- CPUMIPSFPUContext active_fpu;
-
- uint32_t current_tc;
- uint32_t current_fpu;
-
- uint32_t SEGBITS;
- uint32_t PABITS;
-#if defined(TARGET_MIPS64)
-# define PABITS_BASE 36
-#else
-# define PABITS_BASE 32
-#endif
- target_ulong SEGMask;
- uint64_t PAMask;
-#define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
-
- int32_t msair;
-#define MSAIR_ProcID 8
-#define MSAIR_Rev 0
/*
* Summary of CP0 registers
@@ -314,6 +233,90 @@ struct CPUMIPSState {
* 7 TagLo TagHi KScratch<n>
*
*/
+
+
+typedef struct TCState TCState;
+struct TCState {
+ target_ulong gpr[32];
+ target_ulong PC;
+ target_ulong HI[MIPS_DSP_ACC];
+ target_ulong LO[MIPS_DSP_ACC];
+ target_ulong ACX[MIPS_DSP_ACC];
+ target_ulong DSPControl;
+ int32_t CP0_TCStatus;
+#define CP0TCSt_TCU3 31
+#define CP0TCSt_TCU2 30
+#define CP0TCSt_TCU1 29
+#define CP0TCSt_TCU0 28
+#define CP0TCSt_TMX 27
+#define CP0TCSt_RNST 23
+#define CP0TCSt_TDS 21
+#define CP0TCSt_DT 20
+#define CP0TCSt_DA 15
+#define CP0TCSt_A 13
+#define CP0TCSt_TKSU 11
+#define CP0TCSt_IXMT 10
+#define CP0TCSt_TASID 0
+ int32_t CP0_TCBind;
+#define CP0TCBd_CurTC 21
+#define CP0TCBd_TBE 17
+#define CP0TCBd_CurVPE 0
+ target_ulong CP0_TCHalt;
+ target_ulong CP0_TCContext;
+ target_ulong CP0_TCSchedule;
+ target_ulong CP0_TCScheFBack;
+ int32_t CP0_Debug_tcstatus;
+ target_ulong CP0_UserLocal;
+
+ int32_t msacsr;
+
+#define MSACSR_FS 24
+#define MSACSR_FS_MASK (1 << MSACSR_FS)
+#define MSACSR_NX 18
+#define MSACSR_NX_MASK (1 << MSACSR_NX)
+#define MSACSR_CEF 2
+#define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
+#define MSACSR_RM 0
+#define MSACSR_RM_MASK (0x3 << MSACSR_RM)
+#define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
+ MSACSR_FS_MASK)
+
+ float_status msa_fp_status;
+
+#define NUMBER_OF_MXU_REGISTERS 16
+ target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
+ target_ulong mxu_cr;
+#define MXU_CR_LC 31
+#define MXU_CR_RC 30
+#define MXU_CR_BIAS 2
+#define MXU_CR_RD_EN 1
+#define MXU_CR_MXU_EN 0
+
+};
+
+typedef struct CPUMIPSState CPUMIPSState;
+struct CPUMIPSState {
+ TCState active_tc;
+ CPUMIPSFPUContext active_fpu;
+
+ uint32_t current_tc;
+ uint32_t current_fpu;
+
+ uint32_t SEGBITS;
+ uint32_t PABITS;
+#if defined(TARGET_MIPS64)
+# define PABITS_BASE 36
+#else
+# define PABITS_BASE 32
+#endif
+ target_ulong SEGMask;
+ uint64_t PAMask;
+#define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
+
+ int32_t msair;
+#define MSAIR_ProcID 8
+#define MSAIR_Rev 0
+
/*
* CP0 Register 0
*/
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PULL v2 02/12] target/mips: Add preprocessor constants for 32 major CP0 registers
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 01/12] target/mips: Move comment containing summary of CP0 registers Aleksandar Markovic
@ 2019-01-18 16:59 ` Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 03/12] target/mips: Use " Aleksandar Markovic
` (10 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-01-18 16:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add preprocessor constants for 32 major CP0 registers.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 6c2a7e4..b095422 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -233,6 +233,38 @@ typedef struct mips_def_t mips_def_t;
* 7 TagLo TagHi KScratch<n>
*
*/
+#define CPO_REGISTER_00 0
+#define CPO_REGISTER_01 1
+#define CPO_REGISTER_02 2
+#define CPO_REGISTER_03 3
+#define CPO_REGISTER_04 4
+#define CPO_REGISTER_05 5
+#define CPO_REGISTER_06 6
+#define CPO_REGISTER_07 7
+#define CPO_REGISTER_08 8
+#define CPO_REGISTER_09 9
+#define CPO_REGISTER_10 10
+#define CPO_REGISTER_11 11
+#define CPO_REGISTER_12 12
+#define CPO_REGISTER_13 13
+#define CPO_REGISTER_14 14
+#define CPO_REGISTER_15 15
+#define CPO_REGISTER_16 16
+#define CPO_REGISTER_17 17
+#define CPO_REGISTER_18 18
+#define CPO_REGISTER_19 19
+#define CPO_REGISTER_20 20
+#define CPO_REGISTER_21 21
+#define CPO_REGISTER_22 22
+#define CPO_REGISTER_23 23
+#define CPO_REGISTER_24 24
+#define CPO_REGISTER_25 25
+#define CPO_REGISTER_26 26
+#define CPO_REGISTER_27 27
+#define CPO_REGISTER_28 28
+#define CPO_REGISTER_29 29
+#define CPO_REGISTER_30 30
+#define CPO_REGISTER_31 31
typedef struct TCState TCState;
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PULL v2 03/12] target/mips: Use preprocessor constants for 32 major CP0 registers
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 01/12] target/mips: Move comment containing summary of CP0 registers Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 02/12] target/mips: Add preprocessor constants for 32 major " Aleksandar Markovic
@ 2019-01-18 16:59 ` Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 04/12] target/mips: Add fields for SAARI and SAAR " Aleksandar Markovic
` (9 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-01-18 16:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Use preprocessor constants for 32 major CP0 registers.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 272 ++++++++++++++++++++++++------------------------
1 file changed, 136 insertions(+), 136 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 057aaf9..827d0f7 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6570,7 +6570,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *rn = "invalid";
switch (reg) {
- case 2:
+ case CPO_REGISTER_02:
switch (sel) {
case 0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
@@ -6581,7 +6581,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 3:
+ case CPO_REGISTER_03:
switch (sel) {
case 0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
@@ -6592,7 +6592,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 17:
+ case CPO_REGISTER_17:
switch (sel) {
case 0:
gen_mfhc0_load64(arg, offsetof(CPUMIPSState, lladdr),
@@ -6608,7 +6608,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 28:
+ case CPO_REGISTER_28:
switch (sel) {
case 0:
case 2:
@@ -6638,7 +6638,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
uint64_t mask = ctx->PAMask >> 36;
switch (reg) {
- case 2:
+ case CPO_REGISTER_02:
switch (sel) {
case 0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
@@ -6650,7 +6650,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 3:
+ case CPO_REGISTER_03:
switch (sel) {
case 0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
@@ -6662,7 +6662,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 17:
+ case CPO_REGISTER_17:
switch (sel) {
case 0:
/* LLAddr is read-only (the only exception is bit 0 if LLB is
@@ -6680,7 +6680,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 28:
+ case CPO_REGISTER_28:
switch (sel) {
case 0:
case 2:
@@ -6720,7 +6720,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
check_insn(ctx, ISA_MIPS32);
switch (reg) {
- case 0:
+ case CPO_REGISTER_00:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
@@ -6750,7 +6750,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 1:
+ case CPO_REGISTER_01:
switch (sel) {
case 0:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
@@ -6796,7 +6796,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 2:
+ case CPO_REGISTER_02:
switch (sel) {
case 0:
{
@@ -6854,7 +6854,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 3:
+ case CPO_REGISTER_03:
switch (sel) {
case 0:
{
@@ -6882,7 +6882,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 4:
+ case CPO_REGISTER_04:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
@@ -6904,7 +6904,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 5:
+ case CPO_REGISTER_05:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
@@ -6952,7 +6952,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 6:
+ case CPO_REGISTER_06:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
@@ -6992,7 +6992,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 7:
+ case CPO_REGISTER_07:
switch (sel) {
case 0:
check_insn(ctx, ISA_MIPS32R2);
@@ -7003,7 +7003,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 8:
+ case CPO_REGISTER_08:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
@@ -7030,7 +7030,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 9:
+ case CPO_REGISTER_09:
switch (sel) {
case 0:
/* Mark as an IO operation because we read the time. */
@@ -7053,7 +7053,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 10:
+ case CPO_REGISTER_10:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
@@ -7064,7 +7064,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 11:
+ case CPO_REGISTER_11:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
@@ -7075,7 +7075,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 12:
+ case CPO_REGISTER_12:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
@@ -7100,7 +7100,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 13:
+ case CPO_REGISTER_13:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
@@ -7110,7 +7110,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 14:
+ case CPO_REGISTER_14:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
@@ -7121,7 +7121,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 15:
+ case CPO_REGISTER_15:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
@@ -7144,7 +7144,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 16:
+ case CPO_REGISTER_16:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
@@ -7183,7 +7183,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 17:
+ case CPO_REGISTER_17:
switch (sel) {
case 0:
gen_helper_mfc0_lladdr(arg, cpu_env);
@@ -7203,7 +7203,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 18:
+ case CPO_REGISTER_18:
switch (sel) {
case 0:
case 1:
@@ -7221,7 +7221,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 19:
+ case CPO_REGISTER_19:
switch (sel) {
case 0:
case 1:
@@ -7239,7 +7239,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 20:
+ case CPO_REGISTER_20:
switch (sel) {
case 0:
#if defined(TARGET_MIPS64)
@@ -7253,7 +7253,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 21:
+ case CPO_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
switch (sel) {
@@ -7265,11 +7265,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 22:
+ case CPO_REGISTER_22:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "'Diagnostic"; /* implementation dependent */
break;
- case 23:
+ case CPO_REGISTER_23:
switch (sel) {
case 0:
gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
@@ -7295,7 +7295,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 24:
+ case CPO_REGISTER_24:
switch (sel) {
case 0:
/* EJTAG support */
@@ -7307,7 +7307,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 25:
+ case CPO_REGISTER_25:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
@@ -7345,7 +7345,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 26:
+ case CPO_REGISTER_26:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
@@ -7355,7 +7355,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 27:
+ case CPO_REGISTER_27:
switch (sel) {
case 0:
case 1:
@@ -7368,7 +7368,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 28:
+ case CPO_REGISTER_28:
switch (sel) {
case 0:
case 2:
@@ -7393,7 +7393,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 29:
+ case CPO_REGISTER_29:
switch (sel) {
case 0:
case 2:
@@ -7413,7 +7413,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 30:
+ case CPO_REGISTER_30:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
@@ -7424,7 +7424,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 31:
+ case CPO_REGISTER_31:
switch (sel) {
case 0:
/* EJTAG support */
@@ -7470,7 +7470,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
switch (reg) {
- case 0:
+ case CPO_REGISTER_00:
switch (sel) {
case 0:
gen_helper_mtc0_index(cpu_env, arg);
@@ -7500,7 +7500,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 1:
+ case CPO_REGISTER_01:
switch (sel) {
case 0:
/* ignored */
@@ -7547,7 +7547,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 2:
+ case CPO_REGISTER_02:
switch (sel) {
case 0:
gen_helper_mtc0_entrylo0(cpu_env, arg);
@@ -7592,7 +7592,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 3:
+ case CPO_REGISTER_03:
switch (sel) {
case 0:
gen_helper_mtc0_entrylo1(cpu_env, arg);
@@ -7607,7 +7607,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 4:
+ case CPO_REGISTER_04:
switch (sel) {
case 0:
gen_helper_mtc0_context(cpu_env, arg);
@@ -7627,7 +7627,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 5:
+ case CPO_REGISTER_05:
switch (sel) {
case 0:
gen_helper_mtc0_pagemask(cpu_env, arg);
@@ -7673,7 +7673,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 6:
+ case CPO_REGISTER_06:
switch (sel) {
case 0:
gen_helper_mtc0_wired(cpu_env, arg);
@@ -7713,7 +7713,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 7:
+ case CPO_REGISTER_07:
switch (sel) {
case 0:
check_insn(ctx, ISA_MIPS32R2);
@@ -7725,7 +7725,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 8:
+ case CPO_REGISTER_08:
switch (sel) {
case 0:
/* ignored */
@@ -7747,7 +7747,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 9:
+ case CPO_REGISTER_09:
switch (sel) {
case 0:
gen_helper_mtc0_count(cpu_env, arg);
@@ -7758,7 +7758,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 10:
+ case CPO_REGISTER_10:
switch (sel) {
case 0:
gen_helper_mtc0_entryhi(cpu_env, arg);
@@ -7768,7 +7768,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 11:
+ case CPO_REGISTER_11:
switch (sel) {
case 0:
gen_helper_mtc0_compare(cpu_env, arg);
@@ -7779,7 +7779,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 12:
+ case CPO_REGISTER_12:
switch (sel) {
case 0:
save_cpu_state(ctx, 1);
@@ -7814,7 +7814,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 13:
+ case CPO_REGISTER_13:
switch (sel) {
case 0:
save_cpu_state(ctx, 1);
@@ -7830,7 +7830,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 14:
+ case CPO_REGISTER_14:
switch (sel) {
case 0:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
@@ -7840,7 +7840,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 15:
+ case CPO_REGISTER_15:
switch (sel) {
case 0:
/* ignored */
@@ -7855,7 +7855,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 16:
+ case CPO_REGISTER_16:
switch (sel) {
case 0:
gen_helper_mtc0_config0(cpu_env, arg);
@@ -7904,7 +7904,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 17:
+ case CPO_REGISTER_17:
switch (sel) {
case 0:
gen_helper_mtc0_lladdr(cpu_env, arg);
@@ -7924,7 +7924,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 18:
+ case CPO_REGISTER_18:
switch (sel) {
case 0:
case 1:
@@ -7942,7 +7942,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 19:
+ case CPO_REGISTER_19:
switch (sel) {
case 0:
case 1:
@@ -7960,7 +7960,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 20:
+ case CPO_REGISTER_20:
switch (sel) {
case 0:
#if defined(TARGET_MIPS64)
@@ -7973,7 +7973,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 21:
+ case CPO_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
switch (sel) {
@@ -7985,11 +7985,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 22:
+ case CPO_REGISTER_22:
/* ignored */
rn = "Diagnostic"; /* implementation dependent */
break;
- case 23:
+ case CPO_REGISTER_23:
switch (sel) {
case 0:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
@@ -8028,7 +8028,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 24:
+ case CPO_REGISTER_24:
switch (sel) {
case 0:
/* EJTAG support */
@@ -8039,7 +8039,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 25:
+ case CPO_REGISTER_25:
switch (sel) {
case 0:
gen_helper_mtc0_performance0(cpu_env, arg);
@@ -8077,7 +8077,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 26:
+ case CPO_REGISTER_26:
switch (sel) {
case 0:
gen_helper_mtc0_errctl(cpu_env, arg);
@@ -8088,7 +8088,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 27:
+ case CPO_REGISTER_27:
switch (sel) {
case 0:
case 1:
@@ -8101,7 +8101,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 28:
+ case CPO_REGISTER_28:
switch (sel) {
case 0:
case 2:
@@ -8121,7 +8121,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 29:
+ case CPO_REGISTER_29:
switch (sel) {
case 0:
case 2:
@@ -8142,7 +8142,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 30:
+ case CPO_REGISTER_30:
switch (sel) {
case 0:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
@@ -8152,7 +8152,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 31:
+ case CPO_REGISTER_31:
switch (sel) {
case 0:
/* EJTAG support */
@@ -8202,7 +8202,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
check_insn(ctx, ISA_MIPS64);
switch (reg) {
- case 0:
+ case CPO_REGISTER_00:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
@@ -8232,7 +8232,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 1:
+ case CPO_REGISTER_01:
switch (sel) {
case 0:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
@@ -8278,7 +8278,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 2:
+ case CPO_REGISTER_02:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
@@ -8323,7 +8323,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 3:
+ case CPO_REGISTER_03:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
@@ -8338,7 +8338,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 4:
+ case CPO_REGISTER_04:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
@@ -8358,7 +8358,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 5:
+ case CPO_REGISTER_05:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
@@ -8403,7 +8403,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 6:
+ case CPO_REGISTER_06:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
@@ -8443,7 +8443,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 7:
+ case CPO_REGISTER_07:
switch (sel) {
case 0:
check_insn(ctx, ISA_MIPS32R2);
@@ -8454,7 +8454,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 8:
+ case CPO_REGISTER_08:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
@@ -8480,7 +8480,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 9:
+ case CPO_REGISTER_09:
switch (sel) {
case 0:
/* Mark as an IO operation because we read the time. */
@@ -8503,7 +8503,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 10:
+ case CPO_REGISTER_10:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
@@ -8513,7 +8513,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 11:
+ case CPO_REGISTER_11:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
@@ -8524,7 +8524,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 12:
+ case CPO_REGISTER_12:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
@@ -8549,7 +8549,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 13:
+ case CPO_REGISTER_13:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
@@ -8559,7 +8559,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 14:
+ case CPO_REGISTER_14:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
@@ -8569,7 +8569,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 15:
+ case CPO_REGISTER_15:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
@@ -8590,7 +8590,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 16:
+ case CPO_REGISTER_16:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
@@ -8629,7 +8629,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 17:
+ case CPO_REGISTER_17:
switch (sel) {
case 0:
gen_helper_dmfc0_lladdr(arg, cpu_env);
@@ -8649,7 +8649,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 18:
+ case CPO_REGISTER_18:
switch (sel) {
case 0:
case 1:
@@ -8667,7 +8667,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 19:
+ case CPO_REGISTER_19:
switch (sel) {
case 0:
case 1:
@@ -8685,7 +8685,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 20:
+ case CPO_REGISTER_20:
switch (sel) {
case 0:
check_insn(ctx, ISA_MIPS3);
@@ -8696,7 +8696,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 21:
+ case CPO_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
switch (sel) {
@@ -8708,11 +8708,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 22:
+ case CPO_REGISTER_22:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "'Diagnostic"; /* implementation dependent */
break;
- case 23:
+ case CPO_REGISTER_23:
switch (sel) {
case 0:
gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
@@ -8738,7 +8738,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 24:
+ case CPO_REGISTER_24:
switch (sel) {
case 0:
/* EJTAG support */
@@ -8749,7 +8749,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 25:
+ case CPO_REGISTER_25:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
@@ -8787,7 +8787,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 26:
+ case CPO_REGISTER_26:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
@@ -8797,7 +8797,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 27:
+ case CPO_REGISTER_27:
switch (sel) {
/* ignored */
case 0:
@@ -8811,7 +8811,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 28:
+ case CPO_REGISTER_28:
switch (sel) {
case 0:
case 2:
@@ -8831,7 +8831,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 29:
+ case CPO_REGISTER_29:
switch (sel) {
case 0:
case 2:
@@ -8851,7 +8851,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 30:
+ case CPO_REGISTER_30:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
@@ -8861,7 +8861,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 31:
+ case CPO_REGISTER_31:
switch (sel) {
case 0:
/* EJTAG support */
@@ -8906,7 +8906,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
switch (reg) {
- case 0:
+ case CPO_REGISTER_00:
switch (sel) {
case 0:
gen_helper_mtc0_index(cpu_env, arg);
@@ -8936,7 +8936,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 1:
+ case CPO_REGISTER_01:
switch (sel) {
case 0:
/* ignored */
@@ -8981,7 +8981,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 2:
+ case CPO_REGISTER_02:
switch (sel) {
case 0:
gen_helper_dmtc0_entrylo0(cpu_env, arg);
@@ -9026,7 +9026,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 3:
+ case CPO_REGISTER_03:
switch (sel) {
case 0:
gen_helper_dmtc0_entrylo1(cpu_env, arg);
@@ -9041,7 +9041,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 4:
+ case CPO_REGISTER_04:
switch (sel) {
case 0:
gen_helper_mtc0_context(cpu_env, arg);
@@ -9061,7 +9061,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 5:
+ case CPO_REGISTER_05:
switch (sel) {
case 0:
gen_helper_mtc0_pagemask(cpu_env, arg);
@@ -9106,7 +9106,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 6:
+ case CPO_REGISTER_06:
switch (sel) {
case 0:
gen_helper_mtc0_wired(cpu_env, arg);
@@ -9146,7 +9146,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 7:
+ case CPO_REGISTER_07:
switch (sel) {
case 0:
check_insn(ctx, ISA_MIPS32R2);
@@ -9158,7 +9158,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 8:
+ case CPO_REGISTER_08:
switch (sel) {
case 0:
/* ignored */
@@ -9180,7 +9180,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 9:
+ case CPO_REGISTER_09:
switch (sel) {
case 0:
gen_helper_mtc0_count(cpu_env, arg);
@@ -9193,7 +9193,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 10:
+ case CPO_REGISTER_10:
switch (sel) {
case 0:
gen_helper_mtc0_entryhi(cpu_env, arg);
@@ -9203,7 +9203,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 11:
+ case CPO_REGISTER_11:
switch (sel) {
case 0:
gen_helper_mtc0_compare(cpu_env, arg);
@@ -9216,7 +9216,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 12:
+ case CPO_REGISTER_12:
switch (sel) {
case 0:
save_cpu_state(ctx, 1);
@@ -9251,7 +9251,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 13:
+ case CPO_REGISTER_13:
switch (sel) {
case 0:
save_cpu_state(ctx, 1);
@@ -9267,7 +9267,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 14:
+ case CPO_REGISTER_14:
switch (sel) {
case 0:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
@@ -9277,7 +9277,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 15:
+ case CPO_REGISTER_15:
switch (sel) {
case 0:
/* ignored */
@@ -9292,7 +9292,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 16:
+ case CPO_REGISTER_16:
switch (sel) {
case 0:
gen_helper_mtc0_config0(cpu_env, arg);
@@ -9332,7 +9332,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 17:
+ case CPO_REGISTER_17:
switch (sel) {
case 0:
gen_helper_mtc0_lladdr(cpu_env, arg);
@@ -9352,7 +9352,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 18:
+ case CPO_REGISTER_18:
switch (sel) {
case 0:
case 1:
@@ -9370,7 +9370,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 19:
+ case CPO_REGISTER_19:
switch (sel) {
case 0:
case 1:
@@ -9388,7 +9388,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 20:
+ case CPO_REGISTER_20:
switch (sel) {
case 0:
check_insn(ctx, ISA_MIPS3);
@@ -9399,7 +9399,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 21:
+ case CPO_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
switch (sel) {
@@ -9411,11 +9411,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 22:
+ case CPO_REGISTER_22:
/* ignored */
rn = "Diagnostic"; /* implementation dependent */
break;
- case 23:
+ case CPO_REGISTER_23:
switch (sel) {
case 0:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
@@ -9452,7 +9452,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 24:
+ case CPO_REGISTER_24:
switch (sel) {
case 0:
/* EJTAG support */
@@ -9463,7 +9463,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 25:
+ case CPO_REGISTER_25:
switch (sel) {
case 0:
gen_helper_mtc0_performance0(cpu_env, arg);
@@ -9501,7 +9501,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 26:
+ case CPO_REGISTER_26:
switch (sel) {
case 0:
gen_helper_mtc0_errctl(cpu_env, arg);
@@ -9512,7 +9512,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 27:
+ case CPO_REGISTER_27:
switch (sel) {
case 0:
case 1:
@@ -9525,7 +9525,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 28:
+ case CPO_REGISTER_28:
switch (sel) {
case 0:
case 2:
@@ -9545,7 +9545,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 29:
+ case CPO_REGISTER_29:
switch (sel) {
case 0:
case 2:
@@ -9566,7 +9566,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 30:
+ case CPO_REGISTER_30:
switch (sel) {
case 0:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
@@ -9576,7 +9576,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case 31:
+ case CPO_REGISTER_31:
switch (sel) {
case 0:
/* EJTAG support */
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PULL v2 04/12] target/mips: Add fields for SAARI and SAAR CP0 registers
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
` (2 preceding siblings ...)
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 03/12] target/mips: Use " Aleksandar Markovic
@ 2019-01-18 16:59 ` Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 05/12] target/mips: Provide R/W access to " Aleksandar Markovic
` (8 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-01-18 16:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Yongbok Kim <yongbok.kim@mips.com>
Add fields for SAARI and SAAR CP0 registers.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 10 ++++++++--
target/mips/machine.c | 6 ++++--
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index b095422..1c2c682 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -164,8 +164,8 @@ typedef struct mips_def_t mips_def_t;
* 3 BadInstrX
* 4 GuestCtl1 GuestCtl0Ext
* 5 GuestCtl2
- * 6 GuestCtl3
- * 7
+ * 6 SAARI GuestCtl3
+ * 7 SAAR
*
*
* Register 12 Register 13 Register 14 Register 15
@@ -546,6 +546,12 @@ struct CPUMIPSState {
* CP0 Register 9
*/
int32_t CP0_Count;
+ uint32_t CP0_SAARI;
+#define CP0SAARI_TARGET 0 /* 5..0 */
+ uint64_t CP0_SAAR[2];
+#define CP0SAAR_BASE 12 /* 43..12 */
+#define CP0SAAR_SIZE 1 /* 5..1 */
+#define CP0SAAR_EN 0
/*
* CP0 Register 10
*/
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 704e9c0..111d7c3 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
- .version_id = 15,
- .minimum_version_id = 15,
+ .version_id = 16,
+ .minimum_version_id = 16,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
/* Active TC */
@@ -274,6 +274,8 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
VMSTATE_INT32(env.CP0_Count, MIPSCPU),
+ VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
+ VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
VMSTATE_INT32(env.CP0_Status, MIPSCPU),
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PULL v2 05/12] target/mips: Provide R/W access to SAARI and SAAR CP0 registers
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
` (3 preceding siblings ...)
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 04/12] target/mips: Add fields for SAARI and SAAR " Aleksandar Markovic
@ 2019-01-18 16:59 ` Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 06/12] target/mips: Add field and R/W access to ITU control register ICR0 Aleksandar Markovic
` (7 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-01-18 16:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Yongbok Kim <yongbok.kim@mips.com>
Provide R/W access to SAARI and SAAR CP0 registers.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 1 +
target/mips/helper.h | 6 +++++
target/mips/internal.h | 1 +
target/mips/op_helper.c | 50 +++++++++++++++++++++++++++++++++++++
target/mips/translate.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++---
5 files changed, 120 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 1c2c682..185702d 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -901,6 +901,7 @@ struct CPUMIPSState {
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
uint64_t insn_flags; /* Supported instruction set */
+ int saarp;
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
diff --git a/target/mips/helper.h b/target/mips/helper.h
index c23e4e5..8872c46 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -65,6 +65,8 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env)
DEF_HELPER_1(mfc0_tcschefback, tl, env)
DEF_HELPER_1(mftc0_tcschefback, tl, env)
DEF_HELPER_1(mfc0_count, tl, env)
+DEF_HELPER_1(mfc0_saar, tl, env)
+DEF_HELPER_1(mfhc0_saar, tl, env)
DEF_HELPER_1(mftc0_entryhi, tl, env)
DEF_HELPER_1(mftc0_status, tl, env)
DEF_HELPER_1(mftc0_cause, tl, env)
@@ -87,6 +89,7 @@ DEF_HELPER_1(dmfc0_tcschefback, tl, env)
DEF_HELPER_1(dmfc0_lladdr, tl, env)
DEF_HELPER_1(dmfc0_maar, tl, env)
DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
+DEF_HELPER_1(dmfc0_saar, tl, env)
#endif /* TARGET_MIPS64 */
DEF_HELPER_2(mtc0_index, void, env, tl)
@@ -131,6 +134,9 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl)
DEF_HELPER_2(mtc0_hwrena, void, env, tl)
DEF_HELPER_2(mtc0_pwctl, void, env, tl)
DEF_HELPER_2(mtc0_count, void, env, tl)
+DEF_HELPER_2(mtc0_saari, void, env, tl)
+DEF_HELPER_2(mtc0_saar, void, env, tl)
+DEF_HELPER_2(mthc0_saar, void, env, tl)
DEF_HELPER_2(mtc0_entryhi, void, env, tl)
DEF_HELPER_2(mttc0_entryhi, void, env, tl)
DEF_HELPER_2(mtc0_compare, void, env, tl)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 8b1b245..8f6fc91 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -61,6 +61,7 @@ struct mips_def_t {
target_ulong CP0_EBaseWG_rw_bitmask;
uint64_t insn_flags;
enum mips_mmu_types mmu_type;
+ int32_t SAARP;
};
extern const struct mips_def_t mips_defs[];
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index d1f1d1a..409c136 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -938,6 +938,22 @@ target_ulong helper_mfc0_count(CPUMIPSState *env)
return count;
}
+target_ulong helper_mfc0_saar(CPUMIPSState *env)
+{
+ if ((env->CP0_SAARI & 0x3f) < 2) {
+ return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
+ }
+ return 0;
+}
+
+target_ulong helper_mfhc0_saar(CPUMIPSState *env)
+{
+ if ((env->CP0_SAARI & 0x3f) < 2) {
+ return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
+ }
+ return 0;
+}
+
target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
@@ -1059,6 +1075,14 @@ target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
{
return env->CP0_WatchLo[sel];
}
+
+target_ulong helper_dmfc0_saar(CPUMIPSState *env)
+{
+ if ((env->CP0_SAARI & 0x3f) < 2) {
+ return env->CP0_SAAR[env->CP0_SAARI & 0x3f];
+ }
+ return 0;
+}
#endif /* TARGET_MIPS64 */
void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
@@ -1598,6 +1622,32 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
qemu_mutex_unlock_iothread();
}
+void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1)
+{
+ uint32_t target = arg1 & 0x3f;
+ if (target <= 1) {
+ env->CP0_SAARI = target;
+ }
+}
+
+void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
+{
+ uint32_t target = env->CP0_SAARI & 0x3f;
+ if (target < 2) {
+ env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
+ }
+}
+
+void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
+{
+ uint32_t target = env->CP0_SAARI & 0x3f;
+ if (target < 2) {
+ env->CP0_SAAR[target] =
+ (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
+ (env->CP0_SAAR[target] & 0x00000000ffffffffULL);
+ }
+}
+
void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
{
target_ulong old, val, mask;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 827d0f7..00cbbf7 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2537,6 +2537,7 @@ typedef struct DisasContext {
bool mrp;
bool nan2008;
bool abs2008;
+ bool saar;
} DisasContext;
#define DISAS_STOP DISAS_TARGET_0
@@ -6592,6 +6593,17 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
+ case CPO_REGISTER_09:
+ switch (sel) {
+ case 7:
+ CP0_CHECK(ctx->saar);
+ gen_helper_mfhc0_saar(arg, cpu_env);
+ rn = "SAAR";
+ break;
+ default:
+ goto cp0_unimplemented;
+ }
+ break;
case CPO_REGISTER_17:
switch (sel) {
case 0:
@@ -6662,6 +6674,16 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
+ case CPO_REGISTER_09:
+ switch (sel) {
+ case 7:
+ CP0_CHECK(ctx->saar);
+ gen_helper_mthc0_saar(cpu_env, arg);
+ rn = "SAAR";
+ break;
+ default:
+ goto cp0_unimplemented;
+ }
case CPO_REGISTER_17:
switch (sel) {
case 0:
@@ -7048,7 +7070,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
rn = "Count";
break;
- /* 6,7 are implementation dependent */
+ case 6:
+ CP0_CHECK(ctx->saar);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
+ rn = "SAARI";
+ break;
+ case 7:
+ CP0_CHECK(ctx->saar);
+ gen_helper_mfc0_saar(arg, cpu_env);
+ rn = "SAAR";
+ break;
default:
goto cp0_unimplemented;
}
@@ -7753,7 +7784,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_count(cpu_env, arg);
rn = "Count";
break;
- /* 6,7 are implementation dependent */
+ case 6:
+ CP0_CHECK(ctx->saar);
+ gen_helper_mtc0_saari(cpu_env, arg);
+ rn = "SAARI";
+ break;
+ case 7:
+ CP0_CHECK(ctx->saar);
+ gen_helper_mtc0_saar(cpu_env, arg);
+ rn = "SAAR";
+ break;
default:
goto cp0_unimplemented;
}
@@ -8498,7 +8538,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
rn = "Count";
break;
- /* 6,7 are implementation dependent */
+ case 6:
+ CP0_CHECK(ctx->saar);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
+ rn = "SAARI";
+ break;
+ case 7:
+ CP0_CHECK(ctx->saar);
+ gen_helper_dmfc0_saar(arg, cpu_env);
+ rn = "SAAR";
+ break;
default:
goto cp0_unimplemented;
}
@@ -9186,7 +9235,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_count(cpu_env, arg);
rn = "Count";
break;
- /* 6,7 are implementation dependent */
+ case 6:
+ CP0_CHECK(ctx->saar);
+ gen_helper_mtc0_saari(cpu_env, arg);
+ rn = "SAARI";
+ break;
+ case 7:
+ CP0_CHECK(ctx->saar);
+ gen_helper_mtc0_saar(cpu_env, arg);
+ rn = "SAAR";
+ break;
default:
goto cp0_unimplemented;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PULL v2 06/12] target/mips: Add field and R/W access to ITU control register ICR0
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
` (4 preceding siblings ...)
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 05/12] target/mips: Provide R/W access to " Aleksandar Markovic
@ 2019-01-18 16:59 ` Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers Aleksandar Markovic
` (6 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-01-18 16:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Yongbok Kim <yongbok.kim@mips.com>
Add field and R/W access to ITU control register ICR0.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
hw/misc/mips_itu.c | 22 +++++++++++++++++++++-
include/hw/misc/mips_itu.h | 4 ++++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
index 43bbec4..4801958 100644
--- a/hw/misc/mips_itu.c
+++ b/hw/misc/mips_itu.c
@@ -55,9 +55,17 @@ typedef enum ITCView {
ITCVIEW_EF_SYNC = 2,
ITCVIEW_EF_TRY = 3,
ITCVIEW_PV_SYNC = 4,
- ITCVIEW_PV_TRY = 5
+ ITCVIEW_PV_TRY = 5,
+ ITCVIEW_PV_ICR0 = 15,
} ITCView;
+#define ITC_ICR0_CELL_NUM 16
+#define ITC_ICR0_BLK_GRAIN 8
+#define ITC_ICR0_BLK_GRAIN_MASK 0x7
+#define ITC_ICR0_ERR_AXI 2
+#define ITC_ICR0_ERR_PARITY 1
+#define ITC_ICR0_ERR_EXEC 0
+
MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
{
return &itu->tag_io;
@@ -382,6 +390,9 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
case ITCVIEW_PV_TRY:
ret = view_pv_try_read(cell);
break;
+ case ITCVIEW_PV_ICR0:
+ ret = s->icr0;
+ break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"itc_storage_read: Bad ITC View %d\n", (int)view);
@@ -417,6 +428,15 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
case ITCVIEW_PV_TRY:
view_pv_try_write(cell);
break;
+ case ITCVIEW_PV_ICR0:
+ if (data & 0x7) {
+ /* clear ERROR bits */
+ s->icr0 &= ~(data & 0x7);
+ }
+ /* set BLK_GRAIN */
+ s->icr0 &= ~0x700;
+ s->icr0 |= data & 0x700;
+ break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"itc_storage_write: Bad ITC View %d\n", (int)view);
diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h
index 030eb4a..45a0c51 100644
--- a/include/hw/misc/mips_itu.h
+++ b/include/hw/misc/mips_itu.h
@@ -66,6 +66,10 @@ typedef struct MIPSITUState {
/* ITC Configuration Tags */
uint64_t ITCAddressMap[ITC_ADDRESSMAP_NUM];
MemoryRegion tag_io;
+
+ /* ITU Control Register */
+ uint64_t icr0;
+
} MIPSITUState;
/* Get ITC Configuration Tag memory region. */
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PULL v2 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
` (5 preceding siblings ...)
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 06/12] target/mips: Add field and R/W access to ITU control register ICR0 Aleksandar Markovic
@ 2019-01-18 16:59 ` Aleksandar Markovic
2019-02-14 18:40 ` Peter Maydell
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 08/12] target/mips: Update ITU to handle bus errors Aleksandar Markovic
` (5 subsequent siblings)
12 siblings, 1 reply; 18+ messages in thread
From: Aleksandar Markovic @ 2019-01-18 16:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Yongbok Kim <yongbok.kim@mips.com>
Update ITU to utilize SAARI and SAAR CP0 registers.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
hw/mips/cps.c | 8 ++++++++
hw/misc/mips_itu.c | 29 +++++++++++++++++++++++------
include/hw/misc/mips_itu.h | 4 ++++
target/mips/cpu.h | 5 +++++
target/mips/op_helper.c | 14 ++++++++++++++
5 files changed, 54 insertions(+), 6 deletions(-)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 4285d19..fc97f59 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -69,6 +69,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
Error *err = NULL;
target_ulong gcr_base;
bool itu_present = false;
+ bool saar_present = false;
for (i = 0; i < s->num_vp; i++) {
cpu = MIPS_CPU(cpu_create(s->cpu_type));
@@ -82,12 +83,14 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
itu_present = true;
/* Attach ITC Tag to the VP */
env->itc_tag = mips_itu_get_tag_region(&s->itu);
+ env->itu = &s->itu;
}
qemu_register_reset(main_cpu_reset, cpu);
}
cpu = MIPS_CPU(first_cpu);
env = &cpu->env;
+ saar_present = (bool)env->saarp;
/* Inter-Thread Communication Unit */
if (itu_present) {
@@ -96,6 +99,11 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);
object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err);
+ object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present",
+ &err);
+ if (saar_present) {
+ qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_SAAR);
+ }
object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
index 4801958..ee1addc 100644
--- a/hw/misc/mips_itu.c
+++ b/hw/misc/mips_itu.c
@@ -84,7 +84,7 @@ static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size)
return tag->ITCAddressMap[index];
}
-static void itc_reconfigure(MIPSITUState *tag)
+void itc_reconfigure(MIPSITUState *tag)
{
uint64_t *am = &tag->ITCAddressMap[0];
MemoryRegion *mr = &tag->storage_io;
@@ -92,6 +92,12 @@ static void itc_reconfigure(MIPSITUState *tag)
uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
+ if (tag->saar_present) {
+ address = ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4;
+ size = 1 << ((*(uint64_t *) tag->saar >> 1) & 0x1f);
+ is_enabled = *(uint64_t *) tag->saar & 1;
+ }
+
memory_region_transaction_begin();
if (!(size & (size - 1))) {
memory_region_set_size(mr, size);
@@ -150,7 +156,12 @@ static inline ITCView get_itc_view(hwaddr addr)
static inline int get_cell_stride_shift(const MIPSITUState *s)
{
/* Minimum interval (for EntryGain = 0) is 128 B */
- return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
+ if (s->saar_present) {
+ return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) &
+ ITC_ICR0_BLK_GRAIN_MASK);
+ } else {
+ return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
+ }
}
static inline ITCStorageCell *get_cell(MIPSITUState *s,
@@ -499,10 +510,15 @@ static void mips_itu_reset(DeviceState *dev)
{
MIPSITUState *s = MIPS_ITU(dev);
- s->ITCAddressMap[0] = 0;
- s->ITCAddressMap[1] =
- ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
- (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
+ if (s->saar_present) {
+ *(uint64_t *) s->saar = 0x11 << 1;
+ s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM;
+ } else {
+ s->ITCAddressMap[0] = 0;
+ s->ITCAddressMap[1] =
+ ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
+ (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
+ }
itc_reconfigure(s);
itc_reset_cells(s);
@@ -513,6 +529,7 @@ static Property mips_itu_properties[] = {
ITC_FIFO_NUM_MAX),
DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores,
ITC_SEMAPH_NUM_MAX),
+ DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h
index 45a0c51..c44e767 100644
--- a/include/hw/misc/mips_itu.h
+++ b/include/hw/misc/mips_itu.h
@@ -70,6 +70,10 @@ typedef struct MIPSITUState {
/* ITU Control Register */
uint64_t icr0;
+ /* SAAR */
+ bool saar_present;
+ void *saar;
+
} MIPSITUState;
/* Get ITC Configuration Tag memory region. */
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 185702d..48e86d1 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -326,6 +326,7 @@ struct TCState {
};
+struct MIPSITUState;
typedef struct CPUMIPSState CPUMIPSState;
struct CPUMIPSState {
TCState active_tc;
@@ -917,6 +918,7 @@ struct CPUMIPSState {
const mips_def_t *cpu_model;
void *irq[8];
QEMUTimer *timer; /* Internal timer */
+ struct MIPSITUState *itu;
MemoryRegion *itc_tag; /* ITC Configuration Tags */
target_ulong exception_base; /* ExceptionBase input to the core */
};
@@ -1059,6 +1061,9 @@ void cpu_set_exception_base(int vp_index, target_ulong address);
/* mips_int.c */
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
+/* mips_itu.c */
+void itc_reconfigure(struct MIPSITUState *tag);
+
/* helper.c */
target_ulong exception_resume_pc (CPUMIPSState *env);
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 409c136..aebad24 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1635,6 +1635,13 @@ void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
uint32_t target = env->CP0_SAARI & 0x3f;
if (target < 2) {
env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
+ switch (target) {
+ case 0:
+ if (env->itu) {
+ itc_reconfigure(env->itu);
+ }
+ break;
+ }
}
}
@@ -1645,6 +1652,13 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
env->CP0_SAAR[target] =
(((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
(env->CP0_SAAR[target] & 0x00000000ffffffffULL);
+ switch (target) {
+ case 0:
+ if (env->itu) {
+ itc_reconfigure(env->itu);
+ }
+ break;
+ }
}
}
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PULL v2 08/12] target/mips: Update ITU to handle bus errors
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
` (6 preceding siblings ...)
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers Aleksandar Markovic
@ 2019-01-18 16:59 ` Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 09/12] target/mips: Amend preprocessor constants for CP0 registers Aleksandar Markovic
` (4 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-01-18 16:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Yongbok Kim <yongbok.kim@mips.com>
Update ITU to handle bus errors.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
hw/misc/mips_itu.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
index ee1addc..1257d8f 100644
--- a/hw/misc/mips_itu.c
+++ b/hw/misc/mips_itu.c
@@ -375,6 +375,12 @@ static void view_pv_try_write(ITCStorageCell *c)
view_pv_common_write(c);
}
+static void raise_exception(int excp)
+{
+ current_cpu->exception_index = excp;
+ cpu_loop_exit(current_cpu);
+}
+
static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
{
MIPSITUState *s = (MIPSITUState *)opaque;
@@ -382,6 +388,14 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
ITCView view = get_itc_view(addr);
uint64_t ret = -1;
+ switch (size) {
+ case 1:
+ case 2:
+ s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
+ raise_exception(EXCP_DBE);
+ return 0;
+ }
+
switch (view) {
case ITCVIEW_BYPASS:
ret = view_bypass_read(cell);
@@ -420,6 +434,14 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
ITCStorageCell *cell = get_cell(s, addr);
ITCView view = get_itc_view(addr);
+ switch (size) {
+ case 1:
+ case 2:
+ s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
+ raise_exception(EXCP_DBE);
+ return;
+ }
+
switch (view) {
case ITCVIEW_BYPASS:
view_bypass_write(cell, data);
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PULL v2 09/12] target/mips: Amend preprocessor constants for CP0 registers
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
` (7 preceding siblings ...)
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 08/12] target/mips: Update ITU to handle bus errors Aleksandar Markovic
@ 2019-01-18 16:59 ` Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 10/12] target/mips: Add CP0 register MemoryMapID Aleksandar Markovic
` (3 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-01-18 16:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Correct existing CP0-related preprocessor constants (replace
"CPO" with "CP0" (form letter "O" to digit "0", when needed).
Besides, add preprocessor constants for CP0 subregisters.
The names of the subregisters were chosen to be in sync with
the table of corresponding assembler mnemonics found in the
documentation for I6500 and I6400 (release 1.0).
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 178 +++++++++++++++++++++++++------
target/mips/translate.c | 276 ++++++++++++++++++++++++------------------------
2 files changed, 284 insertions(+), 170 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 48e86d1..a5381b7 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -233,38 +233,152 @@ typedef struct mips_def_t mips_def_t;
* 7 TagLo TagHi KScratch<n>
*
*/
-#define CPO_REGISTER_00 0
-#define CPO_REGISTER_01 1
-#define CPO_REGISTER_02 2
-#define CPO_REGISTER_03 3
-#define CPO_REGISTER_04 4
-#define CPO_REGISTER_05 5
-#define CPO_REGISTER_06 6
-#define CPO_REGISTER_07 7
-#define CPO_REGISTER_08 8
-#define CPO_REGISTER_09 9
-#define CPO_REGISTER_10 10
-#define CPO_REGISTER_11 11
-#define CPO_REGISTER_12 12
-#define CPO_REGISTER_13 13
-#define CPO_REGISTER_14 14
-#define CPO_REGISTER_15 15
-#define CPO_REGISTER_16 16
-#define CPO_REGISTER_17 17
-#define CPO_REGISTER_18 18
-#define CPO_REGISTER_19 19
-#define CPO_REGISTER_20 20
-#define CPO_REGISTER_21 21
-#define CPO_REGISTER_22 22
-#define CPO_REGISTER_23 23
-#define CPO_REGISTER_24 24
-#define CPO_REGISTER_25 25
-#define CPO_REGISTER_26 26
-#define CPO_REGISTER_27 27
-#define CPO_REGISTER_28 28
-#define CPO_REGISTER_29 29
-#define CPO_REGISTER_30 30
-#define CPO_REGISTER_31 31
+#define CP0_REGISTER_00 0
+#define CP0_REGISTER_01 1
+#define CP0_REGISTER_02 2
+#define CP0_REGISTER_03 3
+#define CP0_REGISTER_04 4
+#define CP0_REGISTER_05 5
+#define CP0_REGISTER_06 6
+#define CP0_REGISTER_07 7
+#define CP0_REGISTER_08 8
+#define CP0_REGISTER_09 9
+#define CP0_REGISTER_10 10
+#define CP0_REGISTER_11 11
+#define CP0_REGISTER_12 12
+#define CP0_REGISTER_13 13
+#define CP0_REGISTER_14 14
+#define CP0_REGISTER_15 15
+#define CP0_REGISTER_16 16
+#define CP0_REGISTER_17 17
+#define CP0_REGISTER_18 18
+#define CP0_REGISTER_19 19
+#define CP0_REGISTER_20 20
+#define CP0_REGISTER_21 21
+#define CP0_REGISTER_22 22
+#define CP0_REGISTER_23 23
+#define CP0_REGISTER_24 24
+#define CP0_REGISTER_25 25
+#define CP0_REGISTER_26 26
+#define CP0_REGISTER_27 27
+#define CP0_REGISTER_28 28
+#define CP0_REGISTER_29 29
+#define CP0_REGISTER_30 30
+#define CP0_REGISTER_31 31
+
+
+/* CP0 Register 00 */
+#define CP0_REG00__INDEX 0
+#define CP0_REG00__VPCONTROL 4
+/* CP0 Register 01 */
+/* CP0 Register 02 */
+#define CP0_REG02__ENTRYLO0 0
+/* CP0 Register 03 */
+#define CP0_REG03__ENTRYLO1 0
+#define CP0_REG03__GLOBALNUM 1
+/* CP0 Register 04 */
+#define CP0_REG04__CONTEXT 0
+#define CP0_REG04__USERLOCAL 2
+#define CP0_REG04__DBGCONTEXTID 4
+#define CP0_REG00__MMID 5
+/* CP0 Register 05 */
+#define CP0_REG05__PAGEMASK 0
+#define CP0_REG05__PAGEGRAIN 1
+/* CP0 Register 06 */
+#define CP0_REG06__WIRED 0
+/* CP0 Register 07 */
+#define CP0_REG07__HWRENA 0
+/* CP0 Register 08 */
+#define CP0_REG08__BADVADDR 0
+#define CP0_REG08__BADINSTR 1
+#define CP0_REG08__BADINSTRP 2
+/* CP0 Register 09 */
+#define CP0_REG09__COUNT 0
+#define CP0_REG09__SAARI 6
+#define CP0_REG09__SAAR 7
+/* CP0 Register 10 */
+#define CP0_REG10__ENTRYHI 0
+#define CP0_REG10__GUESTCTL1 4
+#define CP0_REG10__GUESTCTL2 5
+/* CP0 Register 11 */
+#define CP0_REG11__COMPARE 0
+#define CP0_REG11__GUESTCTL0EXT 4
+/* CP0 Register 12 */
+#define CP0_REG12__STATUS 0
+#define CP0_REG12__INTCTL 1
+#define CP0_REG12__SRSCTL 2
+#define CP0_REG12__GUESTCTL0 6
+#define CP0_REG12__GTOFFSET 7
+/* CP0 Register 13 */
+#define CP0_REG13__CAUSE 0
+/* CP0 Register 14 */
+#define CP0_REG14__EPC 0
+/* CP0 Register 15 */
+#define CP0_REG15__PRID 0
+#define CP0_REG15__EBASE 1
+#define CP0_REG15__CDMMBASE 2
+#define CP0_REG15__CMGCRBASE 3
+/* CP0 Register 16 */
+#define CP0_REG16__CONFIG 0
+#define CP0_REG16__CONFIG1 1
+#define CP0_REG16__CONFIG2 2
+#define CP0_REG16__CONFIG3 3
+#define CP0_REG16__CONFIG4 4
+#define CP0_REG16__CONFIG5 5
+#define CP0_REG00__CONFIG7 7
+/* CP0 Register 17 */
+#define CP0_REG17__LLADDR 0
+#define CP0_REG17__MAAR 1
+#define CP0_REG17__MAARI 2
+/* CP0 Register 18 */
+#define CP0_REG18__WATCHLO0 0
+#define CP0_REG18__WATCHLO1 1
+#define CP0_REG18__WATCHLO2 2
+#define CP0_REG18__WATCHLO3 3
+/* CP0 Register 19 */
+#define CP0_REG19__WATCHHI0 0
+#define CP0_REG19__WATCHHI1 1
+#define CP0_REG19__WATCHHI2 2
+#define CP0_REG19__WATCHHI3 3
+/* CP0 Register 20 */
+#define CP0_REG20__XCONTEXT 0
+/* CP0 Register 21 */
+/* CP0 Register 22 */
+/* CP0 Register 23 */
+#define CP0_REG23__DEBUG 0
+/* CP0 Register 24 */
+#define CP0_REG24__DEPC 0
+/* CP0 Register 25 */
+#define CP0_REG25__PERFCTL0 0
+#define CP0_REG25__PERFCNT0 1
+#define CP0_REG25__PERFCTL1 2
+#define CP0_REG25__PERFCNT1 3
+#define CP0_REG25__PERFCTL2 4
+#define CP0_REG25__PERFCNT2 5
+#define CP0_REG25__PERFCTL3 6
+#define CP0_REG25__PERFCNT3 7
+/* CP0 Register 26 */
+#define CP0_REG00__ERRCTL 0
+/* CP0 Register 27 */
+#define CP0_REG27__CACHERR 0
+/* CP0 Register 28 */
+#define CP0_REG28__ITAGLO 0
+#define CP0_REG28__IDATALO 1
+#define CP0_REG28__DTAGLO 2
+#define CP0_REG28__DDATALO 3
+/* CP0 Register 29 */
+#define CP0_REG29__IDATAHI 1
+#define CP0_REG29__DDATAHI 3
+/* CP0 Register 30 */
+#define CP0_REG30__ERROREPC 0
+/* CP0 Register 31 */
+#define CP0_REG31__DESAVE 0
+#define CP0_REG31__KSCRATCH1 2
+#define CP0_REG31__KSCRATCH2 3
+#define CP0_REG31__KSCRATCH3 4
+#define CP0_REG31__KSCRATCH4 5
+#define CP0_REG31__KSCRATCH5 6
+#define CP0_REG31__KSCRATCH6 7
typedef struct TCState TCState;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 00cbbf7..2259d44 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6571,7 +6571,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *rn = "invalid";
switch (reg) {
- case CPO_REGISTER_02:
+ case CP0_REGISTER_02:
switch (sel) {
case 0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
@@ -6582,7 +6582,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_03:
+ case CP0_REGISTER_03:
switch (sel) {
case 0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
@@ -6593,7 +6593,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_09:
+ case CP0_REGISTER_09:
switch (sel) {
case 7:
CP0_CHECK(ctx->saar);
@@ -6604,7 +6604,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_17:
+ case CP0_REGISTER_17:
switch (sel) {
case 0:
gen_mfhc0_load64(arg, offsetof(CPUMIPSState, lladdr),
@@ -6620,7 +6620,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_28:
+ case CP0_REGISTER_28:
switch (sel) {
case 0:
case 2:
@@ -6650,7 +6650,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
uint64_t mask = ctx->PAMask >> 36;
switch (reg) {
- case CPO_REGISTER_02:
+ case CP0_REGISTER_02:
switch (sel) {
case 0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
@@ -6662,7 +6662,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_03:
+ case CP0_REGISTER_03:
switch (sel) {
case 0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
@@ -6674,7 +6674,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_09:
+ case CP0_REGISTER_09:
switch (sel) {
case 7:
CP0_CHECK(ctx->saar);
@@ -6684,7 +6684,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
- case CPO_REGISTER_17:
+ case CP0_REGISTER_17:
switch (sel) {
case 0:
/* LLAddr is read-only (the only exception is bit 0 if LLB is
@@ -6702,7 +6702,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_28:
+ case CP0_REGISTER_28:
switch (sel) {
case 0:
case 2:
@@ -6742,7 +6742,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
check_insn(ctx, ISA_MIPS32);
switch (reg) {
- case CPO_REGISTER_00:
+ case CP0_REGISTER_00:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
@@ -6772,7 +6772,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_01:
+ case CP0_REGISTER_01:
switch (sel) {
case 0:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
@@ -6818,7 +6818,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_02:
+ case CP0_REGISTER_02:
switch (sel) {
case 0:
{
@@ -6876,7 +6876,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_03:
+ case CP0_REGISTER_03:
switch (sel) {
case 0:
{
@@ -6904,7 +6904,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_04:
+ case CP0_REGISTER_04:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
@@ -6926,7 +6926,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_05:
+ case CP0_REGISTER_05:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
@@ -6974,7 +6974,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_06:
+ case CP0_REGISTER_06:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
@@ -7014,7 +7014,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_07:
+ case CP0_REGISTER_07:
switch (sel) {
case 0:
check_insn(ctx, ISA_MIPS32R2);
@@ -7025,7 +7025,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_08:
+ case CP0_REGISTER_08:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
@@ -7052,7 +7052,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_09:
+ case CP0_REGISTER_09:
switch (sel) {
case 0:
/* Mark as an IO operation because we read the time. */
@@ -7084,7 +7084,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_10:
+ case CP0_REGISTER_10:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
@@ -7095,7 +7095,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_11:
+ case CP0_REGISTER_11:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
@@ -7106,7 +7106,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_12:
+ case CP0_REGISTER_12:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
@@ -7131,7 +7131,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_13:
+ case CP0_REGISTER_13:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
@@ -7141,7 +7141,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_14:
+ case CP0_REGISTER_14:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
@@ -7152,7 +7152,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_15:
+ case CP0_REGISTER_15:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
@@ -7175,7 +7175,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_16:
+ case CP0_REGISTER_16:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
@@ -7214,7 +7214,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_17:
+ case CP0_REGISTER_17:
switch (sel) {
case 0:
gen_helper_mfc0_lladdr(arg, cpu_env);
@@ -7234,7 +7234,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_18:
+ case CP0_REGISTER_18:
switch (sel) {
case 0:
case 1:
@@ -7252,7 +7252,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_19:
+ case CP0_REGISTER_19:
switch (sel) {
case 0:
case 1:
@@ -7270,7 +7270,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_20:
+ case CP0_REGISTER_20:
switch (sel) {
case 0:
#if defined(TARGET_MIPS64)
@@ -7284,7 +7284,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_21:
+ case CP0_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
switch (sel) {
@@ -7296,11 +7296,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_22:
+ case CP0_REGISTER_22:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "'Diagnostic"; /* implementation dependent */
break;
- case CPO_REGISTER_23:
+ case CP0_REGISTER_23:
switch (sel) {
case 0:
gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
@@ -7326,7 +7326,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_24:
+ case CP0_REGISTER_24:
switch (sel) {
case 0:
/* EJTAG support */
@@ -7338,7 +7338,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_25:
+ case CP0_REGISTER_25:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
@@ -7376,7 +7376,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_26:
+ case CP0_REGISTER_26:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
@@ -7386,7 +7386,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_27:
+ case CP0_REGISTER_27:
switch (sel) {
case 0:
case 1:
@@ -7399,7 +7399,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_28:
+ case CP0_REGISTER_28:
switch (sel) {
case 0:
case 2:
@@ -7424,7 +7424,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_29:
+ case CP0_REGISTER_29:
switch (sel) {
case 0:
case 2:
@@ -7444,7 +7444,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_30:
+ case CP0_REGISTER_30:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
@@ -7455,7 +7455,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_31:
+ case CP0_REGISTER_31:
switch (sel) {
case 0:
/* EJTAG support */
@@ -7501,7 +7501,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
switch (reg) {
- case CPO_REGISTER_00:
+ case CP0_REGISTER_00:
switch (sel) {
case 0:
gen_helper_mtc0_index(cpu_env, arg);
@@ -7531,7 +7531,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_01:
+ case CP0_REGISTER_01:
switch (sel) {
case 0:
/* ignored */
@@ -7578,7 +7578,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_02:
+ case CP0_REGISTER_02:
switch (sel) {
case 0:
gen_helper_mtc0_entrylo0(cpu_env, arg);
@@ -7623,7 +7623,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_03:
+ case CP0_REGISTER_03:
switch (sel) {
case 0:
gen_helper_mtc0_entrylo1(cpu_env, arg);
@@ -7638,7 +7638,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_04:
+ case CP0_REGISTER_04:
switch (sel) {
case 0:
gen_helper_mtc0_context(cpu_env, arg);
@@ -7658,7 +7658,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_05:
+ case CP0_REGISTER_05:
switch (sel) {
case 0:
gen_helper_mtc0_pagemask(cpu_env, arg);
@@ -7704,7 +7704,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_06:
+ case CP0_REGISTER_06:
switch (sel) {
case 0:
gen_helper_mtc0_wired(cpu_env, arg);
@@ -7744,7 +7744,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_07:
+ case CP0_REGISTER_07:
switch (sel) {
case 0:
check_insn(ctx, ISA_MIPS32R2);
@@ -7756,7 +7756,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_08:
+ case CP0_REGISTER_08:
switch (sel) {
case 0:
/* ignored */
@@ -7778,7 +7778,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_09:
+ case CP0_REGISTER_09:
switch (sel) {
case 0:
gen_helper_mtc0_count(cpu_env, arg);
@@ -7798,7 +7798,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_10:
+ case CP0_REGISTER_10:
switch (sel) {
case 0:
gen_helper_mtc0_entryhi(cpu_env, arg);
@@ -7808,7 +7808,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_11:
+ case CP0_REGISTER_11:
switch (sel) {
case 0:
gen_helper_mtc0_compare(cpu_env, arg);
@@ -7819,7 +7819,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_12:
+ case CP0_REGISTER_12:
switch (sel) {
case 0:
save_cpu_state(ctx, 1);
@@ -7854,7 +7854,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_13:
+ case CP0_REGISTER_13:
switch (sel) {
case 0:
save_cpu_state(ctx, 1);
@@ -7870,7 +7870,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_14:
+ case CP0_REGISTER_14:
switch (sel) {
case 0:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
@@ -7880,7 +7880,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_15:
+ case CP0_REGISTER_15:
switch (sel) {
case 0:
/* ignored */
@@ -7895,7 +7895,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_16:
+ case CP0_REGISTER_16:
switch (sel) {
case 0:
gen_helper_mtc0_config0(cpu_env, arg);
@@ -7944,7 +7944,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_17:
+ case CP0_REGISTER_17:
switch (sel) {
case 0:
gen_helper_mtc0_lladdr(cpu_env, arg);
@@ -7964,7 +7964,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_18:
+ case CP0_REGISTER_18:
switch (sel) {
case 0:
case 1:
@@ -7982,7 +7982,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_19:
+ case CP0_REGISTER_19:
switch (sel) {
case 0:
case 1:
@@ -8000,7 +8000,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_20:
+ case CP0_REGISTER_20:
switch (sel) {
case 0:
#if defined(TARGET_MIPS64)
@@ -8013,7 +8013,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_21:
+ case CP0_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
switch (sel) {
@@ -8025,11 +8025,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_22:
+ case CP0_REGISTER_22:
/* ignored */
rn = "Diagnostic"; /* implementation dependent */
break;
- case CPO_REGISTER_23:
+ case CP0_REGISTER_23:
switch (sel) {
case 0:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
@@ -8068,7 +8068,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_24:
+ case CP0_REGISTER_24:
switch (sel) {
case 0:
/* EJTAG support */
@@ -8079,7 +8079,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_25:
+ case CP0_REGISTER_25:
switch (sel) {
case 0:
gen_helper_mtc0_performance0(cpu_env, arg);
@@ -8117,7 +8117,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_26:
+ case CP0_REGISTER_26:
switch (sel) {
case 0:
gen_helper_mtc0_errctl(cpu_env, arg);
@@ -8128,7 +8128,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_27:
+ case CP0_REGISTER_27:
switch (sel) {
case 0:
case 1:
@@ -8141,7 +8141,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_28:
+ case CP0_REGISTER_28:
switch (sel) {
case 0:
case 2:
@@ -8161,7 +8161,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_29:
+ case CP0_REGISTER_29:
switch (sel) {
case 0:
case 2:
@@ -8182,7 +8182,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_30:
+ case CP0_REGISTER_30:
switch (sel) {
case 0:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
@@ -8192,7 +8192,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_31:
+ case CP0_REGISTER_31:
switch (sel) {
case 0:
/* EJTAG support */
@@ -8242,7 +8242,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
check_insn(ctx, ISA_MIPS64);
switch (reg) {
- case CPO_REGISTER_00:
+ case CP0_REGISTER_00:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
@@ -8272,7 +8272,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_01:
+ case CP0_REGISTER_01:
switch (sel) {
case 0:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
@@ -8318,7 +8318,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_02:
+ case CP0_REGISTER_02:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
@@ -8363,7 +8363,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_03:
+ case CP0_REGISTER_03:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
@@ -8378,7 +8378,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_04:
+ case CP0_REGISTER_04:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
@@ -8398,7 +8398,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_05:
+ case CP0_REGISTER_05:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
@@ -8443,7 +8443,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_06:
+ case CP0_REGISTER_06:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
@@ -8483,7 +8483,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_07:
+ case CP0_REGISTER_07:
switch (sel) {
case 0:
check_insn(ctx, ISA_MIPS32R2);
@@ -8494,7 +8494,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_08:
+ case CP0_REGISTER_08:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
@@ -8520,7 +8520,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_09:
+ case CP0_REGISTER_09:
switch (sel) {
case 0:
/* Mark as an IO operation because we read the time. */
@@ -8552,7 +8552,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_10:
+ case CP0_REGISTER_10:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
@@ -8562,7 +8562,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_11:
+ case CP0_REGISTER_11:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
@@ -8573,7 +8573,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_12:
+ case CP0_REGISTER_12:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
@@ -8598,7 +8598,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_13:
+ case CP0_REGISTER_13:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
@@ -8608,7 +8608,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_14:
+ case CP0_REGISTER_14:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
@@ -8618,7 +8618,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_15:
+ case CP0_REGISTER_15:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
@@ -8639,7 +8639,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_16:
+ case CP0_REGISTER_16:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
@@ -8678,7 +8678,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_17:
+ case CP0_REGISTER_17:
switch (sel) {
case 0:
gen_helper_dmfc0_lladdr(arg, cpu_env);
@@ -8698,7 +8698,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_18:
+ case CP0_REGISTER_18:
switch (sel) {
case 0:
case 1:
@@ -8716,7 +8716,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_19:
+ case CP0_REGISTER_19:
switch (sel) {
case 0:
case 1:
@@ -8734,7 +8734,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_20:
+ case CP0_REGISTER_20:
switch (sel) {
case 0:
check_insn(ctx, ISA_MIPS3);
@@ -8745,7 +8745,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_21:
+ case CP0_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
switch (sel) {
@@ -8757,11 +8757,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_22:
+ case CP0_REGISTER_22:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "'Diagnostic"; /* implementation dependent */
break;
- case CPO_REGISTER_23:
+ case CP0_REGISTER_23:
switch (sel) {
case 0:
gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
@@ -8787,7 +8787,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_24:
+ case CP0_REGISTER_24:
switch (sel) {
case 0:
/* EJTAG support */
@@ -8798,7 +8798,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_25:
+ case CP0_REGISTER_25:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
@@ -8836,7 +8836,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_26:
+ case CP0_REGISTER_26:
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
@@ -8846,7 +8846,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_27:
+ case CP0_REGISTER_27:
switch (sel) {
/* ignored */
case 0:
@@ -8860,7 +8860,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_28:
+ case CP0_REGISTER_28:
switch (sel) {
case 0:
case 2:
@@ -8880,7 +8880,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_29:
+ case CP0_REGISTER_29:
switch (sel) {
case 0:
case 2:
@@ -8900,7 +8900,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_30:
+ case CP0_REGISTER_30:
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
@@ -8910,7 +8910,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_31:
+ case CP0_REGISTER_31:
switch (sel) {
case 0:
/* EJTAG support */
@@ -8955,7 +8955,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
switch (reg) {
- case CPO_REGISTER_00:
+ case CP0_REGISTER_00:
switch (sel) {
case 0:
gen_helper_mtc0_index(cpu_env, arg);
@@ -8985,7 +8985,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_01:
+ case CP0_REGISTER_01:
switch (sel) {
case 0:
/* ignored */
@@ -9030,7 +9030,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_02:
+ case CP0_REGISTER_02:
switch (sel) {
case 0:
gen_helper_dmtc0_entrylo0(cpu_env, arg);
@@ -9075,7 +9075,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_03:
+ case CP0_REGISTER_03:
switch (sel) {
case 0:
gen_helper_dmtc0_entrylo1(cpu_env, arg);
@@ -9090,7 +9090,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_04:
+ case CP0_REGISTER_04:
switch (sel) {
case 0:
gen_helper_mtc0_context(cpu_env, arg);
@@ -9110,7 +9110,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_05:
+ case CP0_REGISTER_05:
switch (sel) {
case 0:
gen_helper_mtc0_pagemask(cpu_env, arg);
@@ -9155,7 +9155,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_06:
+ case CP0_REGISTER_06:
switch (sel) {
case 0:
gen_helper_mtc0_wired(cpu_env, arg);
@@ -9195,7 +9195,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_07:
+ case CP0_REGISTER_07:
switch (sel) {
case 0:
check_insn(ctx, ISA_MIPS32R2);
@@ -9207,7 +9207,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_08:
+ case CP0_REGISTER_08:
switch (sel) {
case 0:
/* ignored */
@@ -9229,7 +9229,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_09:
+ case CP0_REGISTER_09:
switch (sel) {
case 0:
gen_helper_mtc0_count(cpu_env, arg);
@@ -9251,7 +9251,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case CPO_REGISTER_10:
+ case CP0_REGISTER_10:
switch (sel) {
case 0:
gen_helper_mtc0_entryhi(cpu_env, arg);
@@ -9261,7 +9261,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_11:
+ case CP0_REGISTER_11:
switch (sel) {
case 0:
gen_helper_mtc0_compare(cpu_env, arg);
@@ -9274,7 +9274,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case CPO_REGISTER_12:
+ case CP0_REGISTER_12:
switch (sel) {
case 0:
save_cpu_state(ctx, 1);
@@ -9309,7 +9309,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_13:
+ case CP0_REGISTER_13:
switch (sel) {
case 0:
save_cpu_state(ctx, 1);
@@ -9325,7 +9325,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_14:
+ case CP0_REGISTER_14:
switch (sel) {
case 0:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
@@ -9335,7 +9335,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_15:
+ case CP0_REGISTER_15:
switch (sel) {
case 0:
/* ignored */
@@ -9350,7 +9350,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_16:
+ case CP0_REGISTER_16:
switch (sel) {
case 0:
gen_helper_mtc0_config0(cpu_env, arg);
@@ -9390,7 +9390,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_17:
+ case CP0_REGISTER_17:
switch (sel) {
case 0:
gen_helper_mtc0_lladdr(cpu_env, arg);
@@ -9410,7 +9410,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_18:
+ case CP0_REGISTER_18:
switch (sel) {
case 0:
case 1:
@@ -9428,7 +9428,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_19:
+ case CP0_REGISTER_19:
switch (sel) {
case 0:
case 1:
@@ -9446,7 +9446,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_20:
+ case CP0_REGISTER_20:
switch (sel) {
case 0:
check_insn(ctx, ISA_MIPS3);
@@ -9457,7 +9457,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_21:
+ case CP0_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
switch (sel) {
@@ -9469,11 +9469,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_22:
+ case CP0_REGISTER_22:
/* ignored */
rn = "Diagnostic"; /* implementation dependent */
break;
- case CPO_REGISTER_23:
+ case CP0_REGISTER_23:
switch (sel) {
case 0:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
@@ -9510,7 +9510,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_24:
+ case CP0_REGISTER_24:
switch (sel) {
case 0:
/* EJTAG support */
@@ -9521,7 +9521,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_25:
+ case CP0_REGISTER_25:
switch (sel) {
case 0:
gen_helper_mtc0_performance0(cpu_env, arg);
@@ -9559,7 +9559,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_26:
+ case CP0_REGISTER_26:
switch (sel) {
case 0:
gen_helper_mtc0_errctl(cpu_env, arg);
@@ -9570,7 +9570,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_27:
+ case CP0_REGISTER_27:
switch (sel) {
case 0:
case 1:
@@ -9583,7 +9583,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_28:
+ case CP0_REGISTER_28:
switch (sel) {
case 0:
case 2:
@@ -9603,7 +9603,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_29:
+ case CP0_REGISTER_29:
switch (sel) {
case 0:
case 2:
@@ -9624,7 +9624,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_30:
+ case CP0_REGISTER_30:
switch (sel) {
case 0:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
@@ -9634,7 +9634,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CPO_REGISTER_31:
+ case CP0_REGISTER_31:
switch (sel) {
case 0:
/* EJTAG support */
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PULL v2 10/12] target/mips: Add CP0 register MemoryMapID
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
` (8 preceding siblings ...)
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 09/12] target/mips: Amend preprocessor constants for CP0 registers Aleksandar Markovic
@ 2019-01-18 16:59 ` Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 11/12] target/mips: Rename 'rn' to 'register_name' Aleksandar Markovic
` (2 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-01-18 16:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add CP0 register MemoryMapID. Only data field is added.
The corresponding functionality will be added in future
patches.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 1 +
target/mips/machine.c | 5 +++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index a5381b7..21daf50 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -536,6 +536,7 @@ struct CPUMIPSState {
*/
target_ulong CP0_Context;
target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
+ int32_t CP0_MemoryMapID;
/*
* CP0 Register 5
*/
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 111d7c3..1341ab1 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
- .version_id = 16,
- .minimum_version_id = 16,
+ .version_id = 17,
+ .minimum_version_id = 17,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
/* Active TC */
@@ -253,6 +253,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
+ VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PULL v2 11/12] target/mips: Rename 'rn' to 'register_name'
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
` (9 preceding siblings ...)
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 10/12] target/mips: Add CP0 register MemoryMapID Aleksandar Markovic
@ 2019-01-18 16:59 ` Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers Aleksandar Markovic
2019-01-21 19:19 ` [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Peter Maydell
12 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-01-18 16:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Rename 'rn' to 'register_name' in CP0-related handlers.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 858 ++++++++++++++++++++++++------------------------
1 file changed, 432 insertions(+), 426 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2259d44..3ac0b1f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6568,7 +6568,7 @@ static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
- const char *rn = "invalid";
+ const char *register_name = "invalid";
switch (reg) {
case CP0_REGISTER_02:
@@ -6576,7 +6576,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
- rn = "EntryLo0";
+ register_name = "EntryLo0";
break;
default:
goto cp0_unimplemented;
@@ -6587,7 +6587,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
- rn = "EntryLo1";
+ register_name = "EntryLo1";
break;
default:
goto cp0_unimplemented;
@@ -6598,7 +6598,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 7:
CP0_CHECK(ctx->saar);
gen_helper_mfhc0_saar(arg, cpu_env);
- rn = "SAAR";
+ register_name = "SAAR";
break;
default:
goto cp0_unimplemented;
@@ -6609,12 +6609,12 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
gen_mfhc0_load64(arg, offsetof(CPUMIPSState, lladdr),
ctx->CP0_LLAddr_shift);
- rn = "LLAddr";
+ register_name = "LLAddr";
break;
case 1:
CP0_CHECK(ctx->mrp);
gen_helper_mfhc0_maar(arg, cpu_env);
- rn = "MAAR";
+ register_name = "MAAR";
break;
default:
goto cp0_unimplemented;
@@ -6627,7 +6627,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 4:
case 6:
gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_TagLo), 0);
- rn = "TagLo";
+ register_name = "TagLo";
break;
default:
goto cp0_unimplemented;
@@ -6636,17 +6636,18 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
- trace_mips_translate_c0("mfhc0", rn, reg, sel);
+ trace_mips_translate_c0("mfhc0", register_name, reg, sel);
return;
cp0_unimplemented:
- qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n",
+ register_name, reg, sel);
tcg_gen_movi_tl(arg, 0);
}
static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
- const char *rn = "invalid";
+ const char *register_name = "invalid";
uint64_t mask = ctx->PAMask >> 36;
switch (reg) {
@@ -6656,7 +6657,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
- rn = "EntryLo0";
+ register_name = "EntryLo0";
break;
default:
goto cp0_unimplemented;
@@ -6668,7 +6669,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
- rn = "EntryLo1";
+ register_name = "EntryLo1";
break;
default:
goto cp0_unimplemented;
@@ -6679,7 +6680,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 7:
CP0_CHECK(ctx->saar);
gen_helper_mthc0_saar(cpu_env, arg);
- rn = "SAAR";
+ register_name = "SAAR";
break;
default:
goto cp0_unimplemented;
@@ -6691,12 +6692,12 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
supported); the CP0_LLAddr_rw_bitmask does not seem to be
relevant for modern MIPS cores supporting MTHC0, therefore
treating MTHC0 to LLAddr as NOP. */
- rn = "LLAddr";
+ register_name = "LLAddr";
break;
case 1:
CP0_CHECK(ctx->mrp);
gen_helper_mthc0_maar(cpu_env, arg);
- rn = "MAAR";
+ register_name = "MAAR";
break;
default:
goto cp0_unimplemented;
@@ -6710,7 +6711,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 6:
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_store64(arg, offsetof(CPUMIPSState, CP0_TagLo));
- rn = "TagLo";
+ register_name = "TagLo";
break;
default:
goto cp0_unimplemented;
@@ -6719,10 +6720,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
- trace_mips_translate_c0("mthc0", rn, reg, sel);
+ trace_mips_translate_c0("mthc0", register_name, reg, sel);
cp0_unimplemented:
- qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n",
+ register_name, reg, sel);
}
static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
@@ -6736,7 +6738,7 @@ static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
- const char *rn = "invalid";
+ const char *register_name = "invalid";
if (sel != 0)
check_insn(ctx, ISA_MIPS32);
@@ -6746,27 +6748,27 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
- rn = "Index";
+ register_name = "Index";
break;
case 1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
- rn = "MVPControl";
+ register_name = "MVPControl";
break;
case 2:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
- rn = "MVPConf0";
+ register_name = "MVPConf0";
break;
case 3:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
- rn = "MVPConf1";
+ register_name = "MVPConf1";
break;
case 4:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
- rn = "VPControl";
+ register_name = "VPControl";
break;
default:
goto cp0_unimplemented;
@@ -6777,42 +6779,42 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
gen_helper_mfc0_random(arg, cpu_env);
- rn = "Random";
+ register_name = "Random";
break;
case 1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
- rn = "VPEControl";
+ register_name = "VPEControl";
break;
case 2:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
- rn = "VPEConf0";
+ register_name = "VPEConf0";
break;
case 3:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
- rn = "VPEConf1";
+ register_name = "VPEConf1";
break;
case 4:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
- rn = "YQMask";
+ register_name = "YQMask";
break;
case 5:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
- rn = "VPESchedule";
+ register_name = "VPESchedule";
break;
case 6:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
- rn = "VPEScheFBack";
+ register_name = "VPEScheFBack";
break;
case 7:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
- rn = "VPEOpt";
+ register_name = "VPEOpt";
break;
default:
goto cp0_unimplemented;
@@ -6835,42 +6837,42 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_move_low32(arg, tmp);
tcg_temp_free_i64(tmp);
}
- rn = "EntryLo0";
+ register_name = "EntryLo0";
break;
case 1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env);
- rn = "TCStatus";
+ register_name = "TCStatus";
break;
case 2:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env);
- rn = "TCBind";
+ register_name = "TCBind";
break;
case 3:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcrestart(arg, cpu_env);
- rn = "TCRestart";
+ register_name = "TCRestart";
break;
case 4:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tchalt(arg, cpu_env);
- rn = "TCHalt";
+ register_name = "TCHalt";
break;
case 5:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tccontext(arg, cpu_env);
- rn = "TCContext";
+ register_name = "TCContext";
break;
case 6:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschedule(arg, cpu_env);
- rn = "TCSchedule";
+ register_name = "TCSchedule";
break;
case 7:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschefback(arg, cpu_env);
- rn = "TCScheFBack";
+ register_name = "TCScheFBack";
break;
default:
goto cp0_unimplemented;
@@ -6893,12 +6895,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_move_low32(arg, tmp);
tcg_temp_free_i64(tmp);
}
- rn = "EntryLo1";
+ register_name = "EntryLo1";
break;
case 1:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
- rn = "GlobalNumber";
+ register_name = "GlobalNumber";
break;
default:
goto cp0_unimplemented;
@@ -6909,18 +6911,18 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
tcg_gen_ext32s_tl(arg, arg);
- rn = "Context";
+ register_name = "Context";
break;
case 1:
// gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
- rn = "ContextConfig";
+ register_name = "ContextConfig";
goto cp0_unimplemented;
case 2:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
tcg_gen_ext32s_tl(arg, arg);
- rn = "UserLocal";
+ register_name = "UserLocal";
break;
default:
goto cp0_unimplemented;
@@ -6930,45 +6932,45 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
- rn = "PageMask";
+ register_name = "PageMask";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
- rn = "PageGrain";
+ register_name = "PageGrain";
break;
case 2:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
tcg_gen_ext32s_tl(arg, arg);
- rn = "SegCtl0";
+ register_name = "SegCtl0";
break;
case 3:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
tcg_gen_ext32s_tl(arg, arg);
- rn = "SegCtl1";
+ register_name = "SegCtl1";
break;
case 4:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
tcg_gen_ext32s_tl(arg, arg);
- rn = "SegCtl2";
+ register_name = "SegCtl2";
break;
case 5:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
- rn = "PWBase";
+ register_name = "PWBase";
break;
case 6:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
- rn = "PWField";
+ register_name = "PWField";
break;
case 7:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));
- rn = "PWSize";
+ register_name = "PWSize";
break;
default:
goto cp0_unimplemented;
@@ -6978,37 +6980,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
- rn = "Wired";
+ register_name = "Wired";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
- rn = "SRSConf0";
+ register_name = "SRSConf0";
break;
case 2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
- rn = "SRSConf1";
+ register_name = "SRSConf1";
break;
case 3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
- rn = "SRSConf2";
+ register_name = "SRSConf2";
break;
case 4:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
- rn = "SRSConf3";
+ register_name = "SRSConf3";
break;
case 5:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
- rn = "SRSConf4";
+ register_name = "SRSConf4";
break;
case 6:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
- rn = "PWCtl";
+ register_name = "PWCtl";
break;
default:
goto cp0_unimplemented;
@@ -7019,7 +7021,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
- rn = "HWREna";
+ register_name = "HWREna";
break;
default:
goto cp0_unimplemented;
@@ -7030,23 +7032,23 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
tcg_gen_ext32s_tl(arg, arg);
- rn = "BadVAddr";
+ register_name = "BadVAddr";
break;
case 1:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
- rn = "BadInstr";
+ register_name = "BadInstr";
break;
case 2:
CP0_CHECK(ctx->bp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
- rn = "BadInstrP";
+ register_name = "BadInstrP";
break;
case 3:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
tcg_gen_andi_tl(arg, arg, ~0xffff);
- rn = "BadInstrX";
+ register_name = "BadInstrX";
break;
default:
goto cp0_unimplemented;
@@ -7068,17 +7070,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ensure we break completely out of translated code. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
- rn = "Count";
+ register_name = "Count";
break;
case 6:
CP0_CHECK(ctx->saar);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
- rn = "SAARI";
+ register_name = "SAARI";
break;
case 7:
CP0_CHECK(ctx->saar);
gen_helper_mfc0_saar(arg, cpu_env);
- rn = "SAAR";
+ register_name = "SAAR";
break;
default:
goto cp0_unimplemented;
@@ -7089,7 +7091,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
tcg_gen_ext32s_tl(arg, arg);
- rn = "EntryHi";
+ register_name = "EntryHi";
break;
default:
goto cp0_unimplemented;
@@ -7099,7 +7101,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
- rn = "Compare";
+ register_name = "Compare";
break;
/* 6,7 are implementation dependent */
default:
@@ -7110,22 +7112,22 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
- rn = "Status";
+ register_name = "Status";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
- rn = "IntCtl";
+ register_name = "IntCtl";
break;
case 2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
- rn = "SRSCtl";
+ register_name = "SRSCtl";
break;
case 3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
- rn = "SRSMap";
+ register_name = "SRSMap";
break;
default:
goto cp0_unimplemented;
@@ -7135,7 +7137,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
- rn = "Cause";
+ register_name = "Cause";
break;
default:
goto cp0_unimplemented;
@@ -7146,7 +7148,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
tcg_gen_ext32s_tl(arg, arg);
- rn = "EPC";
+ register_name = "EPC";
break;
default:
goto cp0_unimplemented;
@@ -7156,20 +7158,20 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
- rn = "PRid";
+ register_name = "PRid";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg);
- rn = "EBase";
+ register_name = "EBase";
break;
case 3:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
tcg_gen_ext32s_tl(arg, arg);
- rn = "CMGCRBase";
+ register_name = "CMGCRBase";
break;
default:
goto cp0_unimplemented;
@@ -7179,36 +7181,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
- rn = "Config";
+ register_name = "Config";
break;
case 1:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
- rn = "Config1";
+ register_name = "Config1";
break;
case 2:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
- rn = "Config2";
+ register_name = "Config2";
break;
case 3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
- rn = "Config3";
+ register_name = "Config3";
break;
case 4:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
- rn = "Config4";
+ register_name = "Config4";
break;
case 5:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
- rn = "Config5";
+ register_name = "Config5";
break;
/* 6,7 are implementation dependent */
case 6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
- rn = "Config6";
+ register_name = "Config6";
break;
case 7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
- rn = "Config7";
+ register_name = "Config7";
break;
default:
goto cp0_unimplemented;
@@ -7218,17 +7220,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mfc0_lladdr(arg, cpu_env);
- rn = "LLAddr";
+ register_name = "LLAddr";
break;
case 1:
CP0_CHECK(ctx->mrp);
gen_helper_mfc0_maar(arg, cpu_env);
- rn = "MAAR";
+ register_name = "MAAR";
break;
case 2:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
- rn = "MAARI";
+ register_name = "MAARI";
break;
default:
goto cp0_unimplemented;
@@ -7246,7 +7248,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchlo, arg, sel);
- rn = "WatchLo";
+ register_name = "WatchLo";
break;
default:
goto cp0_unimplemented;
@@ -7264,7 +7266,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
- rn = "WatchHi";
+ register_name = "WatchHi";
break;
default:
goto cp0_unimplemented;
@@ -7277,7 +7279,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
check_insn(ctx, ISA_MIPS3);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
tcg_gen_ext32s_tl(arg, arg);
- rn = "XContext";
+ register_name = "XContext";
break;
#endif
default:
@@ -7290,7 +7292,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
- rn = "Framemask";
+ register_name = "Framemask";
break;
default:
goto cp0_unimplemented;
@@ -7298,29 +7300,29 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_22:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
- rn = "'Diagnostic"; /* implementation dependent */
+ register_name = "'Diagnostic"; /* implementation dependent */
break;
case CP0_REGISTER_23:
switch (sel) {
case 0:
gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
- rn = "Debug";
+ register_name = "Debug";
break;
case 1:
// gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
- rn = "TraceControl";
+ register_name = "TraceControl";
goto cp0_unimplemented;
case 2:
// gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
- rn = "TraceControl2";
+ register_name = "TraceControl2";
goto cp0_unimplemented;
case 3:
// gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
- rn = "UserTraceData";
+ register_name = "UserTraceData";
goto cp0_unimplemented;
case 4:
// gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
- rn = "TraceBPC";
+ register_name = "TraceBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -7332,7 +7334,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* EJTAG support */
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
tcg_gen_ext32s_tl(arg, arg);
- rn = "DEPC";
+ register_name = "DEPC";
break;
default:
goto cp0_unimplemented;
@@ -7342,35 +7344,35 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
- rn = "Performance0";
+ register_name = "Performance0";
break;
case 1:
// gen_helper_mfc0_performance1(arg);
- rn = "Performance1";
+ register_name = "Performance1";
goto cp0_unimplemented;
case 2:
// gen_helper_mfc0_performance2(arg);
- rn = "Performance2";
+ register_name = "Performance2";
goto cp0_unimplemented;
case 3:
// gen_helper_mfc0_performance3(arg);
- rn = "Performance3";
+ register_name = "Performance3";
goto cp0_unimplemented;
case 4:
// gen_helper_mfc0_performance4(arg);
- rn = "Performance4";
+ register_name = "Performance4";
goto cp0_unimplemented;
case 5:
// gen_helper_mfc0_performance5(arg);
- rn = "Performance5";
+ register_name = "Performance5";
goto cp0_unimplemented;
case 6:
// gen_helper_mfc0_performance6(arg);
- rn = "Performance6";
+ register_name = "Performance6";
goto cp0_unimplemented;
case 7:
// gen_helper_mfc0_performance7(arg);
- rn = "Performance7";
+ register_name = "Performance7";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -7380,7 +7382,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
- rn = "ErrCtl";
+ register_name = "ErrCtl";
break;
default:
goto cp0_unimplemented;
@@ -7393,7 +7395,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 2:
case 3:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
- rn = "CacheErr";
+ register_name = "CacheErr";
break;
default:
goto cp0_unimplemented;
@@ -7411,14 +7413,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_move_low32(arg, tmp);
tcg_temp_free_i64(tmp);
}
- rn = "TagLo";
+ register_name = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
- rn = "DataLo";
+ register_name = "DataLo";
break;
default:
goto cp0_unimplemented;
@@ -7431,14 +7433,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 4:
case 6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
- rn = "TagHi";
+ register_name = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
- rn = "DataHi";
+ register_name = "DataHi";
break;
default:
goto cp0_unimplemented;
@@ -7449,7 +7451,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
tcg_gen_ext32s_tl(arg, arg);
- rn = "ErrorEPC";
+ register_name = "ErrorEPC";
break;
default:
goto cp0_unimplemented;
@@ -7460,7 +7462,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
/* EJTAG support */
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
- rn = "DESAVE";
+ register_name = "DESAVE";
break;
case 2:
case 3:
@@ -7472,7 +7474,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
tcg_gen_ext32s_tl(arg, arg);
- rn = "KScratch";
+ register_name = "KScratch";
break;
default:
goto cp0_unimplemented;
@@ -7481,17 +7483,18 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
- trace_mips_translate_c0("mfc0", rn, reg, sel);
+ trace_mips_translate_c0("mfc0", register_name, reg, sel);
return;
cp0_unimplemented:
- qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n",
+ register_name, reg, sel);
gen_mfc0_unimplemented(ctx, arg);
}
static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
- const char *rn = "invalid";
+ const char *register_name = "invalid";
if (sel != 0)
check_insn(ctx, ISA_MIPS32);
@@ -7505,27 +7508,27 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_index(cpu_env, arg);
- rn = "Index";
+ register_name = "Index";
break;
case 1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
- rn = "MVPControl";
+ register_name = "MVPControl";
break;
case 2:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
- rn = "MVPConf0";
+ register_name = "MVPConf0";
break;
case 3:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
- rn = "MVPConf1";
+ register_name = "MVPConf1";
break;
case 4:
CP0_CHECK(ctx->vp);
/* ignored */
- rn = "VPControl";
+ register_name = "VPControl";
break;
default:
goto cp0_unimplemented;
@@ -7535,44 +7538,44 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
/* ignored */
- rn = "Random";
+ register_name = "Random";
break;
case 1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpecontrol(cpu_env, arg);
- rn = "VPEControl";
+ register_name = "VPEControl";
break;
case 2:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf0(cpu_env, arg);
- rn = "VPEConf0";
+ register_name = "VPEConf0";
break;
case 3:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf1(cpu_env, arg);
- rn = "VPEConf1";
+ register_name = "VPEConf1";
break;
case 4:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_yqmask(cpu_env, arg);
- rn = "YQMask";
+ register_name = "YQMask";
break;
case 5:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
- rn = "VPESchedule";
+ register_name = "VPESchedule";
break;
case 6:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
- rn = "VPEScheFBack";
+ register_name = "VPEScheFBack";
break;
case 7:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeopt(cpu_env, arg);
- rn = "VPEOpt";
+ register_name = "VPEOpt";
break;
default:
goto cp0_unimplemented;
@@ -7582,42 +7585,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_entrylo0(cpu_env, arg);
- rn = "EntryLo0";
+ register_name = "EntryLo0";
break;
case 1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg);
- rn = "TCStatus";
+ register_name = "TCStatus";
break;
case 2:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg);
- rn = "TCBind";
+ register_name = "TCBind";
break;
case 3:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg);
- rn = "TCRestart";
+ register_name = "TCRestart";
break;
case 4:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg);
- rn = "TCHalt";
+ register_name = "TCHalt";
break;
case 5:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg);
- rn = "TCContext";
+ register_name = "TCContext";
break;
case 6:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg);
- rn = "TCSchedule";
+ register_name = "TCSchedule";
break;
case 7:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg);
- rn = "TCScheFBack";
+ register_name = "TCScheFBack";
break;
default:
goto cp0_unimplemented;
@@ -7627,12 +7630,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_entrylo1(cpu_env, arg);
- rn = "EntryLo1";
+ register_name = "EntryLo1";
break;
case 1:
CP0_CHECK(ctx->vp);
/* ignored */
- rn = "GlobalNumber";
+ register_name = "GlobalNumber";
break;
default:
goto cp0_unimplemented;
@@ -7642,17 +7645,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_context(cpu_env, arg);
- rn = "Context";
+ register_name = "Context";
break;
case 1:
// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
- rn = "ContextConfig";
+ register_name = "ContextConfig";
goto cp0_unimplemented;
case 2:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
- rn = "UserLocal";
+ register_name = "UserLocal";
break;
default:
goto cp0_unimplemented;
@@ -7662,43 +7665,43 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_pagemask(cpu_env, arg);
- rn = "PageMask";
+ register_name = "PageMask";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
- rn = "PageGrain";
+ register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP;
break;
case 2:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(cpu_env, arg);
- rn = "SegCtl0";
+ register_name = "SegCtl0";
break;
case 3:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(cpu_env, arg);
- rn = "SegCtl1";
+ register_name = "SegCtl1";
break;
case 4:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(cpu_env, arg);
- rn = "SegCtl2";
+ register_name = "SegCtl2";
break;
case 5:
check_pw(ctx);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
- rn = "PWBase";
+ register_name = "PWBase";
break;
case 6:
check_pw(ctx);
gen_helper_mtc0_pwfield(cpu_env, arg);
- rn = "PWField";
+ register_name = "PWField";
break;
case 7:
check_pw(ctx);
gen_helper_mtc0_pwsize(cpu_env, arg);
- rn = "PWSize";
+ register_name = "PWSize";
break;
default:
goto cp0_unimplemented;
@@ -7708,37 +7711,37 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_wired(cpu_env, arg);
- rn = "Wired";
+ register_name = "Wired";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
- rn = "SRSConf0";
+ register_name = "SRSConf0";
break;
case 2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
- rn = "SRSConf1";
+ register_name = "SRSConf1";
break;
case 3:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
- rn = "SRSConf2";
+ register_name = "SRSConf2";
break;
case 4:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
- rn = "SRSConf3";
+ register_name = "SRSConf3";
break;
case 5:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
- rn = "SRSConf4";
+ register_name = "SRSConf4";
break;
case 6:
check_pw(ctx);
gen_helper_mtc0_pwctl(cpu_env, arg);
- rn = "PWCtl";
+ register_name = "PWCtl";
break;
default:
goto cp0_unimplemented;
@@ -7750,7 +7753,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
- rn = "HWREna";
+ register_name = "HWREna";
break;
default:
goto cp0_unimplemented;
@@ -7760,19 +7763,19 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
/* ignored */
- rn = "BadVAddr";
+ register_name = "BadVAddr";
break;
case 1:
/* ignored */
- rn = "BadInstr";
+ register_name = "BadInstr";
break;
case 2:
/* ignored */
- rn = "BadInstrP";
+ register_name = "BadInstrP";
break;
case 3:
/* ignored */
- rn = "BadInstrX";
+ register_name = "BadInstrX";
break;
default:
goto cp0_unimplemented;
@@ -7782,17 +7785,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_count(cpu_env, arg);
- rn = "Count";
+ register_name = "Count";
break;
case 6:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saari(cpu_env, arg);
- rn = "SAARI";
+ register_name = "SAARI";
break;
case 7:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saar(cpu_env, arg);
- rn = "SAAR";
+ register_name = "SAAR";
break;
default:
goto cp0_unimplemented;
@@ -7802,7 +7805,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_entryhi(cpu_env, arg);
- rn = "EntryHi";
+ register_name = "EntryHi";
break;
default:
goto cp0_unimplemented;
@@ -7812,7 +7815,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_compare(cpu_env, arg);
- rn = "Compare";
+ register_name = "Compare";
break;
/* 6,7 are implementation dependent */
default:
@@ -7827,28 +7830,28 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
- rn = "Status";
+ register_name = "Status";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- rn = "IntCtl";
+ register_name = "IntCtl";
break;
case 2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- rn = "SRSCtl";
+ register_name = "SRSCtl";
break;
case 3:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- rn = "SRSMap";
+ register_name = "SRSMap";
break;
default:
goto cp0_unimplemented;
@@ -7864,7 +7867,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
* translated code to check for pending interrupts. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
- rn = "Cause";
+ register_name = "Cause";
break;
default:
goto cp0_unimplemented;
@@ -7874,7 +7877,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
- rn = "EPC";
+ register_name = "EPC";
break;
default:
goto cp0_unimplemented;
@@ -7884,12 +7887,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
/* ignored */
- rn = "PRid";
+ register_name = "PRid";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
- rn = "EBase";
+ register_name = "EBase";
break;
default:
goto cp0_unimplemented;
@@ -7899,48 +7902,48 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_config0(cpu_env, arg);
- rn = "Config";
+ register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case 1:
/* ignored, read only */
- rn = "Config1";
+ register_name = "Config1";
break;
case 2:
gen_helper_mtc0_config2(cpu_env, arg);
- rn = "Config2";
+ register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case 3:
gen_helper_mtc0_config3(cpu_env, arg);
- rn = "Config3";
+ register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case 4:
gen_helper_mtc0_config4(cpu_env, arg);
- rn = "Config4";
+ register_name = "Config4";
ctx->base.is_jmp = DISAS_STOP;
break;
case 5:
gen_helper_mtc0_config5(cpu_env, arg);
- rn = "Config5";
+ register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
/* 6,7 are implementation dependent */
case 6:
/* ignored */
- rn = "Config6";
+ register_name = "Config6";
break;
case 7:
/* ignored */
- rn = "Config7";
+ register_name = "Config7";
break;
default:
- rn = "Invalid config selector";
+ register_name = "Invalid config selector";
goto cp0_unimplemented;
}
break;
@@ -7948,17 +7951,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_lladdr(cpu_env, arg);
- rn = "LLAddr";
+ register_name = "LLAddr";
break;
case 1:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
- rn = "MAAR";
+ register_name = "MAAR";
break;
case 2:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
- rn = "MAARI";
+ register_name = "MAARI";
break;
default:
goto cp0_unimplemented;
@@ -7976,7 +7979,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
- rn = "WatchLo";
+ register_name = "WatchLo";
break;
default:
goto cp0_unimplemented;
@@ -7994,7 +7997,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
- rn = "WatchHi";
+ register_name = "WatchHi";
break;
default:
goto cp0_unimplemented;
@@ -8006,7 +8009,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
gen_helper_mtc0_xcontext(cpu_env, arg);
- rn = "XContext";
+ register_name = "XContext";
break;
#endif
default:
@@ -8019,7 +8022,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_framemask(cpu_env, arg);
- rn = "Framemask";
+ register_name = "Framemask";
break;
default:
goto cp0_unimplemented;
@@ -8027,7 +8030,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_22:
/* ignored */
- rn = "Diagnostic"; /* implementation dependent */
+ register_name = "Diagnostic"; /* implementation dependent */
break;
case CP0_REGISTER_23:
switch (sel) {
@@ -8036,17 +8039,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
- rn = "Debug";
+ register_name = "Debug";
break;
case 1:
// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
- rn = "TraceControl";
+ register_name = "TraceControl";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
case 2:
// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
- rn = "TraceControl2";
+ register_name = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
@@ -8054,7 +8057,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
- rn = "UserTraceData";
+ register_name = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
@@ -8062,7 +8065,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- rn = "TraceBPC";
+ register_name = "TraceBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -8073,7 +8076,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
/* EJTAG support */
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
- rn = "DEPC";
+ register_name = "DEPC";
break;
default:
goto cp0_unimplemented;
@@ -8083,35 +8086,35 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_performance0(cpu_env, arg);
- rn = "Performance0";
+ register_name = "Performance0";
break;
case 1:
// gen_helper_mtc0_performance1(arg);
- rn = "Performance1";
+ register_name = "Performance1";
goto cp0_unimplemented;
case 2:
// gen_helper_mtc0_performance2(arg);
- rn = "Performance2";
+ register_name = "Performance2";
goto cp0_unimplemented;
case 3:
// gen_helper_mtc0_performance3(arg);
- rn = "Performance3";
+ register_name = "Performance3";
goto cp0_unimplemented;
case 4:
// gen_helper_mtc0_performance4(arg);
- rn = "Performance4";
+ register_name = "Performance4";
goto cp0_unimplemented;
case 5:
// gen_helper_mtc0_performance5(arg);
- rn = "Performance5";
+ register_name = "Performance5";
goto cp0_unimplemented;
case 6:
// gen_helper_mtc0_performance6(arg);
- rn = "Performance6";
+ register_name = "Performance6";
goto cp0_unimplemented;
case 7:
// gen_helper_mtc0_performance7(arg);
- rn = "Performance7";
+ register_name = "Performance7";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -8122,7 +8125,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
gen_helper_mtc0_errctl(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
- rn = "ErrCtl";
+ register_name = "ErrCtl";
break;
default:
goto cp0_unimplemented;
@@ -8135,7 +8138,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 2:
case 3:
/* ignored */
- rn = "CacheErr";
+ register_name = "CacheErr";
break;
default:
goto cp0_unimplemented;
@@ -8148,14 +8151,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 4:
case 6:
gen_helper_mtc0_taglo(cpu_env, arg);
- rn = "TagLo";
+ register_name = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
gen_helper_mtc0_datalo(cpu_env, arg);
- rn = "DataLo";
+ register_name = "DataLo";
break;
default:
goto cp0_unimplemented;
@@ -8168,17 +8171,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 4:
case 6:
gen_helper_mtc0_taghi(cpu_env, arg);
- rn = "TagHi";
+ register_name = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
gen_helper_mtc0_datahi(cpu_env, arg);
- rn = "DataHi";
+ register_name = "DataHi";
break;
default:
- rn = "invalid sel";
+ register_name = "invalid sel";
goto cp0_unimplemented;
}
break;
@@ -8186,7 +8189,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
- rn = "ErrorEPC";
+ register_name = "ErrorEPC";
break;
default:
goto cp0_unimplemented;
@@ -8197,7 +8200,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
/* EJTAG support */
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
- rn = "DESAVE";
+ register_name = "DESAVE";
break;
case 2:
case 3:
@@ -8208,7 +8211,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
- rn = "KScratch";
+ register_name = "KScratch";
break;
default:
goto cp0_unimplemented;
@@ -8217,7 +8220,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
- trace_mips_translate_c0("mtc0", rn, reg, sel);
+ trace_mips_translate_c0("mtc0", register_name, reg, sel);
/* For simplicity assume that all writes can cause interrupts. */
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
@@ -8230,13 +8233,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
return;
cp0_unimplemented:
- qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n",
+ register_name, reg, sel);
}
#if defined(TARGET_MIPS64)
static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
- const char *rn = "invalid";
+ const char *register_name = "invalid";
if (sel != 0)
check_insn(ctx, ISA_MIPS64);
@@ -8246,27 +8250,27 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
- rn = "Index";
+ register_name = "Index";
break;
case 1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
- rn = "MVPControl";
+ register_name = "MVPControl";
break;
case 2:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
- rn = "MVPConf0";
+ register_name = "MVPConf0";
break;
case 3:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
- rn = "MVPConf1";
+ register_name = "MVPConf1";
break;
case 4:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
- rn = "VPControl";
+ register_name = "VPControl";
break;
default:
goto cp0_unimplemented;
@@ -8277,42 +8281,42 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
gen_helper_mfc0_random(arg, cpu_env);
- rn = "Random";
+ register_name = "Random";
break;
case 1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
- rn = "VPEControl";
+ register_name = "VPEControl";
break;
case 2:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
- rn = "VPEConf0";
+ register_name = "VPEConf0";
break;
case 3:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
- rn = "VPEConf1";
+ register_name = "VPEConf1";
break;
case 4:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
- rn = "YQMask";
+ register_name = "YQMask";
break;
case 5:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
- rn = "VPESchedule";
+ register_name = "VPESchedule";
break;
case 6:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
- rn = "VPEScheFBack";
+ register_name = "VPEScheFBack";
break;
case 7:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
- rn = "VPEOpt";
+ register_name = "VPEOpt";
break;
default:
goto cp0_unimplemented;
@@ -8322,42 +8326,42 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
- rn = "EntryLo0";
+ register_name = "EntryLo0";
break;
case 1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env);
- rn = "TCStatus";
+ register_name = "TCStatus";
break;
case 2:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env);
- rn = "TCBind";
+ register_name = "TCBind";
break;
case 3:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcrestart(arg, cpu_env);
- rn = "TCRestart";
+ register_name = "TCRestart";
break;
case 4:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tchalt(arg, cpu_env);
- rn = "TCHalt";
+ register_name = "TCHalt";
break;
case 5:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tccontext(arg, cpu_env);
- rn = "TCContext";
+ register_name = "TCContext";
break;
case 6:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschedule(arg, cpu_env);
- rn = "TCSchedule";
+ register_name = "TCSchedule";
break;
case 7:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschefback(arg, cpu_env);
- rn = "TCScheFBack";
+ register_name = "TCScheFBack";
break;
default:
goto cp0_unimplemented;
@@ -8367,12 +8371,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
- rn = "EntryLo1";
+ register_name = "EntryLo1";
break;
case 1:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
- rn = "GlobalNumber";
+ register_name = "GlobalNumber";
break;
default:
goto cp0_unimplemented;
@@ -8382,17 +8386,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
- rn = "Context";
+ register_name = "Context";
break;
case 1:
// gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
- rn = "ContextConfig";
+ register_name = "ContextConfig";
goto cp0_unimplemented;
case 2:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
- rn = "UserLocal";
+ register_name = "UserLocal";
break;
default:
goto cp0_unimplemented;
@@ -8402,42 +8406,42 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
- rn = "PageMask";
+ register_name = "PageMask";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
- rn = "PageGrain";
+ register_name = "PageGrain";
break;
case 2:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
- rn = "SegCtl0";
+ register_name = "SegCtl0";
break;
case 3:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
- rn = "SegCtl1";
+ register_name = "SegCtl1";
break;
case 4:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
- rn = "SegCtl2";
+ register_name = "SegCtl2";
break;
case 5:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
- rn = "PWBase";
+ register_name = "PWBase";
break;
case 6:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));
- rn = "PWField";
+ register_name = "PWField";
break;
case 7:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
- rn = "PWSize";
+ register_name = "PWSize";
break;
default:
goto cp0_unimplemented;
@@ -8447,37 +8451,37 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
- rn = "Wired";
+ register_name = "Wired";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
- rn = "SRSConf0";
+ register_name = "SRSConf0";
break;
case 2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
- rn = "SRSConf1";
+ register_name = "SRSConf1";
break;
case 3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
- rn = "SRSConf2";
+ register_name = "SRSConf2";
break;
case 4:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
- rn = "SRSConf3";
+ register_name = "SRSConf3";
break;
case 5:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
- rn = "SRSConf4";
+ register_name = "SRSConf4";
break;
case 6:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
- rn = "PWCtl";
+ register_name = "PWCtl";
break;
default:
goto cp0_unimplemented;
@@ -8488,7 +8492,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
- rn = "HWREna";
+ register_name = "HWREna";
break;
default:
goto cp0_unimplemented;
@@ -8498,23 +8502,23 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
- rn = "BadVAddr";
+ register_name = "BadVAddr";
break;
case 1:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
- rn = "BadInstr";
+ register_name = "BadInstr";
break;
case 2:
CP0_CHECK(ctx->bp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
- rn = "BadInstrP";
+ register_name = "BadInstrP";
break;
case 3:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
tcg_gen_andi_tl(arg, arg, ~0xffff);
- rn = "BadInstrX";
+ register_name = "BadInstrX";
break;
default:
goto cp0_unimplemented;
@@ -8536,17 +8540,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ensure we break completely out of translated code. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
- rn = "Count";
+ register_name = "Count";
break;
case 6:
CP0_CHECK(ctx->saar);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
- rn = "SAARI";
+ register_name = "SAARI";
break;
case 7:
CP0_CHECK(ctx->saar);
gen_helper_dmfc0_saar(arg, cpu_env);
- rn = "SAAR";
+ register_name = "SAAR";
break;
default:
goto cp0_unimplemented;
@@ -8556,7 +8560,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
- rn = "EntryHi";
+ register_name = "EntryHi";
break;
default:
goto cp0_unimplemented;
@@ -8566,7 +8570,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
- rn = "Compare";
+ register_name = "Compare";
break;
/* 6,7 are implementation dependent */
default:
@@ -8577,22 +8581,22 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
- rn = "Status";
+ register_name = "Status";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
- rn = "IntCtl";
+ register_name = "IntCtl";
break;
case 2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
- rn = "SRSCtl";
+ register_name = "SRSCtl";
break;
case 3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
- rn = "SRSMap";
+ register_name = "SRSMap";
break;
default:
goto cp0_unimplemented;
@@ -8602,7 +8606,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
- rn = "Cause";
+ register_name = "Cause";
break;
default:
goto cp0_unimplemented;
@@ -8612,7 +8616,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
- rn = "EPC";
+ register_name = "EPC";
break;
default:
goto cp0_unimplemented;
@@ -8622,18 +8626,18 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
- rn = "PRid";
+ register_name = "PRid";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
- rn = "EBase";
+ register_name = "EBase";
break;
case 3:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
- rn = "CMGCRBase";
+ register_name = "CMGCRBase";
break;
default:
goto cp0_unimplemented;
@@ -8643,36 +8647,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
- rn = "Config";
+ register_name = "Config";
break;
case 1:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
- rn = "Config1";
+ register_name = "Config1";
break;
case 2:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
- rn = "Config2";
+ register_name = "Config2";
break;
case 3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
- rn = "Config3";
+ register_name = "Config3";
break;
case 4:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
- rn = "Config4";
+ register_name = "Config4";
break;
case 5:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
- rn = "Config5";
+ register_name = "Config5";
break;
/* 6,7 are implementation dependent */
case 6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
- rn = "Config6";
+ register_name = "Config6";
break;
case 7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
- rn = "Config7";
+ register_name = "Config7";
break;
default:
goto cp0_unimplemented;
@@ -8682,17 +8686,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_dmfc0_lladdr(arg, cpu_env);
- rn = "LLAddr";
+ register_name = "LLAddr";
break;
case 1:
CP0_CHECK(ctx->mrp);
gen_helper_dmfc0_maar(arg, cpu_env);
- rn = "MAAR";
+ register_name = "MAAR";
break;
case 2:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
- rn = "MAARI";
+ register_name = "MAARI";
break;
default:
goto cp0_unimplemented;
@@ -8710,7 +8714,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
- rn = "WatchLo";
+ register_name = "WatchLo";
break;
default:
goto cp0_unimplemented;
@@ -8728,7 +8732,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
- rn = "WatchHi";
+ register_name = "WatchHi";
break;
default:
goto cp0_unimplemented;
@@ -8739,7 +8743,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
check_insn(ctx, ISA_MIPS3);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
- rn = "XContext";
+ register_name = "XContext";
break;
default:
goto cp0_unimplemented;
@@ -8751,7 +8755,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
- rn = "Framemask";
+ register_name = "Framemask";
break;
default:
goto cp0_unimplemented;
@@ -8759,29 +8763,29 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_22:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
- rn = "'Diagnostic"; /* implementation dependent */
+ register_name = "'Diagnostic"; /* implementation dependent */
break;
case CP0_REGISTER_23:
switch (sel) {
case 0:
gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
- rn = "Debug";
+ register_name = "Debug";
break;
case 1:
// gen_helper_dmfc0_tracecontrol(arg, cpu_env); /* PDtrace support */
- rn = "TraceControl";
+ register_name = "TraceControl";
goto cp0_unimplemented;
case 2:
// gen_helper_dmfc0_tracecontrol2(arg, cpu_env); /* PDtrace support */
- rn = "TraceControl2";
+ register_name = "TraceControl2";
goto cp0_unimplemented;
case 3:
// gen_helper_dmfc0_usertracedata(arg, cpu_env); /* PDtrace support */
- rn = "UserTraceData";
+ register_name = "UserTraceData";
goto cp0_unimplemented;
case 4:
// gen_helper_dmfc0_tracebpc(arg, cpu_env); /* PDtrace support */
- rn = "TraceBPC";
+ register_name = "TraceBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -8792,7 +8796,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
/* EJTAG support */
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
- rn = "DEPC";
+ register_name = "DEPC";
break;
default:
goto cp0_unimplemented;
@@ -8802,35 +8806,35 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
- rn = "Performance0";
+ register_name = "Performance0";
break;
case 1:
// gen_helper_dmfc0_performance1(arg);
- rn = "Performance1";
+ register_name = "Performance1";
goto cp0_unimplemented;
case 2:
// gen_helper_dmfc0_performance2(arg);
- rn = "Performance2";
+ register_name = "Performance2";
goto cp0_unimplemented;
case 3:
// gen_helper_dmfc0_performance3(arg);
- rn = "Performance3";
+ register_name = "Performance3";
goto cp0_unimplemented;
case 4:
// gen_helper_dmfc0_performance4(arg);
- rn = "Performance4";
+ register_name = "Performance4";
goto cp0_unimplemented;
case 5:
// gen_helper_dmfc0_performance5(arg);
- rn = "Performance5";
+ register_name = "Performance5";
goto cp0_unimplemented;
case 6:
// gen_helper_dmfc0_performance6(arg);
- rn = "Performance6";
+ register_name = "Performance6";
goto cp0_unimplemented;
case 7:
// gen_helper_dmfc0_performance7(arg);
- rn = "Performance7";
+ register_name = "Performance7";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -8840,7 +8844,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
- rn = "ErrCtl";
+ register_name = "ErrCtl";
break;
default:
goto cp0_unimplemented;
@@ -8854,7 +8858,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 2:
case 3:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
- rn = "CacheErr";
+ register_name = "CacheErr";
break;
default:
goto cp0_unimplemented;
@@ -8867,14 +8871,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 4:
case 6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
- rn = "TagLo";
+ register_name = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
- rn = "DataLo";
+ register_name = "DataLo";
break;
default:
goto cp0_unimplemented;
@@ -8887,14 +8891,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 4:
case 6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
- rn = "TagHi";
+ register_name = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
- rn = "DataHi";
+ register_name = "DataHi";
break;
default:
goto cp0_unimplemented;
@@ -8904,7 +8908,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
- rn = "ErrorEPC";
+ register_name = "ErrorEPC";
break;
default:
goto cp0_unimplemented;
@@ -8915,7 +8919,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
/* EJTAG support */
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
- rn = "DESAVE";
+ register_name = "DESAVE";
break;
case 2:
case 3:
@@ -8926,7 +8930,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
- rn = "KScratch";
+ register_name = "KScratch";
break;
default:
goto cp0_unimplemented;
@@ -8935,17 +8939,18 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
- trace_mips_translate_c0("dmfc0", rn, reg, sel);
+ trace_mips_translate_c0("dmfc0", register_name, reg, sel);
return;
cp0_unimplemented:
- qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n",
+ register_name, reg, sel);
gen_mfc0_unimplemented(ctx, arg);
}
static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
- const char *rn = "invalid";
+ const char *register_name = "invalid";
if (sel != 0)
check_insn(ctx, ISA_MIPS64);
@@ -8959,27 +8964,27 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_index(cpu_env, arg);
- rn = "Index";
+ register_name = "Index";
break;
case 1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
- rn = "MVPControl";
+ register_name = "MVPControl";
break;
case 2:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
- rn = "MVPConf0";
+ register_name = "MVPConf0";
break;
case 3:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
- rn = "MVPConf1";
+ register_name = "MVPConf1";
break;
case 4:
CP0_CHECK(ctx->vp);
/* ignored */
- rn = "VPControl";
+ register_name = "VPControl";
break;
default:
goto cp0_unimplemented;
@@ -8989,42 +8994,42 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
/* ignored */
- rn = "Random";
+ register_name = "Random";
break;
case 1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpecontrol(cpu_env, arg);
- rn = "VPEControl";
+ register_name = "VPEControl";
break;
case 2:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf0(cpu_env, arg);
- rn = "VPEConf0";
+ register_name = "VPEConf0";
break;
case 3:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf1(cpu_env, arg);
- rn = "VPEConf1";
+ register_name = "VPEConf1";
break;
case 4:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_yqmask(cpu_env, arg);
- rn = "YQMask";
+ register_name = "YQMask";
break;
case 5:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
- rn = "VPESchedule";
+ register_name = "VPESchedule";
break;
case 6:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
- rn = "VPEScheFBack";
+ register_name = "VPEScheFBack";
break;
case 7:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeopt(cpu_env, arg);
- rn = "VPEOpt";
+ register_name = "VPEOpt";
break;
default:
goto cp0_unimplemented;
@@ -9034,42 +9039,42 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_dmtc0_entrylo0(cpu_env, arg);
- rn = "EntryLo0";
+ register_name = "EntryLo0";
break;
case 1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg);
- rn = "TCStatus";
+ register_name = "TCStatus";
break;
case 2:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg);
- rn = "TCBind";
+ register_name = "TCBind";
break;
case 3:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg);
- rn = "TCRestart";
+ register_name = "TCRestart";
break;
case 4:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg);
- rn = "TCHalt";
+ register_name = "TCHalt";
break;
case 5:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg);
- rn = "TCContext";
+ register_name = "TCContext";
break;
case 6:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg);
- rn = "TCSchedule";
+ register_name = "TCSchedule";
break;
case 7:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg);
- rn = "TCScheFBack";
+ register_name = "TCScheFBack";
break;
default:
goto cp0_unimplemented;
@@ -9079,12 +9084,12 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_dmtc0_entrylo1(cpu_env, arg);
- rn = "EntryLo1";
+ register_name = "EntryLo1";
break;
case 1:
CP0_CHECK(ctx->vp);
/* ignored */
- rn = "GlobalNumber";
+ register_name = "GlobalNumber";
break;
default:
goto cp0_unimplemented;
@@ -9094,17 +9099,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_context(cpu_env, arg);
- rn = "Context";
+ register_name = "Context";
break;
case 1:
// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
- rn = "ContextConfig";
+ register_name = "ContextConfig";
goto cp0_unimplemented;
case 2:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
- rn = "UserLocal";
+ register_name = "UserLocal";
break;
default:
goto cp0_unimplemented;
@@ -9114,42 +9119,42 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_pagemask(cpu_env, arg);
- rn = "PageMask";
+ register_name = "PageMask";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
- rn = "PageGrain";
+ register_name = "PageGrain";
break;
case 2:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(cpu_env, arg);
- rn = "SegCtl0";
+ register_name = "SegCtl0";
break;
case 3:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(cpu_env, arg);
- rn = "SegCtl1";
+ register_name = "SegCtl1";
break;
case 4:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(cpu_env, arg);
- rn = "SegCtl2";
+ register_name = "SegCtl2";
break;
case 5:
check_pw(ctx);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
- rn = "PWBase";
+ register_name = "PWBase";
break;
case 6:
check_pw(ctx);
gen_helper_mtc0_pwfield(cpu_env, arg);
- rn = "PWField";
+ register_name = "PWField";
break;
case 7:
check_pw(ctx);
gen_helper_mtc0_pwsize(cpu_env, arg);
- rn = "PWSize";
+ register_name = "PWSize";
break;
default:
goto cp0_unimplemented;
@@ -9159,37 +9164,37 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_wired(cpu_env, arg);
- rn = "Wired";
+ register_name = "Wired";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
- rn = "SRSConf0";
+ register_name = "SRSConf0";
break;
case 2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
- rn = "SRSConf1";
+ register_name = "SRSConf1";
break;
case 3:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
- rn = "SRSConf2";
+ register_name = "SRSConf2";
break;
case 4:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
- rn = "SRSConf3";
+ register_name = "SRSConf3";
break;
case 5:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
- rn = "SRSConf4";
+ register_name = "SRSConf4";
break;
case 6:
check_pw(ctx);
gen_helper_mtc0_pwctl(cpu_env, arg);
- rn = "PWCtl";
+ register_name = "PWCtl";
break;
default:
goto cp0_unimplemented;
@@ -9201,7 +9206,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
- rn = "HWREna";
+ register_name = "HWREna";
break;
default:
goto cp0_unimplemented;
@@ -9211,19 +9216,19 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
/* ignored */
- rn = "BadVAddr";
+ register_name = "BadVAddr";
break;
case 1:
/* ignored */
- rn = "BadInstr";
+ register_name = "BadInstr";
break;
case 2:
/* ignored */
- rn = "BadInstrP";
+ register_name = "BadInstrP";
break;
case 3:
/* ignored */
- rn = "BadInstrX";
+ register_name = "BadInstrX";
break;
default:
goto cp0_unimplemented;
@@ -9233,17 +9238,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_count(cpu_env, arg);
- rn = "Count";
+ register_name = "Count";
break;
case 6:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saari(cpu_env, arg);
- rn = "SAARI";
+ register_name = "SAARI";
break;
case 7:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saar(cpu_env, arg);
- rn = "SAAR";
+ register_name = "SAAR";
break;
default:
goto cp0_unimplemented;
@@ -9255,7 +9260,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_entryhi(cpu_env, arg);
- rn = "EntryHi";
+ register_name = "EntryHi";
break;
default:
goto cp0_unimplemented;
@@ -9265,7 +9270,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_compare(cpu_env, arg);
- rn = "Compare";
+ register_name = "Compare";
break;
/* 6,7 are implementation dependent */
default:
@@ -9282,28 +9287,28 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
- rn = "Status";
+ register_name = "Status";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- rn = "IntCtl";
+ register_name = "IntCtl";
break;
case 2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- rn = "SRSCtl";
+ register_name = "SRSCtl";
break;
case 3:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- rn = "SRSMap";
+ register_name = "SRSMap";
break;
default:
goto cp0_unimplemented;
@@ -9319,7 +9324,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
* translated code to check for pending interrupts. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
- rn = "Cause";
+ register_name = "Cause";
break;
default:
goto cp0_unimplemented;
@@ -9329,7 +9334,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
- rn = "EPC";
+ register_name = "EPC";
break;
default:
goto cp0_unimplemented;
@@ -9339,12 +9344,12 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
/* ignored */
- rn = "PRid";
+ register_name = "PRid";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
- rn = "EBase";
+ register_name = "EBase";
break;
default:
goto cp0_unimplemented;
@@ -9354,39 +9359,39 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_config0(cpu_env, arg);
- rn = "Config";
+ register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case 1:
/* ignored, read only */
- rn = "Config1";
+ register_name = "Config1";
break;
case 2:
gen_helper_mtc0_config2(cpu_env, arg);
- rn = "Config2";
+ register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case 3:
gen_helper_mtc0_config3(cpu_env, arg);
- rn = "Config3";
+ register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case 4:
/* currently ignored */
- rn = "Config4";
+ register_name = "Config4";
break;
case 5:
gen_helper_mtc0_config5(cpu_env, arg);
- rn = "Config5";
+ register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
/* 6,7 are implementation dependent */
default:
- rn = "Invalid config selector";
+ register_name = "Invalid config selector";
goto cp0_unimplemented;
}
break;
@@ -9394,17 +9399,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_lladdr(cpu_env, arg);
- rn = "LLAddr";
+ register_name = "LLAddr";
break;
case 1:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
- rn = "MAAR";
+ register_name = "MAAR";
break;
case 2:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
- rn = "MAARI";
+ register_name = "MAARI";
break;
default:
goto cp0_unimplemented;
@@ -9422,7 +9427,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
- rn = "WatchLo";
+ register_name = "WatchLo";
break;
default:
goto cp0_unimplemented;
@@ -9440,7 +9445,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
- rn = "WatchHi";
+ register_name = "WatchHi";
break;
default:
goto cp0_unimplemented;
@@ -9451,7 +9456,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
check_insn(ctx, ISA_MIPS3);
gen_helper_mtc0_xcontext(cpu_env, arg);
- rn = "XContext";
+ register_name = "XContext";
break;
default:
goto cp0_unimplemented;
@@ -9463,7 +9468,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_framemask(cpu_env, arg);
- rn = "Framemask";
+ register_name = "Framemask";
break;
default:
goto cp0_unimplemented;
@@ -9471,7 +9476,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_22:
/* ignored */
- rn = "Diagnostic"; /* implementation dependent */
+ register_name = "Diagnostic"; /* implementation dependent */
break;
case CP0_REGISTER_23:
switch (sel) {
@@ -9480,31 +9485,31 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
- rn = "Debug";
+ register_name = "Debug";
break;
case 1:
// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- rn = "TraceControl";
+ register_name = "TraceControl";
goto cp0_unimplemented;
case 2:
// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- rn = "TraceControl2";
+ register_name = "TraceControl2";
goto cp0_unimplemented;
case 3:
// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- rn = "UserTraceData";
+ register_name = "UserTraceData";
goto cp0_unimplemented;
case 4:
// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- rn = "TraceBPC";
+ register_name = "TraceBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -9515,7 +9520,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
/* EJTAG support */
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
- rn = "DEPC";
+ register_name = "DEPC";
break;
default:
goto cp0_unimplemented;
@@ -9525,35 +9530,35 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_performance0(cpu_env, arg);
- rn = "Performance0";
+ register_name = "Performance0";
break;
case 1:
// gen_helper_mtc0_performance1(cpu_env, arg);
- rn = "Performance1";
+ register_name = "Performance1";
goto cp0_unimplemented;
case 2:
// gen_helper_mtc0_performance2(cpu_env, arg);
- rn = "Performance2";
+ register_name = "Performance2";
goto cp0_unimplemented;
case 3:
// gen_helper_mtc0_performance3(cpu_env, arg);
- rn = "Performance3";
+ register_name = "Performance3";
goto cp0_unimplemented;
case 4:
// gen_helper_mtc0_performance4(cpu_env, arg);
- rn = "Performance4";
+ register_name = "Performance4";
goto cp0_unimplemented;
case 5:
// gen_helper_mtc0_performance5(cpu_env, arg);
- rn = "Performance5";
+ register_name = "Performance5";
goto cp0_unimplemented;
case 6:
// gen_helper_mtc0_performance6(cpu_env, arg);
- rn = "Performance6";
+ register_name = "Performance6";
goto cp0_unimplemented;
case 7:
// gen_helper_mtc0_performance7(cpu_env, arg);
- rn = "Performance7";
+ register_name = "Performance7";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -9564,7 +9569,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
gen_helper_mtc0_errctl(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
- rn = "ErrCtl";
+ register_name = "ErrCtl";
break;
default:
goto cp0_unimplemented;
@@ -9577,7 +9582,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 2:
case 3:
/* ignored */
- rn = "CacheErr";
+ register_name = "CacheErr";
break;
default:
goto cp0_unimplemented;
@@ -9590,14 +9595,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 4:
case 6:
gen_helper_mtc0_taglo(cpu_env, arg);
- rn = "TagLo";
+ register_name = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
gen_helper_mtc0_datalo(cpu_env, arg);
- rn = "DataLo";
+ register_name = "DataLo";
break;
default:
goto cp0_unimplemented;
@@ -9610,17 +9615,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 4:
case 6:
gen_helper_mtc0_taghi(cpu_env, arg);
- rn = "TagHi";
+ register_name = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
gen_helper_mtc0_datahi(cpu_env, arg);
- rn = "DataHi";
+ register_name = "DataHi";
break;
default:
- rn = "invalid sel";
+ register_name = "invalid sel";
goto cp0_unimplemented;
}
break;
@@ -9628,7 +9633,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
- rn = "ErrorEPC";
+ register_name = "ErrorEPC";
break;
default:
goto cp0_unimplemented;
@@ -9639,7 +9644,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
/* EJTAG support */
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
- rn = "DESAVE";
+ register_name = "DESAVE";
break;
case 2:
case 3:
@@ -9650,7 +9655,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
- rn = "KScratch";
+ register_name = "KScratch";
break;
default:
goto cp0_unimplemented;
@@ -9659,7 +9664,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
- trace_mips_translate_c0("dmtc0", rn, reg, sel);
+ trace_mips_translate_c0("dmtc0", register_name, reg, sel);
/* For simplicity assume that all writes can cause interrupts. */
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
@@ -9672,7 +9677,8 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
return;
cp0_unimplemented:
- qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n",
+ register_name, reg, sel);
}
#endif /* TARGET_MIPS64 */
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
` (10 preceding siblings ...)
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 11/12] target/mips: Rename 'rn' to 'register_name' Aleksandar Markovic
@ 2019-01-18 16:59 ` Aleksandar Markovic
2020-11-14 18:23 ` Philippe Mathieu-Daudé
2019-01-21 19:19 ` [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Peter Maydell
12 siblings, 1 reply; 18+ messages in thread
From: Aleksandar Markovic @ 2019-01-18 16:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Fredrik Noring <noring@nocrew.org>
The 32 R5900 128-bit registers are split into two 64-bit halves:
the lower halves are the GPRs and the upper halves are accessible
by the R5900-specific multimedia instructions.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 3 +++
target/mips/translate.c | 16 ++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 21daf50..c4da7df 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -429,6 +429,9 @@ struct TCState {
float_status msa_fp_status;
+ /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */
+ uint64_t mmr[32];
+
#define NUMBER_OF_MXU_REGISTERS 16
target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
target_ulong mxu_cr;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3ac0b1f..ab307c4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2455,6 +2455,11 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31;
static TCGv_i64 fpu_f64[32];
static TCGv_i64 msa_wr_d[64];
+#if defined(TARGET_MIPS64)
+/* Upper halves of R5900's 128-bit registers: MMRs (multimedia registers) */
+static TCGv_i64 cpu_mmr[32];
+#endif
+
#if !defined(TARGET_MIPS64)
/* MXU registers */
static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
@@ -29845,6 +29850,17 @@ void mips_tcg_init(void)
fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMIPSState, active_fpu.fcr31),
"fcr31");
+
+#if defined(TARGET_MIPS64)
+ cpu_mmr[0] = NULL;
+ for (i = 1; i < 32; i++) {
+ cpu_mmr[i] = tcg_global_mem_new_i64(cpu_env,
+ offsetof(CPUMIPSState,
+ active_tc.mmr[i]),
+ regnames[i]);
+ }
+#endif
+
#if !defined(TARGET_MIPS64)
for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
mxu_gpr[i] = tcg_global_mem_new(cpu_env,
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
` (11 preceding siblings ...)
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers Aleksandar Markovic
@ 2019-01-21 19:19 ` Peter Maydell
12 siblings, 0 replies; 18+ messages in thread
From: Peter Maydell @ 2019-01-21 19:19 UTC (permalink / raw)
To: Aleksandar Markovic; +Cc: QEMU Developers, Aleksandar Markovic
On Fri, 18 Jan 2019 at 16:59, Aleksandar Markovic
<aleksandar.markovic@rt-rk.com> wrote:
>
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> The following changes since commit 681d61362d3f766a00806b89d6581869041f73cb:
>
> Merge remote-tracking branch 'remotes/jnsnow/tags/bitmaps-pull-request' into staging (2019-01-17 12:48:42 +0000)
>
> are available in the git repository at:
>
> https://github.com/AMarkovic/qemu tags/mips-queue-january-17-2019-v2
>
> for you to fetch changes up to a168a796e1c251787fcdf2d9ca1e9e69cb86ffcd:
>
> target/mips: Introduce 32 R5900 multimedia registers (2019-01-18 16:53:28 +0100)
>
> ----------------------------------------------------------------
>
> MIPS queue for January 17, 2019 - v2
>
> v1->v2:
> - fixed "make check" error
>
> content:
> - provide access to configuration registers SAARI, SAAR, and
> MemoryMapID
> - update Inter-Thread Communication Unit
> - CP0-related cleanups
> - introduce R5900 multimedia registers
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PULL v2 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers Aleksandar Markovic
@ 2019-02-14 18:40 ` Peter Maydell
2019-02-14 18:58 ` Aleksandar Markovic
0 siblings, 1 reply; 18+ messages in thread
From: Peter Maydell @ 2019-02-14 18:40 UTC (permalink / raw)
To: Aleksandar Markovic; +Cc: QEMU Developers, Aleksandar Markovic
On Fri, 18 Jan 2019 at 16:59, Aleksandar Markovic
<aleksandar.markovic@rt-rk.com> wrote:
>
> From: Yongbok Kim <yongbok.kim@mips.com>
>
> Update ITU to utilize SAARI and SAAR CP0 registers.
Hi; Coverity complains (CID 1398648) about this bit of code:
> -static void itc_reconfigure(MIPSITUState *tag)
> +void itc_reconfigure(MIPSITUState *tag)
> {
> uint64_t *am = &tag->ITCAddressMap[0];
> MemoryRegion *mr = &tag->storage_io;
> @@ -92,6 +92,12 @@ static void itc_reconfigure(MIPSITUState *tag)
> uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
> bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
>
> + if (tag->saar_present) {
> + address = ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4;
> + size = 1 << ((*(uint64_t *) tag->saar >> 1) & 0x1f);
> + is_enabled = *(uint64_t *) tag->saar & 1;
> + }
> +
because the "1 << ..." calculation of size is done as a 32-bit
signed integer which may then be unintentionally sign-extended
into the 64-bit result. Using "1ULL" instead of "1" on the LHS
of the shift would fix this.
thanks
-- PMM
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PULL v2 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
2019-02-14 18:40 ` Peter Maydell
@ 2019-02-14 18:58 ` Aleksandar Markovic
0 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-02-14 18:58 UTC (permalink / raw)
To: Peter Maydell, Aleksandar Markovic; +Cc: QEMU Developers
> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: Thursday, February 14, 2019 7:40 PM
> To: Aleksandar Markovic
> Cc: QEMU Developers; Aleksandar Markovic
> Subject: Re: [PULL v2 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
>
> On Fri, 18 Jan 2019 at 16:59, Aleksandar Markovic
> <aleksandar.markovic@rt-rk.com> wrote:
> >
> > From: Yongbok Kim <yongbok.kim@mips.com>
> >
> > Update ITU to utilize SAARI and SAAR CP0 registers.
>
> Hi; Coverity complains (CID 1398648) about this bit of code:
>
> > -static void itc_reconfigure(MIPSITUState *tag)
> > +void itc_reconfigure(MIPSITUState *tag)
> > {
> > uint64_t *am = &tag->ITCAddressMap[0];
> > MemoryRegion *mr = &tag->storage_io;
> > @@ -92,6 +92,12 @@ static void itc_reconfigure(MIPSITUState *tag)
> > uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
> > bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
> >
> > + if (tag->saar_present) {
> > + address = ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4;
> > + size = 1 << ((*(uint64_t *) tag->saar >> 1) & 0x1f);
> > + is_enabled = *(uint64_t *) tag->saar & 1;
> > + }
> > +
>
> because the "1 << ..." calculation of size is done as a 32-bit
> signed integer which may then be unintentionally sign-extended
> into the 64-bit result. Using "1ULL" instead of "1" on the LHS
> of the shift would fix this.
>
Thanks, I'll try to integrate the fix soon.
Aleksandar
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers Aleksandar Markovic
@ 2020-11-14 18:23 ` Philippe Mathieu-Daudé
2020-12-12 10:19 ` Fredrik Noring
0 siblings, 1 reply; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-11-14 18:23 UTC (permalink / raw)
To: Aleksandar Markovic, Fredrik Noring
Cc: Peter Maydell, qemu-devel@nongnu.org Developers, Aleksandar Markovic
Hi Fredrik and Aleksandar,
On Fri, Jan 18, 2019 at 6:10 PM Aleksandar Markovic
<aleksandar.markovic@rt-rk.com> wrote:
>
> From: Fredrik Noring <noring@nocrew.org>
>
> The 32 R5900 128-bit registers are split into two 64-bit halves:
> the lower halves are the GPRs and the upper halves are accessible
> by the R5900-specific multimedia instructions.
>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Fredrik Noring <noring@nocrew.org>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/cpu.h | 3 +++
> target/mips/translate.c | 16 ++++++++++++++++
> 2 files changed, 19 insertions(+)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 21daf50..c4da7df 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -429,6 +429,9 @@ struct TCState {
>
> float_status msa_fp_status;
>
> + /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */
> + uint64_t mmr[32];
FYI using MMI then migrating fails because these registers are not migrated.
> +
> #define NUMBER_OF_MXU_REGISTERS 16
> target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
> target_ulong mxu_cr;
...
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers
2020-11-14 18:23 ` Philippe Mathieu-Daudé
@ 2020-12-12 10:19 ` Fredrik Noring
0 siblings, 0 replies; 18+ messages in thread
From: Fredrik Noring @ 2020-12-12 10:19 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Aleksandar Markovic, Peter Maydell, Maciej W. Rozycki,
qemu-devel@nongnu.org Developers, Aleksandar Markovic
On Sat, Nov 14, 2020 at 07:23:10PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Fredrik and Aleksandar,
>
> On Fri, Jan 18, 2019 at 6:10 PM Aleksandar Markovic
> <aleksandar.markovic@rt-rk.com> wrote:
> >
> > From: Fredrik Noring <noring@nocrew.org>
> >
> > The 32 R5900 128-bit registers are split into two 64-bit halves:
> > the lower halves are the GPRs and the upper halves are accessible
> > by the R5900-specific multimedia instructions.
> >
> > Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> > Signed-off-by: Fredrik Noring <noring@nocrew.org>
> > Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> > ---
> > target/mips/cpu.h | 3 +++
> > target/mips/translate.c | 16 ++++++++++++++++
> > 2 files changed, 19 insertions(+)
> >
> > diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> > index 21daf50..c4da7df 100644
> > --- a/target/mips/cpu.h
> > +++ b/target/mips/cpu.h
> > @@ -429,6 +429,9 @@ struct TCState {
> >
> > float_status msa_fp_status;
> >
> > + /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */
> > + uint64_t mmr[32];
>
> FYI using MMI then migrating fails because these registers are not migrated.
We can postpone the R5900 MMIs, in my opinion, because they are not (yet)
supported by modern 5.x R5900 Linux kernels anyway. The details of R5900
psABIs having them need to be sorted out too.
Fredrik
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2020-12-12 10:20 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 01/12] target/mips: Move comment containing summary of CP0 registers Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 02/12] target/mips: Add preprocessor constants for 32 major " Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 03/12] target/mips: Use " Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 04/12] target/mips: Add fields for SAARI and SAAR " Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 05/12] target/mips: Provide R/W access to " Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 06/12] target/mips: Add field and R/W access to ITU control register ICR0 Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers Aleksandar Markovic
2019-02-14 18:40 ` Peter Maydell
2019-02-14 18:58 ` Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 08/12] target/mips: Update ITU to handle bus errors Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 09/12] target/mips: Amend preprocessor constants for CP0 registers Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 10/12] target/mips: Add CP0 register MemoryMapID Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 11/12] target/mips: Rename 'rn' to 'register_name' Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers Aleksandar Markovic
2020-11-14 18:23 ` Philippe Mathieu-Daudé
2020-12-12 10:19 ` Fredrik Noring
2019-01-21 19:19 ` [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Peter Maydell
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