* Re: [PATCH] drm/i915: Enable workaround for pixel shader dispatch hang
2019-04-15 14:21 [PATCH] drm/i915: Enable workaround for pixel shader dispatch hang Mika Kuoppala
@ 2019-04-15 14:23 ` Chris Wilson
2019-04-15 14:25 ` Ville Syrjälä
` (3 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2019-04-15 14:23 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-04-15 15:21:22)
> Set chicken bits to workaround a possible pixel shader
> dispatch hang.
>
> Bspec: 14091, ID#0651
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_workarounds.c | 9 +++++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c1c0f7ab03e9..499cc843443d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8902,11 +8902,15 @@ enum {
> #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
> #define DOP_CLOCK_GATING_DISABLE (1 << 0)
> #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> +#define GEN8_DISABLE_RR_ARBITRATION (1 << 1)
> #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
>
> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
>
> +#define GEN8_ROW_CHICKEN4 _MMIO(0xe48c)
> +#define GEN8_DISABLE_TDL_FIX (1 << 3)
> +
> #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
> #define GEN8_ST_PO_DISABLE (1 << 13)
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ccaf63679435..4f1a7500ca07 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -294,6 +294,15 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine)
> FLOW_CONTROL_ENABLE |
> PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>
> + /* Bspec wa: 0651, skl G0 onwards */
> + if (!IS_SKL_REVID(i915, SKL_REVID_A0, SKL_REVID_F0)) {
IS_SKL_REVID(i915, SKL_REVID_G0, REVID_FOREVER) ?
-Chris
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^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH] drm/i915: Enable workaround for pixel shader dispatch hang
2019-04-15 14:21 [PATCH] drm/i915: Enable workaround for pixel shader dispatch hang Mika Kuoppala
2019-04-15 14:23 ` Chris Wilson
@ 2019-04-15 14:25 ` Ville Syrjälä
2019-04-15 14:29 ` Chris Wilson
2019-04-15 14:38 ` Mika Kuoppala
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Ville Syrjälä @ 2019-04-15 14:25 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
On Mon, Apr 15, 2019 at 05:21:22PM +0300, Mika Kuoppala wrote:
> Set chicken bits to workaround a possible pixel shader
> dispatch hang.
>
> Bspec: 14091, ID#0651
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_workarounds.c | 9 +++++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c1c0f7ab03e9..499cc843443d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8902,11 +8902,15 @@ enum {
> #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
> #define DOP_CLOCK_GATING_DISABLE (1 << 0)
> #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> +#define GEN8_DISABLE_RR_ARBITRATION (1 << 1)
> #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
>
> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
>
> +#define GEN8_ROW_CHICKEN4 _MMIO(0xe48c)
> +#define GEN8_DISABLE_TDL_FIX (1 << 3)
> +
> #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
> #define GEN8_ST_PO_DISABLE (1 << 13)
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ccaf63679435..4f1a7500ca07 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -294,6 +294,15 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine)
> FLOW_CONTROL_ENABLE |
> PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>
> + /* Bspec wa: 0651, skl G0 onwards */
> + if (!IS_SKL_REVID(i915, SKL_REVID_A0, SKL_REVID_F0)) {
Aren't all those pre-production?
> + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> + GEN8_DISABLE_RR_ARBITRATION);
> +
> + /* Make sure the default holds to enable TDL fix */
> + WA_CLR_BIT_MASKED(GEN8_ROW_CHICKEN4, GEN8_DISABLE_TDL_FIX);
> + }
> +
> /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
> if (!IS_COFFEELAKE(i915))
> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH] drm/i915: Enable workaround for pixel shader dispatch hang
2019-04-15 14:25 ` Ville Syrjälä
@ 2019-04-15 14:29 ` Chris Wilson
2019-04-15 14:34 ` Mika Kuoppala
0 siblings, 1 reply; 11+ messages in thread
From: Chris Wilson @ 2019-04-15 14:29 UTC (permalink / raw)
To: Mika Kuoppala, Ville Syrjälä; +Cc: intel-gfx
Quoting Ville Syrjälä (2019-04-15 15:25:11)
> On Mon, Apr 15, 2019 at 05:21:22PM +0300, Mika Kuoppala wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> > index ccaf63679435..4f1a7500ca07 100644
> > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > @@ -294,6 +294,15 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine)
> > FLOW_CONTROL_ENABLE |
> > PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
> >
> > + /* Bspec wa: 0651, skl G0 onwards */
> > + if (!IS_SKL_REVID(i915, SKL_REVID_A0, SKL_REVID_F0)) {
>
> Aren't all those pre-production?
intel_detect_preproduction_hw() says yes.
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH] drm/i915: Enable workaround for pixel shader dispatch hang
2019-04-15 14:29 ` Chris Wilson
@ 2019-04-15 14:34 ` Mika Kuoppala
0 siblings, 0 replies; 11+ messages in thread
From: Mika Kuoppala @ 2019-04-15 14:34 UTC (permalink / raw)
To: Chris Wilson, Ville Syrjälä; +Cc: intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Ville Syrjälä (2019-04-15 15:25:11)
>> On Mon, Apr 15, 2019 at 05:21:22PM +0300, Mika Kuoppala wrote:
>> > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
>> > index ccaf63679435..4f1a7500ca07 100644
>> > --- a/drivers/gpu/drm/i915/intel_workarounds.c
>> > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
>> > @@ -294,6 +294,15 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine)
>> > FLOW_CONTROL_ENABLE |
>> > PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>> >
>> > + /* Bspec wa: 0651, skl G0 onwards */
>> > + if (!IS_SKL_REVID(i915, SKL_REVID_A0, SKL_REVID_F0)) {
>>
>> Aren't all those pre-production?
>
> intel_detect_preproduction_hw() says yes.
v2 coming up. The inverse check got left there as I needed
to filter out bxt ones. which turned out to be preprod.
The bell should have rung at that point, but didn't.
-Mika
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH] drm/i915: Enable workaround for pixel shader dispatch hang
2019-04-15 14:21 [PATCH] drm/i915: Enable workaround for pixel shader dispatch hang Mika Kuoppala
2019-04-15 14:23 ` Chris Wilson
2019-04-15 14:25 ` Ville Syrjälä
@ 2019-04-15 14:38 ` Mika Kuoppala
2019-04-15 14:45 ` Mika Kuoppala
2019-04-15 15:43 ` ✗ Fi.CI.BAT: failure for drm/i915: Enable workaround for pixel shader dispatch hang (rev3) Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Mika Kuoppala @ 2019-04-15 14:38 UTC (permalink / raw)
To: intel-gfx
Set chicken bits to workaround a possible pixel shader
dispatch hang.
v2: no need to filter out preprod skl (Ville, Chris)
Bspec: 14091, ID#0651
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1c0f7ab03e9..499cc843443d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8902,11 +8902,15 @@ enum {
#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
+#define GEN8_DISABLE_RR_ARBITRATION (1 << 1)
#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
+#define GEN8_ROW_CHICKEN4 _MMIO(0xe48c)
+#define GEN8_DISABLE_TDL_FIX (1 << 3)
+
#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
#define GEN8_ST_PO_DISABLE (1 << 13)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ccaf63679435..89d8797c91be 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -294,6 +294,11 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine)
FLOW_CONTROL_ENABLE |
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
+ /* Bspec wa: 0651, disable rr arb and enable tdl fix */
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN8_DISABLE_RR_ARBITRATION);
+ WA_CLR_BIT_MASKED(GEN8_ROW_CHICKEN4, GEN8_DISABLE_TDL_FIX);
+
/* Syncing dependencies between camera and graphics:skl,bxt,kbl */
if (!IS_COFFEELAKE(i915))
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH] drm/i915: Enable workaround for pixel shader dispatch hang
2019-04-15 14:21 [PATCH] drm/i915: Enable workaround for pixel shader dispatch hang Mika Kuoppala
` (2 preceding siblings ...)
2019-04-15 14:38 ` Mika Kuoppala
@ 2019-04-15 14:45 ` Mika Kuoppala
2019-04-16 8:24 ` Chris Wilson
2019-04-15 15:43 ` ✗ Fi.CI.BAT: failure for drm/i915: Enable workaround for pixel shader dispatch hang (rev3) Patchwork
4 siblings, 1 reply; 11+ messages in thread
From: Mika Kuoppala @ 2019-04-15 14:45 UTC (permalink / raw)
To: intel-gfx
Set chicken bits to workaround a possible pixel shader
dispatch hang.
v2: no need to filter out preprod skl (Ville, Chris)
v3: formatting
Bspec: 14091, ID#0651
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1c0f7ab03e9..499cc843443d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8902,11 +8902,15 @@ enum {
#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
+#define GEN8_DISABLE_RR_ARBITRATION (1 << 1)
#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
+#define GEN8_ROW_CHICKEN4 _MMIO(0xe48c)
+#define GEN8_DISABLE_TDL_FIX (1 << 3)
+
#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
#define GEN8_ST_PO_DISABLE (1 << 13)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ccaf63679435..b4709de49552 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -294,6 +294,10 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine)
FLOW_CONTROL_ENABLE |
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
+ /* Bspec wa: 0651, disable rr arb and enable tdl fix */
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, GEN8_DISABLE_RR_ARBITRATION);
+ WA_CLR_BIT_MASKED(GEN8_ROW_CHICKEN4, GEN8_DISABLE_TDL_FIX);
+
/* Syncing dependencies between camera and graphics:skl,bxt,kbl */
if (!IS_COFFEELAKE(i915))
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
--
2.17.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH] drm/i915: Enable workaround for pixel shader dispatch hang
2019-04-15 14:45 ` Mika Kuoppala
@ 2019-04-16 8:24 ` Chris Wilson
2019-04-16 13:26 ` Mika Kuoppala
0 siblings, 1 reply; 11+ messages in thread
From: Chris Wilson @ 2019-04-16 8:24 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-04-15 15:45:29)
> Set chicken bits to workaround a possible pixel shader
> dispatch hang.
>
> v2: no need to filter out preprod skl (Ville, Chris)
> v3: formatting
>
> Bspec: 14091, ID#0651
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c1c0f7ab03e9..499cc843443d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8902,11 +8902,15 @@ enum {
> #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
> #define DOP_CLOCK_GATING_DISABLE (1 << 0)
> #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> +#define GEN8_DISABLE_RR_ARBITRATION (1 << 1)
> #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
>
> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
>
> +#define GEN8_ROW_CHICKEN4 _MMIO(0xe48c)
> +#define GEN8_DISABLE_TDL_FIX (1 << 3)
> +
> #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
> #define GEN8_ST_PO_DISABLE (1 << 13)
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ccaf63679435..b4709de49552 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -294,6 +294,10 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine)
> FLOW_CONTROL_ENABLE |
> PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>
> + /* Bspec wa: 0651, disable rr arb and enable tdl fix */
> + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, GEN8_DISABLE_RR_ARBITRATION);
> + WA_CLR_BIT_MASKED(GEN8_ROW_CHICKEN4, GEN8_DISABLE_TDL_FIX);
In your first patch, you had this only applying to Skylake. Is that
still the case? i.e. do we need if (IS_SKYLAKE()) { ... }
-Chris
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^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH] drm/i915: Enable workaround for pixel shader dispatch hang
2019-04-16 8:24 ` Chris Wilson
@ 2019-04-16 13:26 ` Mika Kuoppala
2019-04-16 13:30 ` Chris Wilson
0 siblings, 1 reply; 11+ messages in thread
From: Mika Kuoppala @ 2019-04-16 13:26 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2019-04-15 15:45:29)
>> Set chicken bits to workaround a possible pixel shader
>> dispatch hang.
>>
>> v2: no need to filter out preprod skl (Ville, Chris)
>> v3: formatting
>>
>> Bspec: 14091, ID#0651
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
>> drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
>> 2 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index c1c0f7ab03e9..499cc843443d 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8902,11 +8902,15 @@ enum {
>> #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
>> #define DOP_CLOCK_GATING_DISABLE (1 << 0)
>> #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
>> +#define GEN8_DISABLE_RR_ARBITRATION (1 << 1)
>> #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
>>
>> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
>> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
>>
>> +#define GEN8_ROW_CHICKEN4 _MMIO(0xe48c)
>> +#define GEN8_DISABLE_TDL_FIX (1 << 3)
>> +
>> #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
>> #define GEN8_ST_PO_DISABLE (1 << 13)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
>> index ccaf63679435..b4709de49552 100644
>> --- a/drivers/gpu/drm/i915/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
>> @@ -294,6 +294,10 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine)
>> FLOW_CONTROL_ENABLE |
>> PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>>
>> + /* Bspec wa: 0651, disable rr arb and enable tdl fix */
>> + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, GEN8_DISABLE_RR_ARBITRATION);
>> + WA_CLR_BIT_MASKED(GEN8_ROW_CHICKEN4, GEN8_DISABLE_TDL_FIX);
>
> In your first patch, you had this only applying to Skylake. Is that
> still the case? i.e. do we need if (IS_SKYLAKE()) { ... }
I had !SKL_REVID() so I only wanted to exclude everything up to G0.
Bspec on row chicken 2 says that we want this from skl G0 onwards and
bxt b0 onwards up to ICL. So with preprods out, I think it holds.
-Mika
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^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH] drm/i915: Enable workaround for pixel shader dispatch hang
2019-04-16 13:26 ` Mika Kuoppala
@ 2019-04-16 13:30 ` Chris Wilson
0 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2019-04-16 13:30 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-04-16 14:26:19)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > Quoting Mika Kuoppala (2019-04-15 15:45:29)
> >> Set chicken bits to workaround a possible pixel shader
> >> dispatch hang.
> >>
> >> v2: no need to filter out preprod skl (Ville, Chris)
> >> v3: formatting
> >>
> >> Bspec: 14091, ID#0651
> >> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> >> drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
> >> 2 files changed, 8 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index c1c0f7ab03e9..499cc843443d 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -8902,11 +8902,15 @@ enum {
> >> #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
> >> #define DOP_CLOCK_GATING_DISABLE (1 << 0)
> >> #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> >> +#define GEN8_DISABLE_RR_ARBITRATION (1 << 1)
> >> #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
> >>
> >> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> >> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
> >>
> >> +#define GEN8_ROW_CHICKEN4 _MMIO(0xe48c)
> >> +#define GEN8_DISABLE_TDL_FIX (1 << 3)
> >> +
> >> #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
> >> #define GEN8_ST_PO_DISABLE (1 << 13)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> >> index ccaf63679435..b4709de49552 100644
> >> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> >> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> >> @@ -294,6 +294,10 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine)
> >> FLOW_CONTROL_ENABLE |
> >> PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
> >>
> >> + /* Bspec wa: 0651, disable rr arb and enable tdl fix */
> >> + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, GEN8_DISABLE_RR_ARBITRATION);
> >> + WA_CLR_BIT_MASKED(GEN8_ROW_CHICKEN4, GEN8_DISABLE_TDL_FIX);
> >
> > In your first patch, you had this only applying to Skylake. Is that
> > still the case? i.e. do we need if (IS_SKYLAKE()) { ... }
>
> I had !SKL_REVID() so I only wanted to exclude everything up to G0.
>
> Bspec on row chicken 2 says that we want this from skl G0 onwards and
> bxt b0 onwards up to ICL. So with preprods out, I think it holds.
Ok, I'm easily convinced.
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 11+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Enable workaround for pixel shader dispatch hang (rev3)
2019-04-15 14:21 [PATCH] drm/i915: Enable workaround for pixel shader dispatch hang Mika Kuoppala
` (3 preceding siblings ...)
2019-04-15 14:45 ` Mika Kuoppala
@ 2019-04-15 15:43 ` Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-04-15 15:43 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Enable workaround for pixel shader dispatch hang (rev3)
URL : https://patchwork.freedesktop.org/series/59504/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5934 -> Patchwork_12800
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_12800 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12800, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/59504/revisions/3/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12800:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_basic@gtt-bsd:
- fi-icl-y: PASS -> INCOMPLETE
Known issues
------------
Here are the changes found in Patchwork_12800 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_exec@basic:
- fi-icl-u3: PASS -> INCOMPLETE [fdo#107713]
* igt@kms_busy@basic-flip-a:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_chamelium@hdmi-crc-fast:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +57
#### Possible fixes ####
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: INCOMPLETE [fdo#108602] / [fdo#108744] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] -> PASS
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
Participating hosts (50 -> 40)
------------------------------
Additional (1): fi-bsw-n3050
Missing (11): fi-kbl-soraka fi-ilk-m540 fi-skl-6770hq fi-byt-squawks fi-icl-u2 fi-bwr-2160 fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus fi-skl-6700k2 fi-snb-2600
Build changes
-------------
* Linux: CI_DRM_5934 -> Patchwork_12800
CI_DRM_5934: cc5334c0e706ec423c5f1a139cf3da7bd3287db6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4946: 56bdc68638cec64c6b02cd6b220b52b76059b51a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12800: e2e492f915bfab74f7d8aaa6dc7bcb23d2605759 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e2e492f915bf drm/i915: Enable workaround for pixel shader dispatch hang
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12800/
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^ permalink raw reply [flat|nested] 11+ messages in thread