From: Yong Wu <yong.wu@mediatek.com>
To: Chao Hao <chao.hao@mediatek.com>
Cc: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
<iommu@lists.linux-foundation.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>, <wsd_upstream@mediatek.com>,
FY Yang <fy.yang@mediatek.com>, Jun Yan <jun.yan@mediatek.com>
Subject: Re: [PATCH v3 4/7] iommu/mediatek: Move inv_sel_reg into the plat_data
Date: Mon, 25 May 2020 14:22:23 +0800 [thread overview]
Message-ID: <1590387743.13912.11.camel@mhfsdcap03> (raw)
In-Reply-To: <20200509083654.5178-5-chao.hao@mediatek.com>
On Sat, 2020-05-09 at 16:36 +0800, Chao Hao wrote:
> For mt6779, MMU_INVLDT_SEL register's offset is changed from
At this patch, the register is still called by "MMU_INV_SEL".
> 0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to
> use it.
> In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it
> before mt6779.
>
> Signed-off-by: Chao Hao <chao.hao@mediatek.com>
> ---
> drivers/iommu/mtk_iommu.c | 9 ++++++---
> drivers/iommu/mtk_iommu.h | 1 +
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 9ede327a418d..d73de987f8be 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -37,7 +37,7 @@
> #define REG_MMU_INVLD_START_A 0x024
> #define REG_MMU_INVLD_END_A 0x028
>
> -#define REG_MMU_INV_SEL 0x038
> +#define REG_MMU_INV_SEL_GEN1 0x038
> #define F_INVLD_EN0 BIT(0)
> #define F_INVLD_EN1 BIT(1)
>
> @@ -167,7 +167,7 @@ static void mtk_iommu_tlb_flush_all(void *cookie)
>
> for_each_m4u(data) {
> writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
> - data->base + REG_MMU_INV_SEL);
> + data->base + data->plat_data->inv_sel_reg);
> writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
> wmb(); /* Make sure the tlb flush all done */
> }
> @@ -184,7 +184,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
> for_each_m4u(data) {
> spin_lock_irqsave(&data->tlb_lock, flags);
> writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
> - data->base + REG_MMU_INV_SEL);
> + data->base + data->plat_data->inv_sel_reg);
>
> writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
> writel_relaxed(iova + size - 1,
> @@ -784,6 +784,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
> .has_4gb_mode = true,
> .has_bclk = true,
> .has_vld_pa_rng = true,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
nitpick: align '=' with the next line.
> .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
> };
>
> @@ -792,12 +793,14 @@ static const struct mtk_iommu_plat_data mt8173_data = {
> .has_4gb_mode = true,
> .has_bclk = true,
> .reset_axi = true,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
align '='
> .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
> };
>
> static const struct mtk_iommu_plat_data mt8183_data = {
> .m4u_plat = M4U_MT8183,
> .reset_axi = true,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},
> };
>
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index d711ac630037..afd7a2de5c1e 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -43,6 +43,7 @@ struct mtk_iommu_plat_data {
> bool has_misc_ctrl;
> bool has_vld_pa_rng;
> bool reset_axi;
> + u32 inv_sel_reg;
> unsigned char larbid_remap[MTK_LARB_NR_MAX];
> };
>
WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Chao Hao <chao.hao@mediatek.com>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
iommu@lists.linux-foundation.org,
Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
Jun Yan <jun.yan@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 4/7] iommu/mediatek: Move inv_sel_reg into the plat_data
Date: Mon, 25 May 2020 14:22:23 +0800 [thread overview]
Message-ID: <1590387743.13912.11.camel@mhfsdcap03> (raw)
In-Reply-To: <20200509083654.5178-5-chao.hao@mediatek.com>
On Sat, 2020-05-09 at 16:36 +0800, Chao Hao wrote:
> For mt6779, MMU_INVLDT_SEL register's offset is changed from
At this patch, the register is still called by "MMU_INV_SEL".
> 0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to
> use it.
> In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it
> before mt6779.
>
> Signed-off-by: Chao Hao <chao.hao@mediatek.com>
> ---
> drivers/iommu/mtk_iommu.c | 9 ++++++---
> drivers/iommu/mtk_iommu.h | 1 +
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 9ede327a418d..d73de987f8be 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -37,7 +37,7 @@
> #define REG_MMU_INVLD_START_A 0x024
> #define REG_MMU_INVLD_END_A 0x028
>
> -#define REG_MMU_INV_SEL 0x038
> +#define REG_MMU_INV_SEL_GEN1 0x038
> #define F_INVLD_EN0 BIT(0)
> #define F_INVLD_EN1 BIT(1)
>
> @@ -167,7 +167,7 @@ static void mtk_iommu_tlb_flush_all(void *cookie)
>
> for_each_m4u(data) {
> writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
> - data->base + REG_MMU_INV_SEL);
> + data->base + data->plat_data->inv_sel_reg);
> writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
> wmb(); /* Make sure the tlb flush all done */
> }
> @@ -184,7 +184,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
> for_each_m4u(data) {
> spin_lock_irqsave(&data->tlb_lock, flags);
> writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
> - data->base + REG_MMU_INV_SEL);
> + data->base + data->plat_data->inv_sel_reg);
>
> writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
> writel_relaxed(iova + size - 1,
> @@ -784,6 +784,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
> .has_4gb_mode = true,
> .has_bclk = true,
> .has_vld_pa_rng = true,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
nitpick: align '=' with the next line.
> .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
> };
>
> @@ -792,12 +793,14 @@ static const struct mtk_iommu_plat_data mt8173_data = {
> .has_4gb_mode = true,
> .has_bclk = true,
> .reset_axi = true,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
align '='
> .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
> };
>
> static const struct mtk_iommu_plat_data mt8183_data = {
> .m4u_plat = M4U_MT8183,
> .reset_axi = true,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},
> };
>
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index d711ac630037..afd7a2de5c1e 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -43,6 +43,7 @@ struct mtk_iommu_plat_data {
> bool has_misc_ctrl;
> bool has_vld_pa_rng;
> bool reset_axi;
> + u32 inv_sel_reg;
> unsigned char larbid_remap[MTK_LARB_NR_MAX];
> };
>
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Chao Hao <chao.hao@mediatek.com>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
wsd_upstream@mediatek.com, Joerg Roedel <joro@8bytes.org>,
linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
Jun Yan <jun.yan@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 4/7] iommu/mediatek: Move inv_sel_reg into the plat_data
Date: Mon, 25 May 2020 14:22:23 +0800 [thread overview]
Message-ID: <1590387743.13912.11.camel@mhfsdcap03> (raw)
In-Reply-To: <20200509083654.5178-5-chao.hao@mediatek.com>
On Sat, 2020-05-09 at 16:36 +0800, Chao Hao wrote:
> For mt6779, MMU_INVLDT_SEL register's offset is changed from
At this patch, the register is still called by "MMU_INV_SEL".
> 0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to
> use it.
> In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it
> before mt6779.
>
> Signed-off-by: Chao Hao <chao.hao@mediatek.com>
> ---
> drivers/iommu/mtk_iommu.c | 9 ++++++---
> drivers/iommu/mtk_iommu.h | 1 +
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 9ede327a418d..d73de987f8be 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -37,7 +37,7 @@
> #define REG_MMU_INVLD_START_A 0x024
> #define REG_MMU_INVLD_END_A 0x028
>
> -#define REG_MMU_INV_SEL 0x038
> +#define REG_MMU_INV_SEL_GEN1 0x038
> #define F_INVLD_EN0 BIT(0)
> #define F_INVLD_EN1 BIT(1)
>
> @@ -167,7 +167,7 @@ static void mtk_iommu_tlb_flush_all(void *cookie)
>
> for_each_m4u(data) {
> writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
> - data->base + REG_MMU_INV_SEL);
> + data->base + data->plat_data->inv_sel_reg);
> writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
> wmb(); /* Make sure the tlb flush all done */
> }
> @@ -184,7 +184,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
> for_each_m4u(data) {
> spin_lock_irqsave(&data->tlb_lock, flags);
> writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
> - data->base + REG_MMU_INV_SEL);
> + data->base + data->plat_data->inv_sel_reg);
>
> writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
> writel_relaxed(iova + size - 1,
> @@ -784,6 +784,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
> .has_4gb_mode = true,
> .has_bclk = true,
> .has_vld_pa_rng = true,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
nitpick: align '=' with the next line.
> .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
> };
>
> @@ -792,12 +793,14 @@ static const struct mtk_iommu_plat_data mt8173_data = {
> .has_4gb_mode = true,
> .has_bclk = true,
> .reset_axi = true,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
align '='
> .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
> };
>
> static const struct mtk_iommu_plat_data mt8183_data = {
> .m4u_plat = M4U_MT8183,
> .reset_axi = true,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},
> };
>
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index d711ac630037..afd7a2de5c1e 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -43,6 +43,7 @@ struct mtk_iommu_plat_data {
> bool has_misc_ctrl;
> bool has_vld_pa_rng;
> bool reset_axi;
> + u32 inv_sel_reg;
> unsigned char larbid_remap[MTK_LARB_NR_MAX];
> };
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Chao Hao <chao.hao@mediatek.com>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
wsd_upstream@mediatek.com, Joerg Roedel <joro@8bytes.org>,
linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
Jun Yan <jun.yan@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 4/7] iommu/mediatek: Move inv_sel_reg into the plat_data
Date: Mon, 25 May 2020 14:22:23 +0800 [thread overview]
Message-ID: <1590387743.13912.11.camel@mhfsdcap03> (raw)
In-Reply-To: <20200509083654.5178-5-chao.hao@mediatek.com>
On Sat, 2020-05-09 at 16:36 +0800, Chao Hao wrote:
> For mt6779, MMU_INVLDT_SEL register's offset is changed from
At this patch, the register is still called by "MMU_INV_SEL".
> 0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to
> use it.
> In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it
> before mt6779.
>
> Signed-off-by: Chao Hao <chao.hao@mediatek.com>
> ---
> drivers/iommu/mtk_iommu.c | 9 ++++++---
> drivers/iommu/mtk_iommu.h | 1 +
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 9ede327a418d..d73de987f8be 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -37,7 +37,7 @@
> #define REG_MMU_INVLD_START_A 0x024
> #define REG_MMU_INVLD_END_A 0x028
>
> -#define REG_MMU_INV_SEL 0x038
> +#define REG_MMU_INV_SEL_GEN1 0x038
> #define F_INVLD_EN0 BIT(0)
> #define F_INVLD_EN1 BIT(1)
>
> @@ -167,7 +167,7 @@ static void mtk_iommu_tlb_flush_all(void *cookie)
>
> for_each_m4u(data) {
> writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
> - data->base + REG_MMU_INV_SEL);
> + data->base + data->plat_data->inv_sel_reg);
> writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
> wmb(); /* Make sure the tlb flush all done */
> }
> @@ -184,7 +184,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
> for_each_m4u(data) {
> spin_lock_irqsave(&data->tlb_lock, flags);
> writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
> - data->base + REG_MMU_INV_SEL);
> + data->base + data->plat_data->inv_sel_reg);
>
> writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
> writel_relaxed(iova + size - 1,
> @@ -784,6 +784,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
> .has_4gb_mode = true,
> .has_bclk = true,
> .has_vld_pa_rng = true,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
nitpick: align '=' with the next line.
> .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
> };
>
> @@ -792,12 +793,14 @@ static const struct mtk_iommu_plat_data mt8173_data = {
> .has_4gb_mode = true,
> .has_bclk = true,
> .reset_axi = true,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
align '='
> .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
> };
>
> static const struct mtk_iommu_plat_data mt8183_data = {
> .m4u_plat = M4U_MT8183,
> .reset_axi = true,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},
> };
>
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index d711ac630037..afd7a2de5c1e 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -43,6 +43,7 @@ struct mtk_iommu_plat_data {
> bool has_misc_ctrl;
> bool has_vld_pa_rng;
> bool reset_axi;
> + u32 inv_sel_reg;
> unsigned char larbid_remap[MTK_LARB_NR_MAX];
> };
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-05-25 6:24 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-09 8:36 [PATCH v3 00/07] MT6779 IOMMU SUPPORT Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` [PATCH v3 1/7] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` [PATCH v3 2/7] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-25 6:11 ` Yong Wu
2020-05-25 6:11 ` Yong Wu
2020-05-25 6:11 ` Yong Wu
2020-05-25 6:11 ` Yong Wu
2020-05-09 8:36 ` [PATCH v3 3/7] iommu/mediatek: Disable STANDARD_AXI_MODE in MISC_CTRL Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-25 6:14 ` Yong Wu
2020-05-25 6:14 ` Yong Wu
2020-05-25 6:14 ` Yong Wu
2020-05-25 6:14 ` Yong Wu
2020-06-16 6:10 ` chao hao
2020-06-16 6:10 ` chao hao
2020-06-16 6:10 ` chao hao
2020-06-16 6:10 ` chao hao
2020-05-09 8:36 ` [PATCH v3 4/7] iommu/mediatek: Move inv_sel_reg into the plat_data Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-25 6:22 ` Yong Wu [this message]
2020-05-25 6:22 ` Yong Wu
2020-05-25 6:22 ` Yong Wu
2020-05-25 6:22 ` Yong Wu
2020-05-09 8:36 ` [PATCH v3 5/7] iommu/mediatek: Add sub_comm id in translation fault Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-25 6:31 ` Yong Wu
2020-05-25 6:31 ` Yong Wu
2020-05-25 6:31 ` Yong Wu
2020-05-25 6:31 ` Yong Wu
2020-05-09 8:36 ` [PATCH v3 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779 Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` [PATCH v3 7/7] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-09 8:36 ` Chao Hao
2020-05-25 6:54 ` Yong Wu
2020-05-25 6:54 ` Yong Wu
2020-05-25 6:54 ` Yong Wu
2020-05-25 6:54 ` Yong Wu
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