From: guoren@kernel.org To: guoren@kernel.org, anup.patel@wdc.com, palmerdabbelt@google.com, drew@beagleboard.org, hch@lst.de, wefu@redhat.com, lazyparser@gmail.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-sunxi@lists.linux.dev, Guo Ren <guoren@linux.alibaba.com> Subject: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support Date: Wed, 19 May 2021 05:04:13 +0000 [thread overview] Message-ID: <1621400656-25678-1-git-send-email-guoren@kernel.org> (raw) From: Guo Ren <guoren@linux.alibaba.com> The RISC-V ISA doesn't yet specify how to query or modify PMAs, so let vendors define the custom properties of memory regions in PTE. This patchset helps SOC vendors to support their own custom interconnect coherent solution with PTE attributes. For example, allwinner D1[1] uses T-HEAD C906 as main processor, C906 has two modes in MMU: - Compatible mode, the same as the definitions in spec. - Enhanced mode, add custom DMA_COHERENT attribute bits in PTE which not mentioned in spec. Allwinner D1 needs the enhanced mode to support the DMA type device with non-coherent interconnect in its SOC. C906 uses BITS(63 - 59) as custom attribute bits in PTE. Here is the config example for Allwinner D1: CONFIG_RISCV_DMA_COHERENT=y CONFIG_RISCV_PAGE_DMA_MASK=0xf800000000000000 CONFIG_RISCV_PAGE_CACHE=0x7000000000000000 CONFIG_RISCV_PAGE_DMA_NONCACHE=0x8000000000000000 Link: https://linux-sunxi.org/D1 [1] Guo Ren (3): riscv: pgtable.h: Fixup _PAGE_CHG_MASK usage riscv: Add DMA_COHERENT for custom PTE attributes riscv: Add SYNC_DMA_FOR_CPU/DEVICE for DMA_COHERENT arch/riscv/Kconfig | 31 ++++++++++++++++++++++++++ arch/riscv/include/asm/pgtable-64.h | 8 ++++--- arch/riscv/include/asm/pgtable-bits.h | 13 ++++++++++- arch/riscv/include/asm/pgtable.h | 26 +++++++++++++++++----- arch/riscv/include/asm/sbi.h | 16 ++++++++++++++ arch/riscv/kernel/sbi.c | 19 ++++++++++++++++ arch/riscv/mm/Makefile | 4 ++++ arch/riscv/mm/dma-mapping.c | 41 +++++++++++++++++++++++++++++++++++ 8 files changed, 148 insertions(+), 10 deletions(-) create mode 100644 arch/riscv/mm/dma-mapping.c -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org To: guoren@kernel.org, anup.patel@wdc.com, palmerdabbelt@google.com, drew@beagleboard.org, hch@lst.de, wefu@redhat.com, lazyparser@gmail.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-sunxi@lists.linux.dev, Guo Ren <guoren@linux.alibaba.com> Subject: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support Date: Wed, 19 May 2021 05:04:13 +0000 [thread overview] Message-ID: <1621400656-25678-1-git-send-email-guoren@kernel.org> (raw) From: Guo Ren <guoren@linux.alibaba.com> The RISC-V ISA doesn't yet specify how to query or modify PMAs, so let vendors define the custom properties of memory regions in PTE. This patchset helps SOC vendors to support their own custom interconnect coherent solution with PTE attributes. For example, allwinner D1[1] uses T-HEAD C906 as main processor, C906 has two modes in MMU: - Compatible mode, the same as the definitions in spec. - Enhanced mode, add custom DMA_COHERENT attribute bits in PTE which not mentioned in spec. Allwinner D1 needs the enhanced mode to support the DMA type device with non-coherent interconnect in its SOC. C906 uses BITS(63 - 59) as custom attribute bits in PTE. Here is the config example for Allwinner D1: CONFIG_RISCV_DMA_COHERENT=y CONFIG_RISCV_PAGE_DMA_MASK=0xf800000000000000 CONFIG_RISCV_PAGE_CACHE=0x7000000000000000 CONFIG_RISCV_PAGE_DMA_NONCACHE=0x8000000000000000 Link: https://linux-sunxi.org/D1 [1] Guo Ren (3): riscv: pgtable.h: Fixup _PAGE_CHG_MASK usage riscv: Add DMA_COHERENT for custom PTE attributes riscv: Add SYNC_DMA_FOR_CPU/DEVICE for DMA_COHERENT arch/riscv/Kconfig | 31 ++++++++++++++++++++++++++ arch/riscv/include/asm/pgtable-64.h | 8 ++++--- arch/riscv/include/asm/pgtable-bits.h | 13 ++++++++++- arch/riscv/include/asm/pgtable.h | 26 +++++++++++++++++----- arch/riscv/include/asm/sbi.h | 16 ++++++++++++++ arch/riscv/kernel/sbi.c | 19 ++++++++++++++++ arch/riscv/mm/Makefile | 4 ++++ arch/riscv/mm/dma-mapping.c | 41 +++++++++++++++++++++++++++++++++++ 8 files changed, 148 insertions(+), 10 deletions(-) create mode 100644 arch/riscv/mm/dma-mapping.c -- 2.7.4 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2021-05-19 5:05 UTC|newest] Thread overview: 124+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-19 5:04 guoren [this message] 2021-05-19 5:04 ` [PATCH RFC 0/3] riscv: Add DMA_COHERENT support guoren 2021-05-19 5:04 ` [PATCH RFC 1/3] riscv: pgtable.h: Fixup _PAGE_CHG_MASK usage guoren 2021-05-19 5:04 ` guoren 2021-05-19 5:04 ` [PATCH RFC 2/3] riscv: Add DMA_COHERENT for custom PTE attributes guoren 2021-05-19 5:04 ` guoren 2021-05-19 5:04 ` [PATCH RFC 3/3] riscv: Add SYNC_DMA_FOR_CPU/DEVICE for DMA_COHERENT guoren 2021-05-19 5:04 ` guoren 2021-05-19 6:32 ` Guo Ren 2021-05-19 6:32 ` Guo Ren 2021-05-19 6:32 ` Guo Ren 2021-05-19 5:20 ` [PATCH RFC 0/3] riscv: Add DMA_COHERENT support Christoph Hellwig 2021-05-19 5:20 ` Christoph Hellwig 2021-05-19 5:48 ` Guo Ren 2021-05-19 5:48 ` Guo Ren 2021-05-19 5:48 ` Guo Ren 2021-05-19 5:55 ` Christoph Hellwig 2021-05-19 5:55 ` Christoph Hellwig 2021-05-19 6:09 ` Guo Ren 2021-05-19 6:09 ` Guo Ren 2021-05-19 6:09 ` Guo Ren 2021-05-19 6:44 ` Drew Fustini 2021-05-19 6:44 ` Drew Fustini 2021-05-19 6:53 ` Christoph Hellwig 2021-05-19 6:53 ` Christoph Hellwig 2021-05-20 1:45 ` Guo Ren 2021-05-20 1:45 ` Guo Ren 2021-05-20 1:45 ` Guo Ren 2021-05-20 5:48 ` Christoph Hellwig 2021-05-20 5:48 ` Christoph Hellwig 2021-06-06 18:14 ` Nick Kossifidis 2021-06-06 18:14 ` Nick Kossifidis 2021-06-07 0:04 ` Guo Ren 2021-06-07 0:04 ` Guo Ren 2021-06-07 2:16 ` Nick Kossifidis 2021-06-07 2:16 ` Nick Kossifidis 2021-06-07 3:19 ` Guo Ren 2021-06-07 3:19 ` Guo Ren 2021-06-07 6:27 ` Christoph Hellwig 2021-06-07 6:27 ` Christoph Hellwig 2021-06-07 6:41 ` Guo Ren 2021-06-07 6:41 ` Guo Ren 2021-06-07 6:51 ` Christoph Hellwig 2021-06-07 6:51 ` Christoph Hellwig 2021-06-07 7:46 ` Guo Ren 2021-06-07 7:46 ` Guo Ren 2021-06-08 15:00 ` David Laight 2021-06-08 15:00 ` David Laight 2021-06-08 15:32 ` 'Christoph Hellwig' 2021-06-08 15:32 ` 'Christoph Hellwig' 2021-06-08 16:11 ` David Laight 2021-06-08 16:11 ` David Laight 2021-06-07 8:35 ` Nick Kossifidis 2021-06-07 8:35 ` Nick Kossifidis 2021-06-09 3:28 ` Guo Ren 2021-06-09 3:28 ` Guo Ren 2021-06-09 6:05 ` Jisheng Zhang 2021-06-09 6:05 ` Jisheng Zhang 2021-06-09 9:45 ` Nick Kossifidis 2021-06-09 9:45 ` Nick Kossifidis 2021-06-09 12:43 ` Guo Ren 2021-06-09 12:43 ` Guo Ren 2021-05-19 6:05 ` Guo Ren 2021-05-19 6:05 ` Guo Ren 2021-05-19 6:05 ` Guo Ren 2021-05-19 6:06 ` Christoph Hellwig 2021-05-19 6:06 ` Christoph Hellwig 2021-05-19 6:11 ` Guo Ren 2021-05-19 6:11 ` Guo Ren 2021-05-19 6:11 ` Guo Ren 2021-05-19 6:54 ` Drew Fustini 2021-05-19 6:54 ` Drew Fustini 2021-05-19 6:56 ` Christoph Hellwig 2021-05-19 6:56 ` Christoph Hellwig 2021-05-19 7:14 ` Anup Patel 2021-05-19 7:14 ` Anup Patel 2021-05-19 8:25 ` Damien Le Moal 2021-05-19 8:25 ` Damien Le Moal 2021-05-20 1:47 ` Guo Ren 2021-05-20 1:47 ` Guo Ren 2021-05-20 1:59 ` Guo Ren 2021-05-20 1:59 ` Guo Ren 2021-05-22 0:36 ` Guo Ren 2021-05-22 0:36 ` Guo Ren 2021-05-30 0:30 ` Palmer Dabbelt 2021-05-30 0:30 ` Palmer Dabbelt 2021-06-03 4:13 ` Palmer Dabbelt 2021-06-03 4:13 ` Palmer Dabbelt 2021-06-03 6:00 ` Anup Patel 2021-06-03 6:00 ` Anup Patel 2021-06-03 15:39 ` Palmer Dabbelt 2021-06-03 15:39 ` Palmer Dabbelt 2021-06-04 9:02 ` David Laight 2021-06-04 9:02 ` David Laight 2021-06-04 9:53 ` Arnd Bergmann 2021-06-04 9:53 ` Arnd Bergmann 2021-06-04 9:53 ` Arnd Bergmann 2021-06-04 14:47 ` Guo Ren 2021-06-04 14:47 ` Guo Ren 2021-06-04 16:12 ` Palmer Dabbelt 2021-06-04 16:12 ` Palmer Dabbelt 2021-06-04 21:26 ` Arnd Bergmann 2021-06-04 21:26 ` Arnd Bergmann 2021-06-04 21:26 ` Arnd Bergmann 2021-06-04 22:10 ` Palmer Dabbelt 2021-06-04 22:10 ` Palmer Dabbelt 2021-06-08 12:26 ` Guo Ren 2021-06-08 12:26 ` Guo Ren 2021-06-06 17:11 ` Guo Ren 2021-06-06 17:11 ` Guo Ren 2021-06-06 17:11 ` Guo Ren 2021-06-07 3:38 ` Anup Patel 2021-06-07 3:38 ` Anup Patel 2021-06-07 4:22 ` Guo Ren 2021-06-07 4:22 ` Guo Ren 2021-06-07 4:22 ` Guo Ren 2021-06-07 4:47 ` Anup Patel 2021-06-07 4:47 ` Anup Patel 2021-06-07 5:08 ` Guo Ren 2021-06-07 5:08 ` Guo Ren 2021-06-07 5:08 ` Guo Ren 2021-06-07 5:13 ` Guo Ren 2021-06-07 5:13 ` Guo Ren 2021-06-07 5:13 ` Guo Ren
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