From: CK Hu <ck.hu@mediatek.com>
To: jason-jh.lin <jason-jh.lin@mediatek.com>
Cc: <chunkuang.hu@kernel.org>, <matthias.bgg@gmail.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
<fshao@google.com>, <nancy.lin@mediatek.com>,
<singo.chang@mediatek.com>
Subject: Re: [PATCH v1 06/17] soc: mediatek: add mtk-mutex support for mt8195
Date: Wed, 7 Jul 2021 12:52:46 +0800 [thread overview]
Message-ID: <1625633566.7824.8.camel@mtksdaap41> (raw)
In-Reply-To: <20210707041249.29816-7-jason-jh.lin@mediatek.com>
Hi, Jason:
On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195.
Separate DRM part and SoC part into different patch.
Regards,
CK
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
> drivers/soc/mediatek/mtk-mutex.c | 105 +++++++++++++++++++++++--
> 2 files changed, 102 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 9074ce32912c..5b7ead493487 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -470,6 +470,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8183-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> + { .compatible = "mediatek,mt8195-disp-mutex",
> + .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2701-disp-pwm",
> .data = (void *)MTK_DISP_BLS },
> { .compatible = "mediatek,mt8173-disp-pwm",
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 2e4bcc300576..080bdabfb024 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -17,6 +17,9 @@
> #define MT8183_MUTEX0_MOD0 0x30
> #define MT8183_MUTEX0_SOF0 0x2c
>
> +#define MT8195_DISP_MUTEX0_MOD0 0x30
> +#define MT8195_DISP_MUTEX0_SOF 0x2c
> +
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> @@ -67,6 +70,36 @@
> #define MT8173_MUTEX_MOD_DISP_PWM1 24
> #define MT8173_MUTEX_MOD_DISP_OD 25
>
> +#define MT8195_MUTEX_MOD_DISP_OVL0 0
> +#define MT8195_MUTEX_MOD_DISP_WDMA0 1
> +#define MT8195_MUTEX_MOD_DISP_RDMA0 2
> +#define MT8195_MUTEX_MOD_DISP_COLOR0 3
> +#define MT8195_MUTEX_MOD_DISP_CCORR0 4
> +#define MT8195_MUTEX_MOD_DISP_AAL0 5
> +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
> +#define MT8195_MUTEX_MOD_DISP_DITHER0 7
> +#define MT8195_MUTEX_MOD_DISP_DSI0 8
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
> +#define MT8195_MUTEX_MOD_DISP_OVL1 10
> +#define MT8195_MUTEX_MOD_DISP_WDMA1 11
> +#define MT8195_MUTEX_MOD_DISP_RDMA1 12
> +#define MT8195_MUTEX_MOD_DISP_COLOR1 13
> +#define MT8195_MUTEX_MOD_DISP_CCORR1 14
> +#define MT8195_MUTEX_MOD_DISP_AAL1 15
> +#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
> +#define MT8195_MUTEX_MOD_DISP_DITHER1 17
> +#define MT8195_MUTEX_MOD_DISP_DSI1 18
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
> +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
> +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
> +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
> +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
> +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
> +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
> +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
> +#define MT8195_MUTEX_MOD_DISP_PWM0 27
> +#define MT8195_MUTEX_MOD_DISP_PWM1 28
> +
> #define MT2712_MUTEX_MOD_DISP_PWM2 10
> #define MT2712_MUTEX_MOD_DISP_OVL0 11
> #define MT2712_MUTEX_MOD_DISP_OVL1 12
> @@ -101,11 +134,36 @@
> #define MT2712_MUTEX_SOF_DSI3 6
> #define MT8167_MUTEX_SOF_DPI0 2
> #define MT8167_MUTEX_SOF_DPI1 3
> +
> #define MT8183_MUTEX_SOF_DSI0 1
> #define MT8183_MUTEX_SOF_DPI0 2
>
> -#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
> -#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
> +#define MT8183_MUTEX_EOF_CONVERT(sof) ((sof) << 6)
> +#define MT8183_MUTEX_EOF_DSI0 \
> + MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DSI0)
> +#define MT8183_MUTEX_EOF_DPI0 \
> + MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DPI0)
> +
> +#define MT8195_MUTEX_SOF_DSI0 1
> +#define MT8195_MUTEX_SOF_DSI1 2
> +#define MT8195_MUTEX_SOF_DP_INTF0 3
> +#define MT8195_MUTEX_SOF_DP_INTF1 4
> +#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
> +#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
> +
> +#define MT8195_MUTEX_EOF_CONVERT(sof) ((sof) << 7)
> +#define MT8195_MUTEX_EOF_DSI0 \
> + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI0)
> +#define MT8195_MUTEX_EOF_DSI1 \
> + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI1)
> +#define MT8195_MUTEX_EOF_DP_INTF0 \
> + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF0)
> +#define MT8195_MUTEX_EOF_DP_INTF1 \
> + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF1)
> +#define MT8195_MUTEX_EOF_DPI0 \
> + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI0)
> +#define MT8195_MUTEX_EOF_DPI1 \
> + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI1)
>
> struct mtk_mutex {
> int id;
> @@ -120,6 +178,9 @@ enum mtk_mutex_sof_id {
> MUTEX_SOF_DPI1,
> MUTEX_SOF_DSI2,
> MUTEX_SOF_DSI3,
> + MUTEX_SOF_DP_INTF0,
> + MUTEX_SOF_DP_INTF1,
> + DDP_MUTEX_SOF_MAX,
> };
>
> struct mtk_mutex_data {
> @@ -214,7 +275,20 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> };
>
> -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
> + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
> +};
> +
> +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
> @@ -224,7 +298,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
> };
>
> -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
> @@ -232,12 +306,24 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> };
>
> /* Add EOF setting so overlay hardware can receive frame done irq */
> -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> };
>
> +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
> + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
> + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
> + [MUTEX_SOF_DP_INTF0] =
> + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
> + [MUTEX_SOF_DP_INTF1] =
> + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -275,6 +361,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> .no_clk = true,
> };
>
> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> + .mutex_mod = mt8195_mutex_mod,
> + .mutex_sof = mt8195_mutex_sof,
> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -507,6 +600,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
> .data = &mt8173_mutex_driver_data},
> { .compatible = "mediatek,mt8183-disp-mutex",
> .data = &mt8183_mutex_driver_data},
> + { .compatible = "mediatek,mt8195-disp-mutex",
> + .data = &mt8195_mutex_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
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WARNING: multiple messages have this Message-ID (diff)
From: CK Hu <ck.hu@mediatek.com>
To: jason-jh.lin <jason-jh.lin@mediatek.com>
Cc: <chunkuang.hu@kernel.org>, <matthias.bgg@gmail.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
<fshao@google.com>, <nancy.lin@mediatek.com>,
<singo.chang@mediatek.com>
Subject: Re: [PATCH v1 06/17] soc: mediatek: add mtk-mutex support for mt8195
Date: Wed, 7 Jul 2021 12:52:46 +0800 [thread overview]
Message-ID: <1625633566.7824.8.camel@mtksdaap41> (raw)
In-Reply-To: <20210707041249.29816-7-jason-jh.lin@mediatek.com>
Hi, Jason:
On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195.
Separate DRM part and SoC part into different patch.
Regards,
CK
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
> drivers/soc/mediatek/mtk-mutex.c | 105 +++++++++++++++++++++++--
> 2 files changed, 102 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 9074ce32912c..5b7ead493487 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -470,6 +470,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8183-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> + { .compatible = "mediatek,mt8195-disp-mutex",
> + .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2701-disp-pwm",
> .data = (void *)MTK_DISP_BLS },
> { .compatible = "mediatek,mt8173-disp-pwm",
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 2e4bcc300576..080bdabfb024 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -17,6 +17,9 @@
> #define MT8183_MUTEX0_MOD0 0x30
> #define MT8183_MUTEX0_SOF0 0x2c
>
> +#define MT8195_DISP_MUTEX0_MOD0 0x30
> +#define MT8195_DISP_MUTEX0_SOF 0x2c
> +
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> @@ -67,6 +70,36 @@
> #define MT8173_MUTEX_MOD_DISP_PWM1 24
> #define MT8173_MUTEX_MOD_DISP_OD 25
>
> +#define MT8195_MUTEX_MOD_DISP_OVL0 0
> +#define MT8195_MUTEX_MOD_DISP_WDMA0 1
> +#define MT8195_MUTEX_MOD_DISP_RDMA0 2
> +#define MT8195_MUTEX_MOD_DISP_COLOR0 3
> +#define MT8195_MUTEX_MOD_DISP_CCORR0 4
> +#define MT8195_MUTEX_MOD_DISP_AAL0 5
> +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
> +#define MT8195_MUTEX_MOD_DISP_DITHER0 7
> +#define MT8195_MUTEX_MOD_DISP_DSI0 8
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
> +#define MT8195_MUTEX_MOD_DISP_OVL1 10
> +#define MT8195_MUTEX_MOD_DISP_WDMA1 11
> +#define MT8195_MUTEX_MOD_DISP_RDMA1 12
> +#define MT8195_MUTEX_MOD_DISP_COLOR1 13
> +#define MT8195_MUTEX_MOD_DISP_CCORR1 14
> +#define MT8195_MUTEX_MOD_DISP_AAL1 15
> +#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
> +#define MT8195_MUTEX_MOD_DISP_DITHER1 17
> +#define MT8195_MUTEX_MOD_DISP_DSI1 18
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
> +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
> +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
> +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
> +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
> +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
> +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
> +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
> +#define MT8195_MUTEX_MOD_DISP_PWM0 27
> +#define MT8195_MUTEX_MOD_DISP_PWM1 28
> +
> #define MT2712_MUTEX_MOD_DISP_PWM2 10
> #define MT2712_MUTEX_MOD_DISP_OVL0 11
> #define MT2712_MUTEX_MOD_DISP_OVL1 12
> @@ -101,11 +134,36 @@
> #define MT2712_MUTEX_SOF_DSI3 6
> #define MT8167_MUTEX_SOF_DPI0 2
> #define MT8167_MUTEX_SOF_DPI1 3
> +
> #define MT8183_MUTEX_SOF_DSI0 1
> #define MT8183_MUTEX_SOF_DPI0 2
>
> -#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
> -#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
> +#define MT8183_MUTEX_EOF_CONVERT(sof) ((sof) << 6)
> +#define MT8183_MUTEX_EOF_DSI0 \
> + MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DSI0)
> +#define MT8183_MUTEX_EOF_DPI0 \
> + MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DPI0)
> +
> +#define MT8195_MUTEX_SOF_DSI0 1
> +#define MT8195_MUTEX_SOF_DSI1 2
> +#define MT8195_MUTEX_SOF_DP_INTF0 3
> +#define MT8195_MUTEX_SOF_DP_INTF1 4
> +#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
> +#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
> +
> +#define MT8195_MUTEX_EOF_CONVERT(sof) ((sof) << 7)
> +#define MT8195_MUTEX_EOF_DSI0 \
> + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI0)
> +#define MT8195_MUTEX_EOF_DSI1 \
> + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI1)
> +#define MT8195_MUTEX_EOF_DP_INTF0 \
> + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF0)
> +#define MT8195_MUTEX_EOF_DP_INTF1 \
> + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF1)
> +#define MT8195_MUTEX_EOF_DPI0 \
> + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI0)
> +#define MT8195_MUTEX_EOF_DPI1 \
> + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI1)
>
> struct mtk_mutex {
> int id;
> @@ -120,6 +178,9 @@ enum mtk_mutex_sof_id {
> MUTEX_SOF_DPI1,
> MUTEX_SOF_DSI2,
> MUTEX_SOF_DSI3,
> + MUTEX_SOF_DP_INTF0,
> + MUTEX_SOF_DP_INTF1,
> + DDP_MUTEX_SOF_MAX,
> };
>
> struct mtk_mutex_data {
> @@ -214,7 +275,20 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> };
>
> -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
> + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
> +};
> +
> +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
> @@ -224,7 +298,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
> };
>
> -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
> @@ -232,12 +306,24 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> };
>
> /* Add EOF setting so overlay hardware can receive frame done irq */
> -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> };
>
> +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
> + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
> + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
> + [MUTEX_SOF_DP_INTF0] =
> + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
> + [MUTEX_SOF_DP_INTF1] =
> + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -275,6 +361,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> .no_clk = true,
> };
>
> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> + .mutex_mod = mt8195_mutex_mod,
> + .mutex_sof = mt8195_mutex_sof,
> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -507,6 +600,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
> .data = &mt8173_mutex_driver_data},
> { .compatible = "mediatek,mt8183-disp-mutex",
> .data = &mt8183_mutex_driver_data},
> + { .compatible = "mediatek,mt8195-disp-mutex",
> + .data = &mt8195_mutex_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
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next prev parent reply other threads:[~2021-07-07 5:03 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-07 4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 4:12 ` [PATCH v1 01/17] dt-bindings: mediatek: add definition for mt8195 display jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 4:33 ` CK Hu
2021-07-07 4:33 ` CK Hu
2021-07-10 6:57 ` Jason-JH Lin
2021-07-10 6:57 ` Jason-JH Lin
2021-07-07 4:12 ` [PATCH v1 02/17] dt-bindings: arm: mediatek: add definition for mt8195 mmsys jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 4:12 ` [PATCH v1 03/17] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 4:12 ` [PATCH v1 04/17] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 4:44 ` CK Hu
2021-07-07 4:44 ` CK Hu
2021-07-10 6:58 ` Jason-JH Lin
2021-07-10 6:58 ` Jason-JH Lin
2021-07-07 4:12 ` [PATCH v1 05/17] drm/mediatek: add mediatek-drm of vdosys0 support for MT8195 jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 4:48 ` CK Hu
2021-07-07 4:48 ` CK Hu
2021-07-10 6:59 ` Jason-JH Lin
2021-07-10 6:59 ` Jason-JH Lin
2021-07-10 6:59 ` Jason-JH Lin
2021-07-07 4:12 ` [PATCH v1 06/17] soc: mediatek: add mtk-mutex support for mt8195 jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 4:52 ` CK Hu [this message]
2021-07-07 4:52 ` CK Hu
2021-07-10 7:01 ` Jason-JH Lin
2021-07-10 7:01 ` Jason-JH Lin
2021-07-07 4:12 ` [PATCH v1 07/17] drm/mediatek: add OVL support for MT8195 jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 5:03 ` CK Hu
2021-07-07 5:03 ` CK Hu
2021-07-10 7:05 ` Jason-JH Lin
2021-07-10 7:05 ` Jason-JH Lin
2021-07-10 7:05 ` Jason-JH Lin
2021-07-07 4:12 ` [PATCH v1 08/17] drm/mediatek: Add component_del in OVL remove function jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 5:12 ` CK Hu
2021-07-07 5:12 ` CK Hu
2021-07-10 7:06 ` Jason-JH Lin
2021-07-10 7:06 ` Jason-JH Lin
2021-07-10 7:06 ` Jason-JH Lin
2021-07-07 4:12 ` [PATCH v1 09/17] drm/mediatek: add OVL support multi-layer jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 5:43 ` CK Hu
2021-07-07 5:43 ` CK Hu
2021-07-10 7:17 ` Jason-JH Lin
2021-07-10 7:17 ` Jason-JH Lin
2021-07-10 7:17 ` Jason-JH Lin
2021-07-07 4:12 ` [PATCH v1 10/17] drm/mediatek: add RDMA support for MT8195 jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 4:12 ` [PATCH v1 11/17] drm/mediatek: add COLOR " jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 6:01 ` CK Hu
2021-07-07 6:01 ` CK Hu
2021-07-10 7:21 ` Jason-JH Lin
2021-07-10 7:21 ` Jason-JH Lin
2021-07-10 7:21 ` Jason-JH Lin
2021-07-07 4:12 ` [PATCH v1 12/17] drm/mediatek: add CCORR " jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 6:02 ` CK Hu
2021-07-07 6:02 ` CK Hu
2021-07-10 7:22 ` Jason-JH Lin
2021-07-10 7:22 ` Jason-JH Lin
2021-07-10 7:22 ` Jason-JH Lin
2021-07-07 4:12 ` [PATCH v1 13/17] drm/mediatek: Add AAL " jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 6:14 ` CK Hu
2021-07-07 6:14 ` CK Hu
2021-07-10 7:35 ` Jason-JH Lin
2021-07-10 7:35 ` Jason-JH Lin
2021-07-07 4:12 ` [PATCH v1 14/17] drm/mediatek: add GAMMA " jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 4:12 ` [PATCH v1 15/17] drm/mediatek: add DITHER " jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 4:12 ` [PATCH v1 16/17] drm/mediatek: add MERGE " jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 7:02 ` CK Hu
2021-07-07 7:02 ` CK Hu
2021-07-10 7:52 ` Jason-JH Lin
2021-07-10 7:52 ` Jason-JH Lin
2021-07-07 4:12 ` [PATCH v1 17/17] drm/mediatek: add DSC " jason-jh.lin
2021-07-07 4:12 ` jason-jh.lin
2021-07-07 7:35 ` CK Hu
2021-07-07 7:35 ` CK Hu
2021-07-10 7:55 ` Jason-JH Lin
2021-07-10 7:55 ` Jason-JH Lin
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