From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mm@kvack.org
Cc: akpm@linux-foundation.org, suzuki.poulose@arm.com,
mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com,
maz@kernel.org, james.morse@arm.com, steven.price@arm.com,
Anshuman Khandual <anshuman.khandual@arm.com>
Subject: [RFC 09/10] arm64/mm: Add FEAT_LPA2 specific fallback (48 bits PA) when not implemented
Date: Wed, 14 Jul 2021 07:51:30 +0530 [thread overview]
Message-ID: <1626229291-6569-10-git-send-email-anshuman.khandual@arm.com> (raw)
In-Reply-To: <1626229291-6569-1-git-send-email-anshuman.khandual@arm.com>
CONFIG_ARM64_PA_BITS_52 build kernels need to fallback for 48 bits PA range
encodings when FEAT_LPA2 is not implemented i.e TCR_EL1.DS could not be set
. Hence modify applicable PTE and TTBR encoding helpers to accommodate the
scenario via 'arm64_lpa2_enabled'.
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/include/asm/assembler.h | 13 +++++++++++++
arch/arm64/include/asm/pgtable-hwdef.h | 2 ++
arch/arm64/include/asm/pgtable.h | 12 ++++++++++--
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 0492543..844e9a0 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -615,6 +615,10 @@ alternative_endif
orr \pte, \phys, \phys, lsr #36
and \pte, \pte, #PTE_ADDR_MASK
#elif defined(CONFIG_ARM64_PA_BITS_52_LPA2)
+ ldr_l \tmp, arm64_lpa2_enabled
+ cmp \tmp, #1
+ b.ne .Lskip_lpa2\@
+
orr \pte, \phys, \phys, lsr #42
/*
@@ -625,6 +629,9 @@ alternative_endif
mov \tmp, #PTE_ADDR_LOW
orr \tmp, \tmp, #PTE_ADDR_HIGH
and \pte, \pte, \tmp
+
+.Lskip_lpa2\@:
+ mov \pte, \phys
#else /* !CONFIG_ARM64_PA_BITS_52_LPA */
mov \pte, \phys
#endif /* CONFIG_ARM64_PA_BITS_52_LPA */
@@ -636,9 +643,15 @@ alternative_endif
bfxil \phys, \pte, #PAGE_SHIFT, #(48 - PAGE_SHIFT)
lsl \phys, \phys, #PAGE_SHIFT
#elif defined(CONFIG_ARM64_PA_BITS_52_LPA2)
+ ldr_l \phys, arm64_lpa2_enabled
+ cmp \phys, #1
+ b.ne .Lskip_lpa2\@
+
ubfiz \phys, \pte, #(52 - PAGE_SHIFT - 10), #10
bfxil \phys, \pte, #PAGE_SHIFT, #(50 - PAGE_SHIFT)
lsl \phys, \phys, #PAGE_SHIFT
+.Lskip_lpa2\@:
+ and \phys, \pte, #PTE_ADDR_MASK_48
#else /* !CONFIG_ARM64_PA_BITS_52_LPA */
and \phys, \pte, #PTE_ADDR_MASK
#endif /* CONFIG_ARM64_PA_BITS_52_LPA */
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 8a3b75e..b98b764 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -176,6 +176,8 @@
#define PTE_ADDR_MASK PTE_ADDR_LOW
#endif /* CONFIG_ARM64_PA_BITS_52_LPA */
+#define PTE_ADDR_MASK_48 (((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
+
/*
* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
*/
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 5e7e402..97b3cd2 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -71,9 +71,17 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36))
#define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK)
#elif defined(CONFIG_ARM64_PA_BITS_52_LPA2)
-#define __pte_to_phys(pte) \
+#define __pte_to_phys_52(pte) \
((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 42))
-#define __phys_to_pte_val(phys) (((phys) | ((phys) >> 42)) & PTE_ADDR_MASK)
+#define __phys_to_pte_val_52(phys) (((phys) | ((phys) >> 42)) & PTE_ADDR_MASK)
+
+#define __pte_to_phys_48(pte) (pte_val(pte) & PTE_ADDR_MASK_48)
+#define __phys_to_pte_val_48(phys) (phys)
+
+#define __pte_to_phys(pte) \
+ (arm64_lpa2_enabled ? __pte_to_phys_52(pte) : __pte_to_phys_48(pte))
+#define __phys_to_pte_val(phys) \
+ (arm64_lpa2_enabled ? __phys_to_pte_val_52(phys) : __phys_to_pte_val_48(phys))
#else /* !CONFIG_ARM64_PA_BITS_52_LPA */
#define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
#define __phys_to_pte_val(phys) (phys)
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mm@kvack.org
Cc: akpm@linux-foundation.org, suzuki.poulose@arm.com,
mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com,
maz@kernel.org, james.morse@arm.com, steven.price@arm.com,
Anshuman Khandual <anshuman.khandual@arm.com>
Subject: [RFC 09/10] arm64/mm: Add FEAT_LPA2 specific fallback (48 bits PA) when not implemented
Date: Wed, 14 Jul 2021 07:51:30 +0530 [thread overview]
Message-ID: <1626229291-6569-10-git-send-email-anshuman.khandual@arm.com> (raw)
In-Reply-To: <1626229291-6569-1-git-send-email-anshuman.khandual@arm.com>
CONFIG_ARM64_PA_BITS_52 build kernels need to fallback for 48 bits PA range
encodings when FEAT_LPA2 is not implemented i.e TCR_EL1.DS could not be set
. Hence modify applicable PTE and TTBR encoding helpers to accommodate the
scenario via 'arm64_lpa2_enabled'.
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/include/asm/assembler.h | 13 +++++++++++++
arch/arm64/include/asm/pgtable-hwdef.h | 2 ++
arch/arm64/include/asm/pgtable.h | 12 ++++++++++--
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 0492543..844e9a0 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -615,6 +615,10 @@ alternative_endif
orr \pte, \phys, \phys, lsr #36
and \pte, \pte, #PTE_ADDR_MASK
#elif defined(CONFIG_ARM64_PA_BITS_52_LPA2)
+ ldr_l \tmp, arm64_lpa2_enabled
+ cmp \tmp, #1
+ b.ne .Lskip_lpa2\@
+
orr \pte, \phys, \phys, lsr #42
/*
@@ -625,6 +629,9 @@ alternative_endif
mov \tmp, #PTE_ADDR_LOW
orr \tmp, \tmp, #PTE_ADDR_HIGH
and \pte, \pte, \tmp
+
+.Lskip_lpa2\@:
+ mov \pte, \phys
#else /* !CONFIG_ARM64_PA_BITS_52_LPA */
mov \pte, \phys
#endif /* CONFIG_ARM64_PA_BITS_52_LPA */
@@ -636,9 +643,15 @@ alternative_endif
bfxil \phys, \pte, #PAGE_SHIFT, #(48 - PAGE_SHIFT)
lsl \phys, \phys, #PAGE_SHIFT
#elif defined(CONFIG_ARM64_PA_BITS_52_LPA2)
+ ldr_l \phys, arm64_lpa2_enabled
+ cmp \phys, #1
+ b.ne .Lskip_lpa2\@
+
ubfiz \phys, \pte, #(52 - PAGE_SHIFT - 10), #10
bfxil \phys, \pte, #PAGE_SHIFT, #(50 - PAGE_SHIFT)
lsl \phys, \phys, #PAGE_SHIFT
+.Lskip_lpa2\@:
+ and \phys, \pte, #PTE_ADDR_MASK_48
#else /* !CONFIG_ARM64_PA_BITS_52_LPA */
and \phys, \pte, #PTE_ADDR_MASK
#endif /* CONFIG_ARM64_PA_BITS_52_LPA */
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 8a3b75e..b98b764 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -176,6 +176,8 @@
#define PTE_ADDR_MASK PTE_ADDR_LOW
#endif /* CONFIG_ARM64_PA_BITS_52_LPA */
+#define PTE_ADDR_MASK_48 (((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
+
/*
* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
*/
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 5e7e402..97b3cd2 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -71,9 +71,17 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36))
#define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK)
#elif defined(CONFIG_ARM64_PA_BITS_52_LPA2)
-#define __pte_to_phys(pte) \
+#define __pte_to_phys_52(pte) \
((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 42))
-#define __phys_to_pte_val(phys) (((phys) | ((phys) >> 42)) & PTE_ADDR_MASK)
+#define __phys_to_pte_val_52(phys) (((phys) | ((phys) >> 42)) & PTE_ADDR_MASK)
+
+#define __pte_to_phys_48(pte) (pte_val(pte) & PTE_ADDR_MASK_48)
+#define __phys_to_pte_val_48(phys) (phys)
+
+#define __pte_to_phys(pte) \
+ (arm64_lpa2_enabled ? __pte_to_phys_52(pte) : __pte_to_phys_48(pte))
+#define __phys_to_pte_val(phys) \
+ (arm64_lpa2_enabled ? __phys_to_pte_val_52(phys) : __phys_to_pte_val_48(phys))
#else /* !CONFIG_ARM64_PA_BITS_52_LPA */
#define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
#define __phys_to_pte_val(phys) (phys)
--
2.7.4
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next prev parent reply other threads:[~2021-07-14 2:21 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-14 2:21 [RFC 00/10] arm64/mm: Enable FEAT_LPA2 (52 bits PA support on 4K|16K pages) Anshuman Khandual
2021-07-14 2:21 ` Anshuman Khandual
2021-07-14 2:21 ` [RFC 01/10] mm/mmap: Dynamically initialize protection_map[] Anshuman Khandual
2021-07-14 2:21 ` Anshuman Khandual
2021-07-14 2:21 ` [RFC 02/10] arm64/mm: Consolidate TCR_EL1 fields Anshuman Khandual
2021-07-14 2:21 ` Anshuman Khandual
2021-07-14 2:21 ` [RFC 03/10] arm64/mm: Add FEAT_LPA2 specific TCR_EL1.DS field Anshuman Khandual
2021-07-14 2:21 ` Anshuman Khandual
2021-07-14 2:21 ` [RFC 04/10] arm64/mm: Add FEAT_LPA2 specific ID_AA64MMFR0.TGRAN[2] Anshuman Khandual
2021-07-14 2:21 ` Anshuman Khandual
2021-07-14 2:21 ` [RFC 05/10] arm64/mm: Add CONFIG_ARM64_PA_BITS_52_[LPA|LPA2] Anshuman Khandual
2021-07-14 2:21 ` Anshuman Khandual
2021-07-14 2:21 ` [RFC 06/10] arm64/mm: Add FEAT_LPA2 specific encoding Anshuman Khandual
2021-07-14 2:21 ` Anshuman Khandual
2021-07-14 15:38 ` Steven Price
2021-07-14 15:38 ` Steven Price
2021-07-16 7:20 ` Anshuman Khandual
2021-07-16 7:20 ` Anshuman Khandual
2021-07-16 10:02 ` Steven Price
2021-07-16 10:02 ` Steven Price
2021-07-16 14:37 ` Anshuman Khandual
2021-07-16 14:37 ` Anshuman Khandual
2021-07-14 2:21 ` [RFC 07/10] arm64/mm: Detect and enable FEAT_LPA2 Anshuman Khandual
2021-07-14 2:21 ` Anshuman Khandual
2021-07-14 8:21 ` Suzuki K Poulose
2021-07-14 8:21 ` Suzuki K Poulose
2021-07-16 7:06 ` Anshuman Khandual
2021-07-16 7:06 ` Anshuman Khandual
2021-07-16 8:08 ` Suzuki K Poulose
2021-07-16 8:08 ` Suzuki K Poulose
2021-07-19 4:47 ` Anshuman Khandual
2021-07-19 4:47 ` Anshuman Khandual
2021-07-14 2:21 ` [RFC 08/10] arm64/mm: Add FEAT_LPA2 specific PTE_SHARED and PMD_SECT_S Anshuman Khandual
2021-07-14 2:21 ` Anshuman Khandual
2021-07-14 2:21 ` Anshuman Khandual [this message]
2021-07-14 2:21 ` [RFC 09/10] arm64/mm: Add FEAT_LPA2 specific fallback (48 bits PA) when not implemented Anshuman Khandual
2021-07-14 2:21 ` [RFC 10/10] arm64/mm: Enable CONFIG_ARM64_PA_BITS_52 on CONFIG_ARM64_[4K|16K]_PAGES Anshuman Khandual
2021-07-14 2:21 ` Anshuman Khandual
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