From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Cc: akpm@linux-foundation.org, suzuki.poulose@arm.com, mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, james.morse@arm.com, steven.price@arm.com, Anshuman Khandual <anshuman.khandual@arm.com> Subject: [RFC 07/10] arm64/mm: Detect and enable FEAT_LPA2 Date: Wed, 14 Jul 2021 07:51:28 +0530 [thread overview] Message-ID: <1626229291-6569-8-git-send-email-anshuman.khandual@arm.com> (raw) In-Reply-To: <1626229291-6569-1-git-send-email-anshuman.khandual@arm.com> Detect FEAT_LPA2 implementation early enough during boot when requested via CONFIG_ARM64_PA_BITS_52_LPA2 and remember in a variable arm64_lpa2_enabled. This variable could then be used to turn on TCR_EL1.TCR_DS effecting the 52 bits PA range or fall back to default 48 bits PA range if FEAT_LPA2 feature was requested but found not to be implemented. Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- arch/arm64/include/asm/memory.h | 1 + arch/arm64/kernel/head.S | 15 +++++++++++++++ arch/arm64/mm/mmu.c | 3 +++ arch/arm64/mm/proc.S | 9 +++++++++ 4 files changed, 28 insertions(+) diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index 824a365..d0ca002 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -178,6 +178,7 @@ #include <asm/bug.h> extern u64 vabits_actual; +extern u64 arm64_lpa2_enabled; extern s64 memstart_addr; /* PHYS_OFFSET - the physical address of the start of memory. */ diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 6444147..9cf79ea 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -94,6 +94,21 @@ SYM_CODE_START(primary_entry) adrp x23, __PHYS_OFFSET and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 bl set_cpu_boot_mode_flag + +#ifdef CONFIG_ARM64_PA_BITS_52_LPA2 + mrs x10, ID_AA64MMFR0_EL1 + ubfx x10, x10, #ID_AA64MMFR0_TGRAN_SHIFT, 4 + cmp x10, #ID_AA64MMFR0_TGRAN_LPA2 + b.ne 1f + + mov x10, #1 + adr_l x11, arm64_lpa2_enabled + str x10, [x11] + dmb sy + dc ivac, x11 +1: +#endif /* CONFIG_ARM64_PA_BITS_52_LPA2 */ + bl __create_page_tables /* * The following calls CPU setup code, see arch/arm64/mm/proc.S for diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index d745865..00b7595 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -48,6 +48,9 @@ u64 idmap_ptrs_per_pgd = PTRS_PER_PGD; u64 __section(".mmuoff.data.write") vabits_actual; EXPORT_SYMBOL(vabits_actual); +u64 __section(".mmuoff.data.write") arm64_lpa2_enabled; +EXPORT_SYMBOL(arm64_lpa2_enabled); + u64 kimage_voffset __ro_after_init; EXPORT_SYMBOL(kimage_voffset); diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 1ae0c2b..672880c 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -423,6 +423,15 @@ SYM_FUNC_START(__cpu_setup) TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS +#ifdef CONFIG_ARM64_PA_BITS_52_LPA2 + ldr_l x10, arm64_lpa2_enabled + cmp x10, #1 + b.ne 1f + mov_q x10, TCR_DS + orr tcr, tcr, x10 +1: +#endif /* CONFIG_ARM64_PA_BITS_52_LPA2 */ + #ifdef CONFIG_ARM64_MTE /* * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Cc: akpm@linux-foundation.org, suzuki.poulose@arm.com, mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, james.morse@arm.com, steven.price@arm.com, Anshuman Khandual <anshuman.khandual@arm.com> Subject: [RFC 07/10] arm64/mm: Detect and enable FEAT_LPA2 Date: Wed, 14 Jul 2021 07:51:28 +0530 [thread overview] Message-ID: <1626229291-6569-8-git-send-email-anshuman.khandual@arm.com> (raw) In-Reply-To: <1626229291-6569-1-git-send-email-anshuman.khandual@arm.com> Detect FEAT_LPA2 implementation early enough during boot when requested via CONFIG_ARM64_PA_BITS_52_LPA2 and remember in a variable arm64_lpa2_enabled. This variable could then be used to turn on TCR_EL1.TCR_DS effecting the 52 bits PA range or fall back to default 48 bits PA range if FEAT_LPA2 feature was requested but found not to be implemented. Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- arch/arm64/include/asm/memory.h | 1 + arch/arm64/kernel/head.S | 15 +++++++++++++++ arch/arm64/mm/mmu.c | 3 +++ arch/arm64/mm/proc.S | 9 +++++++++ 4 files changed, 28 insertions(+) diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index 824a365..d0ca002 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -178,6 +178,7 @@ #include <asm/bug.h> extern u64 vabits_actual; +extern u64 arm64_lpa2_enabled; extern s64 memstart_addr; /* PHYS_OFFSET - the physical address of the start of memory. */ diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 6444147..9cf79ea 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -94,6 +94,21 @@ SYM_CODE_START(primary_entry) adrp x23, __PHYS_OFFSET and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 bl set_cpu_boot_mode_flag + +#ifdef CONFIG_ARM64_PA_BITS_52_LPA2 + mrs x10, ID_AA64MMFR0_EL1 + ubfx x10, x10, #ID_AA64MMFR0_TGRAN_SHIFT, 4 + cmp x10, #ID_AA64MMFR0_TGRAN_LPA2 + b.ne 1f + + mov x10, #1 + adr_l x11, arm64_lpa2_enabled + str x10, [x11] + dmb sy + dc ivac, x11 +1: +#endif /* CONFIG_ARM64_PA_BITS_52_LPA2 */ + bl __create_page_tables /* * The following calls CPU setup code, see arch/arm64/mm/proc.S for diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index d745865..00b7595 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -48,6 +48,9 @@ u64 idmap_ptrs_per_pgd = PTRS_PER_PGD; u64 __section(".mmuoff.data.write") vabits_actual; EXPORT_SYMBOL(vabits_actual); +u64 __section(".mmuoff.data.write") arm64_lpa2_enabled; +EXPORT_SYMBOL(arm64_lpa2_enabled); + u64 kimage_voffset __ro_after_init; EXPORT_SYMBOL(kimage_voffset); diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 1ae0c2b..672880c 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -423,6 +423,15 @@ SYM_FUNC_START(__cpu_setup) TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS +#ifdef CONFIG_ARM64_PA_BITS_52_LPA2 + ldr_l x10, arm64_lpa2_enabled + cmp x10, #1 + b.ne 1f + mov_q x10, TCR_DS + orr tcr, tcr, x10 +1: +#endif /* CONFIG_ARM64_PA_BITS_52_LPA2 */ + #ifdef CONFIG_ARM64_MTE /* * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-07-14 2:21 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-14 2:21 [RFC 00/10] arm64/mm: Enable FEAT_LPA2 (52 bits PA support on 4K|16K pages) Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 01/10] mm/mmap: Dynamically initialize protection_map[] Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 02/10] arm64/mm: Consolidate TCR_EL1 fields Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 03/10] arm64/mm: Add FEAT_LPA2 specific TCR_EL1.DS field Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 04/10] arm64/mm: Add FEAT_LPA2 specific ID_AA64MMFR0.TGRAN[2] Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 05/10] arm64/mm: Add CONFIG_ARM64_PA_BITS_52_[LPA|LPA2] Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 06/10] arm64/mm: Add FEAT_LPA2 specific encoding Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 15:38 ` Steven Price 2021-07-14 15:38 ` Steven Price 2021-07-16 7:20 ` Anshuman Khandual 2021-07-16 7:20 ` Anshuman Khandual 2021-07-16 10:02 ` Steven Price 2021-07-16 10:02 ` Steven Price 2021-07-16 14:37 ` Anshuman Khandual 2021-07-16 14:37 ` Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual [this message] 2021-07-14 2:21 ` [RFC 07/10] arm64/mm: Detect and enable FEAT_LPA2 Anshuman Khandual 2021-07-14 8:21 ` Suzuki K Poulose 2021-07-14 8:21 ` Suzuki K Poulose 2021-07-16 7:06 ` Anshuman Khandual 2021-07-16 7:06 ` Anshuman Khandual 2021-07-16 8:08 ` Suzuki K Poulose 2021-07-16 8:08 ` Suzuki K Poulose 2021-07-19 4:47 ` Anshuman Khandual 2021-07-19 4:47 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 08/10] arm64/mm: Add FEAT_LPA2 specific PTE_SHARED and PMD_SECT_S Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 09/10] arm64/mm: Add FEAT_LPA2 specific fallback (48 bits PA) when not implemented Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 10/10] arm64/mm: Enable CONFIG_ARM64_PA_BITS_52 on CONFIG_ARM64_[4K|16K]_PAGES Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual
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