From: Anshuman Khandual <anshuman.khandual@arm.com> To: Steven Price <steven.price@arm.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Cc: akpm@linux-foundation.org, suzuki.poulose@arm.com, mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, james.morse@arm.com Subject: Re: [RFC 06/10] arm64/mm: Add FEAT_LPA2 specific encoding Date: Fri, 16 Jul 2021 12:50:49 +0530 [thread overview] Message-ID: <b471b41b-de6d-3b56-2595-30586b0a47b3@arm.com> (raw) In-Reply-To: <9f0d9925-3694-3fae-0d09-00adbecd1878@arm.com> On 7/14/21 9:08 PM, Steven Price wrote: > On 14/07/2021 03:21, Anshuman Khandual wrote: >> FEAT_LPA2 requires different PTE representation formats for both 4K and 16K >> page size config. This adds FEAT_LPA2 specific new PTE encodings as per ARM >> ARM (0487G.A) which updates [pte|phys]_to_[phys|pte](). The updated helpers >> would be used when FEAT_LPA2 gets enabled via CONFIG_ARM64_PA_BITS_52 on 4K >> and 16K page size. Although TTBR encoding and phys_to_ttbr() helper remains >> the same as FEAT_LPA for FEAT_LPA2 as well. It updates 'phys_to_pte' helper >> to accept a temporary variable and changes impacted call sites. >> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> >> --- >> arch/arm64/include/asm/assembler.h | 23 +++++++++++++++++++---- >> arch/arm64/include/asm/pgtable-hwdef.h | 4 ++++ >> arch/arm64/include/asm/pgtable.h | 4 ++++ >> arch/arm64/kernel/head.S | 25 +++++++++++++------------ >> 4 files changed, 40 insertions(+), 16 deletions(-) >> >> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h >> index fedc202..0492543 100644 >> --- a/arch/arm64/include/asm/assembler.h >> +++ b/arch/arm64/include/asm/assembler.h >> @@ -606,7 +606,7 @@ alternative_endif >> #endif >> .endm >> >> - .macro phys_to_pte, pte, phys >> + .macro phys_to_pte, pte, phys, tmp >> #ifdef CONFIG_ARM64_PA_BITS_52_LPA >> /* >> * We assume \phys is 64K aligned and this is guaranteed by only >> @@ -614,6 +614,17 @@ alternative_endif >> */ >> orr \pte, \phys, \phys, lsr #36 >> and \pte, \pte, #PTE_ADDR_MASK >> +#elif defined(CONFIG_ARM64_PA_BITS_52_LPA2) >> + orr \pte, \phys, \phys, lsr #42 >> + >> + /* >> + * The 'tmp' is being used here to just prepare >> + * and hold PTE_ADDR_MASK which cannot be passed >> + * to the subsequent 'and' instruction. >> + */ >> + mov \tmp, #PTE_ADDR_LOW >> + orr \tmp, \tmp, #PTE_ADDR_HIGH >> + and \pte, \pte, \tmp > Rather than adding an extra temporary register (and the fallout of > various other macros needing an extra register), this can be done with > two AND instructions: I would really like to get rid of the 'tmp' variable here as well but did not figure out any method of accomplishing it. > > /* PTE_ADDR_MASK cannot be encoded as an immediate, so > * mask off all but two bits, followed by masking the > * extra two bits > */ > and \pte, \pte, #PTE_ADDR_MASK | (3 << 10) > and \pte, \pte, #~(3 << 10) Did this change as suggested --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -626,9 +626,8 @@ alternative_endif * and hold PTE_ADDR_MASK which cannot be passed * to the subsequent 'and' instruction. */ - mov \tmp, #PTE_ADDR_LOW - orr \tmp, \tmp, #PTE_ADDR_HIGH - and \pte, \pte, \tmp + and \pte, \pte, #PTE_ADDR_MASK | (0x3 << 10) + and \pte, \pte, #~(0x3 << 10) .Lskip_lpa2\@: mov \pte, \phys but still fails to build (tested on 16K) arch/arm64/kernel/head.S: Assembler messages: arch/arm64/kernel/head.S:377: Error: immediate out of range at operand 3 -- `and x6,x6,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)' arch/arm64/kernel/head.S:390: Error: immediate out of range at operand 3 -- `and x12,x12,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)' arch/arm64/kernel/head.S:390: Error: immediate out of range at operand 3 -- `and x12,x12,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)' arch/arm64/kernel/head.S:404: Error: immediate out of range at operand 3 -- `and x12,x12,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)' arch/arm64/kernel/head.S:404: Error: immediate out of range at operand 3 -- `and x12,x12,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)'
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com> To: Steven Price <steven.price@arm.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Cc: akpm@linux-foundation.org, suzuki.poulose@arm.com, mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, james.morse@arm.com Subject: Re: [RFC 06/10] arm64/mm: Add FEAT_LPA2 specific encoding Date: Fri, 16 Jul 2021 12:50:49 +0530 [thread overview] Message-ID: <b471b41b-de6d-3b56-2595-30586b0a47b3@arm.com> (raw) In-Reply-To: <9f0d9925-3694-3fae-0d09-00adbecd1878@arm.com> On 7/14/21 9:08 PM, Steven Price wrote: > On 14/07/2021 03:21, Anshuman Khandual wrote: >> FEAT_LPA2 requires different PTE representation formats for both 4K and 16K >> page size config. This adds FEAT_LPA2 specific new PTE encodings as per ARM >> ARM (0487G.A) which updates [pte|phys]_to_[phys|pte](). The updated helpers >> would be used when FEAT_LPA2 gets enabled via CONFIG_ARM64_PA_BITS_52 on 4K >> and 16K page size. Although TTBR encoding and phys_to_ttbr() helper remains >> the same as FEAT_LPA for FEAT_LPA2 as well. It updates 'phys_to_pte' helper >> to accept a temporary variable and changes impacted call sites. >> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> >> --- >> arch/arm64/include/asm/assembler.h | 23 +++++++++++++++++++---- >> arch/arm64/include/asm/pgtable-hwdef.h | 4 ++++ >> arch/arm64/include/asm/pgtable.h | 4 ++++ >> arch/arm64/kernel/head.S | 25 +++++++++++++------------ >> 4 files changed, 40 insertions(+), 16 deletions(-) >> >> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h >> index fedc202..0492543 100644 >> --- a/arch/arm64/include/asm/assembler.h >> +++ b/arch/arm64/include/asm/assembler.h >> @@ -606,7 +606,7 @@ alternative_endif >> #endif >> .endm >> >> - .macro phys_to_pte, pte, phys >> + .macro phys_to_pte, pte, phys, tmp >> #ifdef CONFIG_ARM64_PA_BITS_52_LPA >> /* >> * We assume \phys is 64K aligned and this is guaranteed by only >> @@ -614,6 +614,17 @@ alternative_endif >> */ >> orr \pte, \phys, \phys, lsr #36 >> and \pte, \pte, #PTE_ADDR_MASK >> +#elif defined(CONFIG_ARM64_PA_BITS_52_LPA2) >> + orr \pte, \phys, \phys, lsr #42 >> + >> + /* >> + * The 'tmp' is being used here to just prepare >> + * and hold PTE_ADDR_MASK which cannot be passed >> + * to the subsequent 'and' instruction. >> + */ >> + mov \tmp, #PTE_ADDR_LOW >> + orr \tmp, \tmp, #PTE_ADDR_HIGH >> + and \pte, \pte, \tmp > Rather than adding an extra temporary register (and the fallout of > various other macros needing an extra register), this can be done with > two AND instructions: I would really like to get rid of the 'tmp' variable here as well but did not figure out any method of accomplishing it. > > /* PTE_ADDR_MASK cannot be encoded as an immediate, so > * mask off all but two bits, followed by masking the > * extra two bits > */ > and \pte, \pte, #PTE_ADDR_MASK | (3 << 10) > and \pte, \pte, #~(3 << 10) Did this change as suggested --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -626,9 +626,8 @@ alternative_endif * and hold PTE_ADDR_MASK which cannot be passed * to the subsequent 'and' instruction. */ - mov \tmp, #PTE_ADDR_LOW - orr \tmp, \tmp, #PTE_ADDR_HIGH - and \pte, \pte, \tmp + and \pte, \pte, #PTE_ADDR_MASK | (0x3 << 10) + and \pte, \pte, #~(0x3 << 10) .Lskip_lpa2\@: mov \pte, \phys but still fails to build (tested on 16K) arch/arm64/kernel/head.S: Assembler messages: arch/arm64/kernel/head.S:377: Error: immediate out of range at operand 3 -- `and x6,x6,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)' arch/arm64/kernel/head.S:390: Error: immediate out of range at operand 3 -- `and x12,x12,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)' arch/arm64/kernel/head.S:390: Error: immediate out of range at operand 3 -- `and x12,x12,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)' arch/arm64/kernel/head.S:404: Error: immediate out of range at operand 3 -- `and x12,x12,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)' arch/arm64/kernel/head.S:404: Error: immediate out of range at operand 3 -- `and x12,x12,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)' _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-07-16 7:20 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-14 2:21 [RFC 00/10] arm64/mm: Enable FEAT_LPA2 (52 bits PA support on 4K|16K pages) Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 01/10] mm/mmap: Dynamically initialize protection_map[] Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 02/10] arm64/mm: Consolidate TCR_EL1 fields Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 03/10] arm64/mm: Add FEAT_LPA2 specific TCR_EL1.DS field Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 04/10] arm64/mm: Add FEAT_LPA2 specific ID_AA64MMFR0.TGRAN[2] Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 05/10] arm64/mm: Add CONFIG_ARM64_PA_BITS_52_[LPA|LPA2] Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 06/10] arm64/mm: Add FEAT_LPA2 specific encoding Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 15:38 ` Steven Price 2021-07-14 15:38 ` Steven Price 2021-07-16 7:20 ` Anshuman Khandual [this message] 2021-07-16 7:20 ` Anshuman Khandual 2021-07-16 10:02 ` Steven Price 2021-07-16 10:02 ` Steven Price 2021-07-16 14:37 ` Anshuman Khandual 2021-07-16 14:37 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 07/10] arm64/mm: Detect and enable FEAT_LPA2 Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 8:21 ` Suzuki K Poulose 2021-07-14 8:21 ` Suzuki K Poulose 2021-07-16 7:06 ` Anshuman Khandual 2021-07-16 7:06 ` Anshuman Khandual 2021-07-16 8:08 ` Suzuki K Poulose 2021-07-16 8:08 ` Suzuki K Poulose 2021-07-19 4:47 ` Anshuman Khandual 2021-07-19 4:47 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 08/10] arm64/mm: Add FEAT_LPA2 specific PTE_SHARED and PMD_SECT_S Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 09/10] arm64/mm: Add FEAT_LPA2 specific fallback (48 bits PA) when not implemented Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual 2021-07-14 2:21 ` [RFC 10/10] arm64/mm: Enable CONFIG_ARM64_PA_BITS_52 on CONFIG_ARM64_[4K|16K]_PAGES Anshuman Khandual 2021-07-14 2:21 ` Anshuman Khandual
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