From: Richard Zhu <hongxing.zhu@nxp.com> To: l.stach@pengutronix.de, bhelgaas@google.com, robh+dt@kernel.org, broonie@kernel.org, lorenzo.pieralisi@arm.com, jingoohan1@gmail.com, festevam@gmail.com, francesco.dolcini@toradex.com Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v9 8/8] PCI: imx6: Add compliance tests mode support Date: Fri, 6 May 2022 09:47:09 +0800 [thread overview] Message-ID: <1651801629-30223-9-git-send-email-hongxing.zhu@nxp.com> (raw) In-Reply-To: <1651801629-30223-1-git-send-email-hongxing.zhu@nxp.com> Refer to the Chapter 3.2 System Board Signal Quality of PCI Express Architecture PHY Test Specification Revision 2.0. Signal quality tests (for example: jitter, differential eye opening and so on) can be executed with devices in the polling.compliance state. To let the device support polling.compliance state, the clocks and powers shouldn't be turned off when the probe of device driver fails. Based on CLB (Compliance Load Board) Test Fixture and so on test equipments, the PHY link would be down during the compliance tests. Refer to this scenario, add the i.MX PCIe compliance tests mode enable support, and keep the clocks and powers on, and finish the driver probe without error return. Use the "pci_imx6.compliance=1" in kernel command line to enable the compliance tests mode. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 39 ++++++++++++++++++--------- 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index f0ffd9011975..f78b59822626 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -146,6 +146,10 @@ struct imx6_pcie { #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) +static bool imx6_pcie_cmp_mode; +module_param_named(compliance, imx6_pcie_cmp_mode, bool, 0644); +MODULE_PARM_DESC(compliance, "i.MX PCIe compliance test mode (1=compliance test mode enabled)"); + static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) { struct dw_pcie *pci = imx6_pcie->pci; @@ -826,10 +830,12 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) * started in Gen2 mode, there is a possibility the devices on the * bus will not be detected at all. This happens with PCIe switches. */ - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); - tmp &= ~PCI_EXP_LNKCAP_SLS; - tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + if (!imx6_pcie_cmp_mode) { + tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + tmp &= ~PCI_EXP_LNKCAP_SLS; + tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + } /* Start LTSSM. */ imx6_pcie_ltssm_enable(dev); @@ -887,14 +893,16 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); - imx6_pcie_reset_phy(imx6_pcie); - imx6_pcie_clk_disable(imx6_pcie); - if (imx6_pcie->phy != NULL) { - phy_power_off(imx6_pcie->phy); - phy_exit(imx6_pcie->phy); + if (!imx6_pcie_cmp_mode) { + imx6_pcie_reset_phy(imx6_pcie); + imx6_pcie_clk_disable(imx6_pcie); + if (imx6_pcie->phy != NULL) { + phy_power_off(imx6_pcie->phy); + phy_exit(imx6_pcie->phy); + } + if (imx6_pcie->vpcie) + regulator_disable(imx6_pcie->vpcie); } - if (imx6_pcie->vpcie) - regulator_disable(imx6_pcie->vpcie); return ret; } @@ -1289,8 +1297,15 @@ static int imx6_pcie_probe(struct platform_device *pdev) return ret; ret = dw_pcie_host_init(&pci->pp); - if (ret < 0) + if (ret < 0) { + if (imx6_pcie_cmp_mode) { + dev_info(dev, "driver loaded with compliance test mode enabled\n"); + ret = 0; + } else { + dev_err(dev, "unable to add PCIe port\n"); + } return ret; + } if (pci_msi_enabled()) { u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Richard Zhu <hongxing.zhu@nxp.com> To: l.stach@pengutronix.de, bhelgaas@google.com, robh+dt@kernel.org, broonie@kernel.org, lorenzo.pieralisi@arm.com, jingoohan1@gmail.com, festevam@gmail.com, francesco.dolcini@toradex.com Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v9 8/8] PCI: imx6: Add compliance tests mode support Date: Fri, 6 May 2022 09:47:09 +0800 [thread overview] Message-ID: <1651801629-30223-9-git-send-email-hongxing.zhu@nxp.com> (raw) In-Reply-To: <1651801629-30223-1-git-send-email-hongxing.zhu@nxp.com> Refer to the Chapter 3.2 System Board Signal Quality of PCI Express Architecture PHY Test Specification Revision 2.0. Signal quality tests (for example: jitter, differential eye opening and so on) can be executed with devices in the polling.compliance state. To let the device support polling.compliance state, the clocks and powers shouldn't be turned off when the probe of device driver fails. Based on CLB (Compliance Load Board) Test Fixture and so on test equipments, the PHY link would be down during the compliance tests. Refer to this scenario, add the i.MX PCIe compliance tests mode enable support, and keep the clocks and powers on, and finish the driver probe without error return. Use the "pci_imx6.compliance=1" in kernel command line to enable the compliance tests mode. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 39 ++++++++++++++++++--------- 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index f0ffd9011975..f78b59822626 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -146,6 +146,10 @@ struct imx6_pcie { #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) +static bool imx6_pcie_cmp_mode; +module_param_named(compliance, imx6_pcie_cmp_mode, bool, 0644); +MODULE_PARM_DESC(compliance, "i.MX PCIe compliance test mode (1=compliance test mode enabled)"); + static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) { struct dw_pcie *pci = imx6_pcie->pci; @@ -826,10 +830,12 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) * started in Gen2 mode, there is a possibility the devices on the * bus will not be detected at all. This happens with PCIe switches. */ - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); - tmp &= ~PCI_EXP_LNKCAP_SLS; - tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + if (!imx6_pcie_cmp_mode) { + tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + tmp &= ~PCI_EXP_LNKCAP_SLS; + tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + } /* Start LTSSM. */ imx6_pcie_ltssm_enable(dev); @@ -887,14 +893,16 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); - imx6_pcie_reset_phy(imx6_pcie); - imx6_pcie_clk_disable(imx6_pcie); - if (imx6_pcie->phy != NULL) { - phy_power_off(imx6_pcie->phy); - phy_exit(imx6_pcie->phy); + if (!imx6_pcie_cmp_mode) { + imx6_pcie_reset_phy(imx6_pcie); + imx6_pcie_clk_disable(imx6_pcie); + if (imx6_pcie->phy != NULL) { + phy_power_off(imx6_pcie->phy); + phy_exit(imx6_pcie->phy); + } + if (imx6_pcie->vpcie) + regulator_disable(imx6_pcie->vpcie); } - if (imx6_pcie->vpcie) - regulator_disable(imx6_pcie->vpcie); return ret; } @@ -1289,8 +1297,15 @@ static int imx6_pcie_probe(struct platform_device *pdev) return ret; ret = dw_pcie_host_init(&pci->pp); - if (ret < 0) + if (ret < 0) { + if (imx6_pcie_cmp_mode) { + dev_info(dev, "driver loaded with compliance test mode enabled\n"); + ret = 0; + } else { + dev_err(dev, "unable to add PCIe port\n"); + } return ret; + } if (pci_msi_enabled()) { u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-05-06 1:59 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-06 1:47 [PATCH v9 0/8] PCI: imx6: refine codes and add compliance tests mode support Richard Zhu 2022-05-06 1:47 ` Richard Zhu 2022-05-06 1:47 ` [PATCH v9 1/8] PCI: imx6: Encapsulate the clock enable into one standalone function Richard Zhu 2022-05-06 1:47 ` Richard Zhu 2022-06-08 18:51 ` Bjorn Helgaas 2022-06-08 18:51 ` Bjorn Helgaas 2022-06-09 6:18 ` Hongxing Zhu 2022-06-09 6:18 ` Hongxing Zhu 2022-05-06 1:47 ` [PATCH v9 2/8] PCI: imx6: Add the error propagation from host_init Richard Zhu 2022-05-06 1:47 ` Richard Zhu 2022-06-08 18:53 ` Bjorn Helgaas 2022-06-08 18:53 ` Bjorn Helgaas 2022-06-09 6:19 ` Hongxing Zhu 2022-06-09 6:19 ` Hongxing Zhu 2022-05-06 1:47 ` [PATCH v9 3/8] PCI: imx6: Move imx6_pcie_clk_disable() earlier Richard Zhu 2022-05-06 1:47 ` Richard Zhu 2022-06-08 7:14 ` Lucas Stach 2022-06-08 7:14 ` Lucas Stach 2022-05-06 1:47 ` [PATCH v9 4/8] PCI: imx6: Disable iMX6QDL PCIe REF clock when disable PCIe clocks Richard Zhu 2022-05-06 1:47 ` Richard Zhu 2022-06-08 7:18 ` Lucas Stach 2022-06-08 7:18 ` Lucas Stach 2022-05-06 1:47 ` [PATCH v9 5/8] PCI: imx6: Refine the regulator usage Richard Zhu 2022-05-06 1:47 ` Richard Zhu 2022-06-08 7:26 ` Lucas Stach 2022-06-08 7:26 ` Lucas Stach 2022-06-09 6:17 ` Hongxing Zhu 2022-06-09 6:17 ` Hongxing Zhu 2022-06-09 7:47 ` Lucas Stach 2022-06-09 7:47 ` Lucas Stach 2022-06-09 7:54 ` Hongxing Zhu 2022-06-09 7:54 ` Hongxing Zhu 2022-06-08 18:54 ` Bjorn Helgaas 2022-06-08 18:54 ` Bjorn Helgaas 2022-06-09 6:19 ` Hongxing Zhu 2022-06-09 6:19 ` Hongxing Zhu 2022-06-09 17:20 ` Bjorn Helgaas 2022-06-09 17:20 ` Bjorn Helgaas 2022-06-10 7:09 ` Hongxing Zhu 2022-06-10 7:09 ` Hongxing Zhu 2022-05-06 1:47 ` [PATCH v9 6/8] PCI: imx6: Disable clocks and regulators after link is down Richard Zhu 2022-05-06 1:47 ` Richard Zhu 2022-06-08 7:35 ` Lucas Stach 2022-06-08 7:35 ` Lucas Stach 2022-06-09 6:17 ` Hongxing Zhu 2022-06-09 6:17 ` Hongxing Zhu 2022-06-09 7:53 ` Francesco Dolcini 2022-06-09 7:53 ` Francesco Dolcini 2022-06-09 8:36 ` Hongxing Zhu 2022-06-09 8:36 ` Hongxing Zhu 2022-06-09 7:55 ` Lucas Stach 2022-06-09 7:55 ` Lucas Stach 2022-06-09 8:30 ` Hongxing Zhu 2022-06-09 8:30 ` Hongxing Zhu 2022-05-06 1:47 ` [PATCH v9 7/8] PCI: imx6: Move the phy driver callbacks to the proper places Richard Zhu 2022-05-06 1:47 ` Richard Zhu 2022-06-08 7:44 ` Lucas Stach 2022-06-08 7:44 ` Lucas Stach 2022-06-09 6:18 ` Hongxing Zhu 2022-06-09 6:18 ` Hongxing Zhu 2022-06-08 18:57 ` Bjorn Helgaas 2022-06-08 18:57 ` Bjorn Helgaas 2022-06-09 6:20 ` Hongxing Zhu 2022-06-09 6:20 ` Hongxing Zhu 2022-06-09 16:25 ` Bjorn Helgaas 2022-06-09 16:25 ` Bjorn Helgaas 2022-06-10 6:51 ` Hongxing Zhu 2022-06-10 6:51 ` Hongxing Zhu 2022-05-06 1:47 ` Richard Zhu [this message] 2022-05-06 1:47 ` [PATCH v9 8/8] PCI: imx6: Add compliance tests mode support Richard Zhu 2022-06-08 7:48 ` Lucas Stach 2022-06-08 7:48 ` Lucas Stach 2022-06-09 6:18 ` Hongxing Zhu 2022-06-09 6:18 ` Hongxing Zhu
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