From: Catalin Marinas <catalin.marinas@arm.com>
To: Mark Brown <broonie@kernel.org>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
linux-arm-kernel@lists.infradead.org,
Marc Zyngier <maz@kernel.org>
Subject: Re: [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers
Date: Mon, 16 May 2022 20:08:15 +0100 [thread overview]
Message-ID: <165272802687.3873653.10476231866149040023.b4-ty@arm.com> (raw)
In-Reply-To: <20220510161208.631259-1-broonie@kernel.org>
On Tue, 10 May 2022 17:11:56 +0100, Mark Brown wrote:
> This series builds on top of the recently applied series for system
> register generation, converting the floating point registers to
> automatic generation. There's nothing remarkable in here, just a bunch
> of straightforward cleanups and the addition of support for RAZ fields
> followed by the actual conversions.
>
> It does skip over the SVCRSM, SVCRZA and SVCRSMZA aliases for now since
> I need to think a little about what to do with those.
>
> [...]
Applied to arm64 (for-next/sysreg-gen), thanks!
(I merged for-next/sme into this branch for dependencies)
[01/12] arm64/fp: Make SVE and SME length register definition match architecture
https://git.kernel.org/arm64/c/f171f9e4097d
[02/12] arm64/fp: Rename SVE and SME LEN field name to _WIDTH
https://git.kernel.org/arm64/c/5b06dcfd9e0a
[03/12] arm64/sme: Drop SYS_ from SMIDR_EL1 defines
https://git.kernel.org/arm64/c/a6dab6cc0f4c
[04/12] arm64/sme: Standardise bitfield names for SVCR
https://git.kernel.org/arm64/c/e65fc01bf271
[05/12] arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h
https://git.kernel.org/arm64/c/ec0067a63e5a
[06/12] arm64/sysreg: Support generation of RAZ fields
https://git.kernel.org/arm64/c/9e2c0819ac85
[07/12] arm64/sme: Automatically generate defines for SMCR
https://git.kernel.org/arm64/c/0d1322e7ea75
[08/12] arm64/sme: Automatically generate SMIDR_EL1 defines
https://git.kernel.org/arm64/c/c37b8700b723
[09/12] arm64/sme: Automatically generate SMPRIMAP_EL2 definitions
https://git.kernel.org/arm64/c/8e053810e6ce
[10/12] arm64/sme: Generate SMPRI_EL1 definitions
https://git.kernel.org/arm64/c/9321f0492b89
[11/12] arm64/sme: Generate defintions for SVCR
https://git.kernel.org/arm64/c/11e12a91c118
[12/12] arm64/sve: Generate ZCR definitions
https://git.kernel.org/arm64/c/89e9fb327421
--
Catalin
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prev parent reply other threads:[~2022-05-16 19:09 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
2022-05-10 16:11 ` [PATCH v1 01/12] arm64/fp: Make SVE and SME length register definition match architecture Mark Brown
2022-05-10 16:11 ` [PATCH v1 02/12] arm64/fp: Rename SVE and SME LEN field name to _WIDTH Mark Brown
2022-05-10 16:11 ` [PATCH v1 03/12] arm64/sme: Drop SYS_ from SMIDR_EL1 defines Mark Brown
2022-05-10 16:12 ` [PATCH v1 04/12] arm64/sme: Standardise bitfield names for SVCR Mark Brown
2022-05-10 16:12 ` [PATCH v1 05/12] arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h Mark Brown
2022-05-13 14:16 ` Mark Rutland
2022-05-13 19:39 ` Mark Brown
2022-05-10 16:12 ` [PATCH v1 06/12] arm64/sysreg: Support generation of RAZ fields Mark Brown
2022-05-13 14:18 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 07/12] arm64/sme: Automatically generate defines for SMCR Mark Brown
2022-05-13 14:31 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 08/12] arm64/sme: Automatically generate SMIDR_EL1 defines Mark Brown
2022-05-13 14:35 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 09/12] arm64/sme: Automatically generate SMPRIMAP_EL2 definitions Mark Brown
2022-05-13 14:38 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 10/12] arm64/sme: Generate SMPRI_EL1 definitions Mark Brown
2022-05-13 14:39 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 11/12] arm64/sme: Generate defintions for SVCR Mark Brown
2022-05-13 14:41 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 12/12] arm64/sve: Generate ZCR definitions Mark Brown
2022-05-13 14:46 ` Mark Rutland
2022-05-16 19:08 ` Catalin Marinas [this message]
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