From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 07/12] arm64/sme: Automatically generate defines for SMCR
Date: Fri, 13 May 2022 15:31:57 +0100 [thread overview]
Message-ID: <Yn5r3cLLZIYtrA9w@lakrids> (raw)
In-Reply-To: <20220510161208.631259-8-broonie@kernel.org>
On Tue, May 10, 2022 at 05:12:03PM +0100, Mark Brown wrote:
> Convert SMCR to use the register definition code, no functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 10 ----------
> arch/arm64/tools/sysreg | 20 ++++++++++++++++++++
> 2 files changed, 20 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index a2f0759f65b2..cbf03a1f316e 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -216,7 +216,6 @@
> #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
> #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
> #define SYS_SMPRI_EL1 sys_reg(3, 0, 1, 2, 4)
> -#define SYS_SMCR_EL1 sys_reg(3, 0, 1, 2, 6)
>
> #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
>
> @@ -571,7 +570,6 @@
> #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
> #define SYS_HCRX_EL2 sys_reg(3, 4, 1, 2, 2)
> #define SYS_SMPRIMAP_EL2 sys_reg(3, 4, 1, 2, 5)
> -#define SYS_SMCR_EL2 sys_reg(3, 4, 1, 2, 6)
> #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
> #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4)
> #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5)
> @@ -631,7 +629,6 @@
> #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
> #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
> #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
> -#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
> #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
> #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
> #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
> @@ -1117,13 +1114,6 @@
> #define ZCR_ELx_LEN_WIDTH 4
> #define ZCR_ELx_LEN_MASK 0xf
>
> -#define SMCR_ELx_FA64_SHIFT 31
> -#define SMCR_ELx_FA64_MASK (1 << SMCR_ELx_FA64_SHIFT)
> -
> -#define SMCR_ELx_LEN_SHIFT 0
> -#define SMCR_ELx_LEN_WIDTH 4
> -#define SMCR_ELx_LEN_MASK 0xf
> -
> #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
> #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
>
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index c5619629bf9c..d0ac57648000 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -185,6 +185,26 @@ Field 1 A
> Field 0 M
> EndSysreg
>
> +SysregFields SMCR_ELx
> +Res0 63:32
> +Field 31 FA64
> +Res0 30:9
> +Raz 8:4
> +Field 3:0 LEN
> +EndSysregFields
> +
> +Sysreg SMCR_EL1 3 0 1 2 6
> +Fields SMCR_ELx
> +EndSysreg
> +
> +Sysreg SMCR_EL2 3 4 1 2 6
> +Fields SMCR_ELx
> +EndSysreg
> +
> +Sysreg SMCR_EL12 3 5 1 2 6
> +Fields SMCR_ELx
> +EndSysreg
These all look right to me, per ARM DDI 0487H.a, so:
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
One minor thing for the benefit of other reviewers: the ARM ARM
describes SMCR_ELx[8:4] as RAZ/WI. I think it's fine to capture that as
RAZ (since the script won't output anything, and just needs some field
type to check we've described all bits), but if other folk want that
captured as RAZ/WI specifically that's also fine by me.
Thanks,
Mark.
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next prev parent reply other threads:[~2022-05-13 14:33 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
2022-05-10 16:11 ` [PATCH v1 01/12] arm64/fp: Make SVE and SME length register definition match architecture Mark Brown
2022-05-10 16:11 ` [PATCH v1 02/12] arm64/fp: Rename SVE and SME LEN field name to _WIDTH Mark Brown
2022-05-10 16:11 ` [PATCH v1 03/12] arm64/sme: Drop SYS_ from SMIDR_EL1 defines Mark Brown
2022-05-10 16:12 ` [PATCH v1 04/12] arm64/sme: Standardise bitfield names for SVCR Mark Brown
2022-05-10 16:12 ` [PATCH v1 05/12] arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h Mark Brown
2022-05-13 14:16 ` Mark Rutland
2022-05-13 19:39 ` Mark Brown
2022-05-10 16:12 ` [PATCH v1 06/12] arm64/sysreg: Support generation of RAZ fields Mark Brown
2022-05-13 14:18 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 07/12] arm64/sme: Automatically generate defines for SMCR Mark Brown
2022-05-13 14:31 ` Mark Rutland [this message]
2022-05-10 16:12 ` [PATCH v1 08/12] arm64/sme: Automatically generate SMIDR_EL1 defines Mark Brown
2022-05-13 14:35 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 09/12] arm64/sme: Automatically generate SMPRIMAP_EL2 definitions Mark Brown
2022-05-13 14:38 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 10/12] arm64/sme: Generate SMPRI_EL1 definitions Mark Brown
2022-05-13 14:39 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 11/12] arm64/sme: Generate defintions for SVCR Mark Brown
2022-05-13 14:41 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 12/12] arm64/sve: Generate ZCR definitions Mark Brown
2022-05-13 14:46 ` Mark Rutland
2022-05-16 19:08 ` [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Catalin Marinas
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