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From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Marc Zyngier <maz@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	Mark Brown <broonie@kernel.org>
Subject: [PATCH v1 04/12] arm64/sme: Standardise bitfield names for SVCR
Date: Tue, 10 May 2022 17:12:00 +0100	[thread overview]
Message-ID: <20220510161208.631259-5-broonie@kernel.org> (raw)
In-Reply-To: <20220510161208.631259-1-broonie@kernel.org>

The bitfield definitions for SVCR have a SYS_ added to the names of the
constant which will be a problem for automatic generation. Remove the
prefixes, no functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/fpsimd.h    | 4 ++--
 arch/arm64/include/asm/processor.h | 2 +-
 arch/arm64/include/asm/sysreg.h    | 4 ++--
 arch/arm64/kernel/fpsimd.c         | 6 +++---
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
index 75caa2098d5b..aa11dbec0d70 100644
--- a/arch/arm64/include/asm/fpsimd.h
+++ b/arch/arm64/include/asm/fpsimd.h
@@ -67,12 +67,12 @@ extern void fpsimd_save_and_flush_cpu_state(void);
 
 static inline bool thread_sm_enabled(struct thread_struct *thread)
 {
-	return system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_SM_MASK);
+	return system_supports_sme() && (thread->svcr & SVCR_EL0_SM_MASK);
 }
 
 static inline bool thread_za_enabled(struct thread_struct *thread)
 {
-	return system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_ZA_MASK);
+	return system_supports_sme() && (thread->svcr & SVCR_EL0_ZA_MASK);
 }
 
 /* Maximum VL that SVE/SME VL-agnostic software can transparently support */
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 1d2ca4870b84..69ce163d2fb2 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -192,7 +192,7 @@ static inline unsigned int thread_get_sme_vl(struct thread_struct *thread)
 
 static inline unsigned int thread_get_cur_vl(struct thread_struct *thread)
 {
-	if (system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_SM_MASK))
+	if (system_supports_sme() && (thread->svcr & SVCR_EL0_SM_MASK))
 		return thread_get_sme_vl(thread);
 	else
 		return thread_get_sve_vl(thread);
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index ab2d7cbc63fc..4459cd4a37f5 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -480,8 +480,8 @@
 #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
 
 #define SYS_SVCR_EL0			sys_reg(3, 3, 4, 2, 2)
-#define SYS_SVCR_EL0_ZA_MASK		2
-#define SYS_SVCR_EL0_SM_MASK		1
+#define SVCR_EL0_ZA_MASK		2
+#define SVCR_EL0_SM_MASK		1
 
 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
 #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 95a733d3b253..8b48e870e14e 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -1893,7 +1893,7 @@ void __efi_fpsimd_begin(void)
 				svcr = read_sysreg_s(SYS_SVCR_EL0);
 
 				if (!system_supports_fa64())
-					ffr = svcr & SYS_SVCR_EL0_SM_MASK;
+					ffr = svcr & SVCR_EL0_SM_MASK;
 
 				__this_cpu_write(efi_sm_state, ffr);
 			}
@@ -1904,7 +1904,7 @@ void __efi_fpsimd_begin(void)
 
 			if (system_supports_sme())
 				sysreg_clear_set_s(SYS_SVCR_EL0,
-						   SYS_SVCR_EL0_SM_MASK, 0);
+						   SVCR_EL0_SM_MASK, 0);
 
 		} else {
 			fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state));
@@ -1939,7 +1939,7 @@ void __efi_fpsimd_end(void)
 				if (__this_cpu_read(efi_sm_state)) {
 					sysreg_clear_set_s(SYS_SVCR_EL0,
 							   0,
-							   SYS_SVCR_EL0_SM_MASK);
+							   SVCR_EL0_SM_MASK);
 					if (!system_supports_fa64())
 						ffr = efi_sm_state;
 				}
-- 
2.30.2


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  parent reply	other threads:[~2022-05-10 16:14 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
2022-05-10 16:11 ` [PATCH v1 01/12] arm64/fp: Make SVE and SME length register definition match architecture Mark Brown
2022-05-10 16:11 ` [PATCH v1 02/12] arm64/fp: Rename SVE and SME LEN field name to _WIDTH Mark Brown
2022-05-10 16:11 ` [PATCH v1 03/12] arm64/sme: Drop SYS_ from SMIDR_EL1 defines Mark Brown
2022-05-10 16:12 ` Mark Brown [this message]
2022-05-10 16:12 ` [PATCH v1 05/12] arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h Mark Brown
2022-05-13 14:16   ` Mark Rutland
2022-05-13 19:39     ` Mark Brown
2022-05-10 16:12 ` [PATCH v1 06/12] arm64/sysreg: Support generation of RAZ fields Mark Brown
2022-05-13 14:18   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 07/12] arm64/sme: Automatically generate defines for SMCR Mark Brown
2022-05-13 14:31   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 08/12] arm64/sme: Automatically generate SMIDR_EL1 defines Mark Brown
2022-05-13 14:35   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 09/12] arm64/sme: Automatically generate SMPRIMAP_EL2 definitions Mark Brown
2022-05-13 14:38   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 10/12] arm64/sme: Generate SMPRI_EL1 definitions Mark Brown
2022-05-13 14:39   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 11/12] arm64/sme: Generate defintions for SVCR Mark Brown
2022-05-13 14:41   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 12/12] arm64/sve: Generate ZCR definitions Mark Brown
2022-05-13 14:46   ` Mark Rutland
2022-05-16 19:08 ` [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Catalin Marinas

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