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From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 10/12] arm64/sme: Generate SMPRI_EL1 definitions
Date: Fri, 13 May 2022 15:39:43 +0100	[thread overview]
Message-ID: <Yn5trzbq/kQpmZJJ@lakrids> (raw)
In-Reply-To: <20220510161208.631259-11-broonie@kernel.org>

On Tue, May 10, 2022 at 05:12:06PM +0100, Mark Brown wrote:
> Convert SMPRI_EL1 to be generated. No functional change.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h | 3 ---
>  arch/arm64/tools/sysreg         | 5 +++++
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 2a9468d449fa..b4affc3fd569 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -215,7 +215,6 @@
>  
>  #define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)
>  #define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
> -#define SYS_SMPRI_EL1			sys_reg(3, 0, 1, 2, 4)
>  
>  #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
>  
> @@ -406,8 +405,6 @@
>  #define TRBIDR_ALIGN_MASK		GENMASK(3, 0)
>  #define TRBIDR_ALIGN_SHIFT		0
>  
> -#define SMPRI_EL1_PRIORITY_MASK		0xf
> -
>  #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
>  #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
>  
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 2cdcdac0465e..d29bc429f504 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -185,6 +185,11 @@ Field	1	A
>  Field	0	M
>  EndSysreg
>  
> +Sysreg	SMPRI_EL1	3	0	1	2	4
> +Res0	63:4
> +Field	3:0	PRIORITY
> +EndSysreg

These all look right to me per ARM DDI 0487H.a, section D13.2.130, pages
D13-5943 to D13-5945.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>

Mark.

> +
>  SysregFields	SMCR_ELx
>  Res0	63:32
>  Field	31	FA64
> -- 
> 2.30.2
> 

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  reply	other threads:[~2022-05-13 14:40 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
2022-05-10 16:11 ` [PATCH v1 01/12] arm64/fp: Make SVE and SME length register definition match architecture Mark Brown
2022-05-10 16:11 ` [PATCH v1 02/12] arm64/fp: Rename SVE and SME LEN field name to _WIDTH Mark Brown
2022-05-10 16:11 ` [PATCH v1 03/12] arm64/sme: Drop SYS_ from SMIDR_EL1 defines Mark Brown
2022-05-10 16:12 ` [PATCH v1 04/12] arm64/sme: Standardise bitfield names for SVCR Mark Brown
2022-05-10 16:12 ` [PATCH v1 05/12] arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h Mark Brown
2022-05-13 14:16   ` Mark Rutland
2022-05-13 19:39     ` Mark Brown
2022-05-10 16:12 ` [PATCH v1 06/12] arm64/sysreg: Support generation of RAZ fields Mark Brown
2022-05-13 14:18   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 07/12] arm64/sme: Automatically generate defines for SMCR Mark Brown
2022-05-13 14:31   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 08/12] arm64/sme: Automatically generate SMIDR_EL1 defines Mark Brown
2022-05-13 14:35   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 09/12] arm64/sme: Automatically generate SMPRIMAP_EL2 definitions Mark Brown
2022-05-13 14:38   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 10/12] arm64/sme: Generate SMPRI_EL1 definitions Mark Brown
2022-05-13 14:39   ` Mark Rutland [this message]
2022-05-10 16:12 ` [PATCH v1 11/12] arm64/sme: Generate defintions for SVCR Mark Brown
2022-05-13 14:41   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 12/12] arm64/sve: Generate ZCR definitions Mark Brown
2022-05-13 14:46   ` Mark Rutland
2022-05-16 19:08 ` [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Catalin Marinas

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