* [PATCH 0/2] sunxi: clk: fix unhandled clocks warnings
@ 2022-05-06 0:32 Andre Przywara
2022-05-06 0:33 ` [PATCH 1/2] clk: sunxi: add PIO bus gate clocks Andre Przywara
2022-05-06 0:33 ` [PATCH 2/2] clk: sunxi: add and use dummy " Andre Przywara
0 siblings, 2 replies; 7+ messages in thread
From: Andre Przywara @ 2022-05-06 0:32 UTC (permalink / raw)
To: Jagan Teki
Cc: Samuel Holland, Jernej Skrabec, Lukasz Majewski, Sean Anderson,
u-boot, linux-sunxi
The introduction of the DM pinctrl driver saw many clocks, referenced in
the respective pinctrl DT nodes, being enabled by the DM clock driver.
We didn't model all them correctly, so there are now some warnings on
the console when booting:
=========
sunxi_set_gate: (CLK#58) unhandled
=========
This series fixes them. The first patch just describes some missing gate
clocks, mostly for the pin controller directly.
The second patch introduces a GATE_DUMMY macro, that allows to just
ignore some other clocks, and to suppress the warnings.
Please have a look and test!
Cheers,
Andre
Andre Przywara (2):
clk: sunxi: add PIO bus gate clocks
clk: sunxi: add and use dummy gate clocks
drivers/clk/sunxi/clk_a10.c | 2 ++
drivers/clk/sunxi/clk_a10s.c | 2 ++
drivers/clk/sunxi/clk_a23.c | 2 ++
drivers/clk/sunxi/clk_a31.c | 2 ++
drivers/clk/sunxi/clk_a64.c | 4 ++++
drivers/clk/sunxi/clk_a80.c | 2 ++
drivers/clk/sunxi/clk_a83t.c | 2 ++
drivers/clk/sunxi/clk_h3.c | 4 ++++
drivers/clk/sunxi/clk_h6.c | 4 ++++
drivers/clk/sunxi/clk_h616.c | 4 ++++
drivers/clk/sunxi/clk_h6_r.c | 2 ++
drivers/clk/sunxi/clk_r40.c | 2 ++
drivers/clk/sunxi/clk_sunxi.c | 3 +++
drivers/clk/sunxi/clk_v3s.c | 2 ++
include/clk/sunxi.h | 5 +++++
15 files changed, 42 insertions(+)
--
2.35.3
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] clk: sunxi: add PIO bus gate clocks
2022-05-06 0:32 [PATCH 0/2] sunxi: clk: fix unhandled clocks warnings Andre Przywara
@ 2022-05-06 0:33 ` Andre Przywara
2022-05-07 1:47 ` Samuel Holland
2022-05-24 16:12 ` Andre Przywara
2022-05-06 0:33 ` [PATCH 2/2] clk: sunxi: add and use dummy " Andre Przywara
1 sibling, 2 replies; 7+ messages in thread
From: Andre Przywara @ 2022-05-06 0:33 UTC (permalink / raw)
To: Jagan Teki
Cc: Samuel Holland, Jernej Skrabec, Lukasz Majewski, Sean Anderson,
u-boot, linux-sunxi
The introduction of the DM pinctrl driver made its probe function enable
all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and
variations) gate clock, but also CLK_PLL_PERIPH0. So far we didn't
describe those clocks in our clock driver.
As we enable them already in the SPL, the devices happen to work, but
the clock driver still complains about not finding those clocks:
=========
sunxi_set_gate: (CLK#58) unhandled
=========
Add the one-liners that are needed to announce the gate bit for those
clocks, to silence that message on the console.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/clk/sunxi/clk_a10.c | 2 ++
drivers/clk/sunxi/clk_a10s.c | 2 ++
drivers/clk/sunxi/clk_a23.c | 2 ++
drivers/clk/sunxi/clk_a31.c | 2 ++
drivers/clk/sunxi/clk_a64.c | 4 ++++
drivers/clk/sunxi/clk_a80.c | 2 ++
drivers/clk/sunxi/clk_a83t.c | 2 ++
drivers/clk/sunxi/clk_h3.c | 4 ++++
drivers/clk/sunxi/clk_h6.c | 2 ++
drivers/clk/sunxi/clk_h616.c | 2 ++
drivers/clk/sunxi/clk_r40.c | 2 ++
drivers/clk/sunxi/clk_v3s.c | 2 ++
12 files changed, 28 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index 90b929d3d32..db92848aafd 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -31,6 +31,8 @@ static struct ccu_clk_gate a10_gates[] = {
[CLK_AHB_GMAC] = GATE(0x064, BIT(17)),
+ [CLK_APB0_PIO] = GATE(0x068, BIT(5)),
+
[CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
[CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
[CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index addf4f4d5cd..0c6564ef3b6 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -25,6 +25,8 @@ static struct ccu_clk_gate a10s_gates[] = {
[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
[CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
+ [CLK_APB0_PIO] = GATE(0x068, BIT(5)),
+
[CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
[CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
[CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index c45d2c35298..0280fb51e2d 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -23,6 +23,8 @@ static struct ccu_clk_gate a23_gates[] = {
[CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
[CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
+ [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
+
[CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 251fc3b705e..26d25f32408 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -30,6 +30,8 @@ static struct ccu_clk_gate a31_gates[] = {
[CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
[CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
+ [CLK_APB1_PIO] = GATE(0x068, BIT(5)),
+
[CLK_APB2_I2C0] = GATE(0x06c, BIT(0)),
[CLK_APB2_I2C1] = GATE(0x06c, BIT(1)),
[CLK_APB2_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 1004a795033..cbb9168edb9 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -14,6 +14,8 @@
#include <linux/bitops.h>
static const struct ccu_clk_gate a64_gates[] = {
+ [CLK_PLL_PERIPH0] = GATE(0x028, BIT(31)),
+
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
@@ -26,6 +28,8 @@ static const struct ccu_clk_gate a64_gates[] = {
[CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
[CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
+ [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
+
[CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index 8a0834d83a3..1ee1f99a8f4 100644
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -25,6 +25,8 @@ static const struct ccu_clk_gate a80_gates[] = {
[CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
[CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
+ [CLK_BUS_PIO] = GATE(0x590, BIT(5)),
+
[CLK_BUS_I2C0] = GATE(0x594, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x594, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x594, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 8c6043f51e2..4b57434cfaa 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -25,6 +25,8 @@ static struct ccu_clk_gate a83t_gates[] = {
[CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
[CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
+ [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
+
[CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 59afba53eef..08a830bd188 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -14,6 +14,8 @@
#include <linux/bitops.h>
static struct ccu_clk_gate h3_gates[] = {
+ [CLK_PLL_PERIPH0] = GATE(0x028, BIT(31)),
+
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
@@ -30,6 +32,8 @@ static struct ccu_clk_gate h3_gates[] = {
[CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
[CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
+ [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
+
[CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 4a53788352c..f4e26cbcd45 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -14,6 +14,8 @@
#include <linux/bitops.h>
static struct ccu_clk_gate h6_gates[] = {
+ [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31)),
+
[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
index af97d3bb9f7..65ab44643da 100644
--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -13,6 +13,8 @@
#include <linux/bitops.h>
static struct ccu_clk_gate h616_gates[] = {
+ [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31) | BIT(27)),
+
[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index 4d5b69a9765..45633a2a524 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -32,6 +32,8 @@ static struct ccu_clk_gate r40_gates[] = {
[CLK_BUS_GMAC] = GATE(0x064, BIT(17)),
+ [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
+
[CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index cce5c658ca0..67d215cbba8 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -20,6 +20,8 @@ static struct ccu_clk_gate v3s_gates[] = {
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
+ [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
+
[CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
--
2.35.3
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] clk: sunxi: add and use dummy gate clocks
2022-05-06 0:32 [PATCH 0/2] sunxi: clk: fix unhandled clocks warnings Andre Przywara
2022-05-06 0:33 ` [PATCH 1/2] clk: sunxi: add PIO bus gate clocks Andre Przywara
@ 2022-05-06 0:33 ` Andre Przywara
2022-05-09 5:00 ` Samuel Holland
2022-05-24 16:13 ` Andre Przywara
1 sibling, 2 replies; 7+ messages in thread
From: Andre Przywara @ 2022-05-06 0:33 UTC (permalink / raw)
To: Jagan Teki
Cc: Samuel Holland, Jernej Skrabec, Lukasz Majewski, Sean Anderson,
u-boot, linux-sunxi
Some devices enumerate various clocks in their DT, and many drivers
just blanketly try to enable all of them. This creates problems
since we only model a few gate clocks, and the clock driver outputs
a warning when a clock is not described:
=========
sunxi_set_gate: (CLK#3) unhandled
=========
Some clocks don't have an enable bit, or are already enabled in a
different way, so we might want to just ignore them.
Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define
a GATE_DUMMY macro that can be used in the clock description array.
Define a few clocks, used by some pinctrl devices, that way to suppress
the runtime warnings.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/clk/sunxi/clk_h6.c | 2 ++
drivers/clk/sunxi/clk_h616.c | 2 ++
drivers/clk/sunxi/clk_h6_r.c | 2 ++
drivers/clk/sunxi/clk_sunxi.c | 3 +++
include/clk/sunxi.h | 5 +++++
5 files changed, 14 insertions(+)
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index f4e26cbcd45..b3202342932 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -16,6 +16,8 @@
static struct ccu_clk_gate h6_gates[] = {
[CLK_PLL_PERIPH0] = GATE(0x020, BIT(31)),
+ [CLK_APB1] = GATE_DUMMY,
+
[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
index 65ab44643da..80099727def 100644
--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -15,6 +15,8 @@
static struct ccu_clk_gate h616_gates[] = {
[CLK_PLL_PERIPH0] = GATE(0x020, BIT(31) | BIT(27)),
+ [CLK_APB1] = GATE_DUMMY,
+
[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_h6_r.c b/drivers/clk/sunxi/clk_h6_r.c
index 2e0bbaa903b..c592886a258 100644
--- a/drivers/clk/sunxi/clk_h6_r.c
+++ b/drivers/clk/sunxi/clk_h6_r.c
@@ -11,6 +11,8 @@
#include <linux/bitops.h>
static struct ccu_clk_gate h6_r_gates[] = {
+ [CLK_R_APB1] = GATE_DUMMY,
+
[CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)),
[CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)),
[CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)),
diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
index 9673b58a492..9a21367a5d0 100644
--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -27,6 +27,9 @@ static int sunxi_set_gate(struct clk *clk, bool on)
const struct ccu_clk_gate *gate = priv_to_gate(priv, clk->id);
u32 reg;
+ if ((gate->flags & CCU_CLK_F_DUMMY_GATE))
+ return 0;
+
if (!(gate->flags & CCU_CLK_F_IS_VALID)) {
printf("%s: (CLK#%ld) unhandled\n", __func__, clk->id);
return 0;
diff --git a/include/clk/sunxi.h b/include/clk/sunxi.h
index a2239b990b8..c4a9dee5ebf 100644
--- a/include/clk/sunxi.h
+++ b/include/clk/sunxi.h
@@ -18,6 +18,7 @@
enum ccu_flags {
CCU_CLK_F_IS_VALID = BIT(0),
CCU_RST_F_IS_VALID = BIT(1),
+ CCU_CLK_F_DUMMY_GATE = BIT(2),
};
/**
@@ -38,6 +39,10 @@ struct ccu_clk_gate {
.flags = CCU_CLK_F_IS_VALID, \
}
+#define GATE_DUMMY { \
+ .flags = CCU_CLK_F_DUMMY_GATE, \
+}
+
/**
* struct ccu_reset - ccu reset
* @off: reset offset
--
2.35.3
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] clk: sunxi: add PIO bus gate clocks
2022-05-06 0:33 ` [PATCH 1/2] clk: sunxi: add PIO bus gate clocks Andre Przywara
@ 2022-05-07 1:47 ` Samuel Holland
2022-05-24 16:12 ` Andre Przywara
1 sibling, 0 replies; 7+ messages in thread
From: Samuel Holland @ 2022-05-07 1:47 UTC (permalink / raw)
To: Andre Przywara, Jagan Teki
Cc: Jernej Skrabec, Lukasz Majewski, Sean Anderson, u-boot, linux-sunxi
On 5/5/22 7:33 PM, Andre Przywara wrote:
> The introduction of the DM pinctrl driver made its probe function enable
> all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and
> variations) gate clock, but also CLK_PLL_PERIPH0. So far we didn't
I believe the use of CLK_PLL_PERIPH0 is from the R_CCU driver, so it is not
directly related to the introduction of DM pinctrl.
> describe those clocks in our clock driver.
> As we enable them already in the SPL, the devices happen to work, but
> the clock driver still complains about not finding those clocks:
> =========
> sunxi_set_gate: (CLK#58) unhandled
> =========
>
> Add the one-liners that are needed to announce the gate bit for those
> clocks, to silence that message on the console.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] clk: sunxi: add and use dummy gate clocks
2022-05-06 0:33 ` [PATCH 2/2] clk: sunxi: add and use dummy " Andre Przywara
@ 2022-05-09 5:00 ` Samuel Holland
2022-05-24 16:13 ` Andre Przywara
1 sibling, 0 replies; 7+ messages in thread
From: Samuel Holland @ 2022-05-09 5:00 UTC (permalink / raw)
To: Andre Przywara, Jagan Teki
Cc: Jernej Skrabec, Lukasz Majewski, Sean Anderson, u-boot, linux-sunxi
On 5/5/22 7:33 PM, Andre Przywara wrote:
> Some devices enumerate various clocks in their DT, and many drivers
> just blanketly try to enable all of them. This creates problems
> since we only model a few gate clocks, and the clock driver outputs
> a warning when a clock is not described:
> =========
> sunxi_set_gate: (CLK#3) unhandled
> =========
>
> Some clocks don't have an enable bit, or are already enabled in a
> different way, so we might want to just ignore them.
>
> Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define
> a GATE_DUMMY macro that can be used in the clock description array.
> Define a few clocks, used by some pinctrl devices, that way to suppress
> the runtime warnings.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] clk: sunxi: add PIO bus gate clocks
2022-05-06 0:33 ` [PATCH 1/2] clk: sunxi: add PIO bus gate clocks Andre Przywara
2022-05-07 1:47 ` Samuel Holland
@ 2022-05-24 16:12 ` Andre Przywara
1 sibling, 0 replies; 7+ messages in thread
From: Andre Przywara @ 2022-05-24 16:12 UTC (permalink / raw)
To: Jagan Teki
Cc: Samuel Holland, Jernej Skrabec, Lukasz Majewski, Sean Anderson,
u-boot, linux-sunxi
On Fri, 6 May 2022 01:33:00 +0100
Andre Przywara <andre.przywara@arm.com> wrote:
> The introduction of the DM pinctrl driver made its probe function enable
> all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and
> variations) gate clock, but also CLK_PLL_PERIPH0. So far we didn't
> describe those clocks in our clock driver.
> As we enable them already in the SPL, the devices happen to work, but
> the clock driver still complains about not finding those clocks:
> =========
> sunxi_set_gate: (CLK#58) unhandled
> =========
>
> Add the one-liners that are needed to announce the gate bit for those
> clocks, to silence that message on the console.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Applied to sunxi/master.
Thanks,
Andre
> ---
> drivers/clk/sunxi/clk_a10.c | 2 ++
> drivers/clk/sunxi/clk_a10s.c | 2 ++
> drivers/clk/sunxi/clk_a23.c | 2 ++
> drivers/clk/sunxi/clk_a31.c | 2 ++
> drivers/clk/sunxi/clk_a64.c | 4 ++++
> drivers/clk/sunxi/clk_a80.c | 2 ++
> drivers/clk/sunxi/clk_a83t.c | 2 ++
> drivers/clk/sunxi/clk_h3.c | 4 ++++
> drivers/clk/sunxi/clk_h6.c | 2 ++
> drivers/clk/sunxi/clk_h616.c | 2 ++
> drivers/clk/sunxi/clk_r40.c | 2 ++
> drivers/clk/sunxi/clk_v3s.c | 2 ++
> 12 files changed, 28 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
> index 90b929d3d32..db92848aafd 100644
> --- a/drivers/clk/sunxi/clk_a10.c
> +++ b/drivers/clk/sunxi/clk_a10.c
> @@ -31,6 +31,8 @@ static struct ccu_clk_gate a10_gates[] = {
>
> [CLK_AHB_GMAC] = GATE(0x064, BIT(17)),
>
> + [CLK_APB0_PIO] = GATE(0x068, BIT(5)),
> +
> [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
> [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
> index addf4f4d5cd..0c6564ef3b6 100644
> --- a/drivers/clk/sunxi/clk_a10s.c
> +++ b/drivers/clk/sunxi/clk_a10s.c
> @@ -25,6 +25,8 @@ static struct ccu_clk_gate a10s_gates[] = {
> [CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
> [CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
>
> + [CLK_APB0_PIO] = GATE(0x068, BIT(5)),
> +
> [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
> [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
> index c45d2c35298..0280fb51e2d 100644
> --- a/drivers/clk/sunxi/clk_a23.c
> +++ b/drivers/clk/sunxi/clk_a23.c
> @@ -23,6 +23,8 @@ static struct ccu_clk_gate a23_gates[] = {
> [CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
> [CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
>
> + [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
> +
> [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
> index 251fc3b705e..26d25f32408 100644
> --- a/drivers/clk/sunxi/clk_a31.c
> +++ b/drivers/clk/sunxi/clk_a31.c
> @@ -30,6 +30,8 @@ static struct ccu_clk_gate a31_gates[] = {
> [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
> [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
>
> + [CLK_APB1_PIO] = GATE(0x068, BIT(5)),
> +
> [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)),
> [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
> index 1004a795033..cbb9168edb9 100644
> --- a/drivers/clk/sunxi/clk_a64.c
> +++ b/drivers/clk/sunxi/clk_a64.c
> @@ -14,6 +14,8 @@
> #include <linux/bitops.h>
>
> static const struct ccu_clk_gate a64_gates[] = {
> + [CLK_PLL_PERIPH0] = GATE(0x028, BIT(31)),
> +
> [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
> [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
> [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
> @@ -26,6 +28,8 @@ static const struct ccu_clk_gate a64_gates[] = {
> [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
> [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
>
> + [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
> +
> [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
> index 8a0834d83a3..1ee1f99a8f4 100644
> --- a/drivers/clk/sunxi/clk_a80.c
> +++ b/drivers/clk/sunxi/clk_a80.c
> @@ -25,6 +25,8 @@ static const struct ccu_clk_gate a80_gates[] = {
> [CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
> [CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
>
> + [CLK_BUS_PIO] = GATE(0x590, BIT(5)),
> +
> [CLK_BUS_I2C0] = GATE(0x594, BIT(0)),
> [CLK_BUS_I2C1] = GATE(0x594, BIT(1)),
> [CLK_BUS_I2C2] = GATE(0x594, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
> index 8c6043f51e2..4b57434cfaa 100644
> --- a/drivers/clk/sunxi/clk_a83t.c
> +++ b/drivers/clk/sunxi/clk_a83t.c
> @@ -25,6 +25,8 @@ static struct ccu_clk_gate a83t_gates[] = {
> [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
> [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
>
> + [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
> +
> [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
> index 59afba53eef..08a830bd188 100644
> --- a/drivers/clk/sunxi/clk_h3.c
> +++ b/drivers/clk/sunxi/clk_h3.c
> @@ -14,6 +14,8 @@
> #include <linux/bitops.h>
>
> static struct ccu_clk_gate h3_gates[] = {
> + [CLK_PLL_PERIPH0] = GATE(0x028, BIT(31)),
> +
> [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
> [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
> [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
> @@ -30,6 +32,8 @@ static struct ccu_clk_gate h3_gates[] = {
> [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
> [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
>
> + [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
> +
> [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
> index 4a53788352c..f4e26cbcd45 100644
> --- a/drivers/clk/sunxi/clk_h6.c
> +++ b/drivers/clk/sunxi/clk_h6.c
> @@ -14,6 +14,8 @@
> #include <linux/bitops.h>
>
> static struct ccu_clk_gate h6_gates[] = {
> + [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31)),
> +
> [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
> [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
> [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
> index af97d3bb9f7..65ab44643da 100644
> --- a/drivers/clk/sunxi/clk_h616.c
> +++ b/drivers/clk/sunxi/clk_h616.c
> @@ -13,6 +13,8 @@
> #include <linux/bitops.h>
>
> static struct ccu_clk_gate h616_gates[] = {
> + [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31) | BIT(27)),
> +
> [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
> [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
> [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
> index 4d5b69a9765..45633a2a524 100644
> --- a/drivers/clk/sunxi/clk_r40.c
> +++ b/drivers/clk/sunxi/clk_r40.c
> @@ -32,6 +32,8 @@ static struct ccu_clk_gate r40_gates[] = {
>
> [CLK_BUS_GMAC] = GATE(0x064, BIT(17)),
>
> + [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
> +
> [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
> index cce5c658ca0..67d215cbba8 100644
> --- a/drivers/clk/sunxi/clk_v3s.c
> +++ b/drivers/clk/sunxi/clk_v3s.c
> @@ -20,6 +20,8 @@ static struct ccu_clk_gate v3s_gates[] = {
> [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
> [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
>
> + [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
> +
> [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] clk: sunxi: add and use dummy gate clocks
2022-05-06 0:33 ` [PATCH 2/2] clk: sunxi: add and use dummy " Andre Przywara
2022-05-09 5:00 ` Samuel Holland
@ 2022-05-24 16:13 ` Andre Przywara
1 sibling, 0 replies; 7+ messages in thread
From: Andre Przywara @ 2022-05-24 16:13 UTC (permalink / raw)
To: Jagan Teki
Cc: Samuel Holland, Jernej Skrabec, Lukasz Majewski, Sean Anderson,
u-boot, linux-sunxi
On Fri, 6 May 2022 01:33:01 +0100
Andre Przywara <andre.przywara@arm.com> wrote:
> Some devices enumerate various clocks in their DT, and many drivers
> just blanketly try to enable all of them. This creates problems
> since we only model a few gate clocks, and the clock driver outputs
> a warning when a clock is not described:
> =========
> sunxi_set_gate: (CLK#3) unhandled
> =========
>
> Some clocks don't have an enable bit, or are already enabled in a
> different way, so we might want to just ignore them.
>
> Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define
> a GATE_DUMMY macro that can be used in the clock description array.
> Define a few clocks, used by some pinctrl devices, that way to suppress
> the runtime warnings.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Applied to sunxi/master.
Thanks,
Andre
> ---
> drivers/clk/sunxi/clk_h6.c | 2 ++
> drivers/clk/sunxi/clk_h616.c | 2 ++
> drivers/clk/sunxi/clk_h6_r.c | 2 ++
> drivers/clk/sunxi/clk_sunxi.c | 3 +++
> include/clk/sunxi.h | 5 +++++
> 5 files changed, 14 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
> index f4e26cbcd45..b3202342932 100644
> --- a/drivers/clk/sunxi/clk_h6.c
> +++ b/drivers/clk/sunxi/clk_h6.c
> @@ -16,6 +16,8 @@
> static struct ccu_clk_gate h6_gates[] = {
> [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31)),
>
> + [CLK_APB1] = GATE_DUMMY,
> +
> [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
> [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
> [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
> index 65ab44643da..80099727def 100644
> --- a/drivers/clk/sunxi/clk_h616.c
> +++ b/drivers/clk/sunxi/clk_h616.c
> @@ -15,6 +15,8 @@
> static struct ccu_clk_gate h616_gates[] = {
> [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31) | BIT(27)),
>
> + [CLK_APB1] = GATE_DUMMY,
> +
> [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
> [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
> [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_h6_r.c b/drivers/clk/sunxi/clk_h6_r.c
> index 2e0bbaa903b..c592886a258 100644
> --- a/drivers/clk/sunxi/clk_h6_r.c
> +++ b/drivers/clk/sunxi/clk_h6_r.c
> @@ -11,6 +11,8 @@
> #include <linux/bitops.h>
>
> static struct ccu_clk_gate h6_r_gates[] = {
> + [CLK_R_APB1] = GATE_DUMMY,
> +
> [CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)),
> [CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)),
> [CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)),
> diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
> index 9673b58a492..9a21367a5d0 100644
> --- a/drivers/clk/sunxi/clk_sunxi.c
> +++ b/drivers/clk/sunxi/clk_sunxi.c
> @@ -27,6 +27,9 @@ static int sunxi_set_gate(struct clk *clk, bool on)
> const struct ccu_clk_gate *gate = priv_to_gate(priv, clk->id);
> u32 reg;
>
> + if ((gate->flags & CCU_CLK_F_DUMMY_GATE))
> + return 0;
> +
> if (!(gate->flags & CCU_CLK_F_IS_VALID)) {
> printf("%s: (CLK#%ld) unhandled\n", __func__, clk->id);
> return 0;
> diff --git a/include/clk/sunxi.h b/include/clk/sunxi.h
> index a2239b990b8..c4a9dee5ebf 100644
> --- a/include/clk/sunxi.h
> +++ b/include/clk/sunxi.h
> @@ -18,6 +18,7 @@
> enum ccu_flags {
> CCU_CLK_F_IS_VALID = BIT(0),
> CCU_RST_F_IS_VALID = BIT(1),
> + CCU_CLK_F_DUMMY_GATE = BIT(2),
> };
>
> /**
> @@ -38,6 +39,10 @@ struct ccu_clk_gate {
> .flags = CCU_CLK_F_IS_VALID, \
> }
>
> +#define GATE_DUMMY { \
> + .flags = CCU_CLK_F_DUMMY_GATE, \
> +}
> +
> /**
> * struct ccu_reset - ccu reset
> * @off: reset offset
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-05-24 16:17 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-06 0:32 [PATCH 0/2] sunxi: clk: fix unhandled clocks warnings Andre Przywara
2022-05-06 0:33 ` [PATCH 1/2] clk: sunxi: add PIO bus gate clocks Andre Przywara
2022-05-07 1:47 ` Samuel Holland
2022-05-24 16:12 ` Andre Przywara
2022-05-06 0:33 ` [PATCH 2/2] clk: sunxi: add and use dummy " Andre Przywara
2022-05-09 5:00 ` Samuel Holland
2022-05-24 16:13 ` Andre Przywara
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