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From: Shuai Xue <xueshuai@linux.alibaba.com>
To: Baolin Wang <baolin.wang@linux.alibaba.com>,
	chengyou@linux.alibaba.com, kaishen@linux.alibaba.com,
	helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org,
	Jonathan.Cameron@huawei.com, robin.murphy@arm.com
Cc: linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
	rdunlap@infradead.org, mark.rutland@arm.com,
	zhuo.song@linux.alibaba.com
Subject: Re: [PATCH v5 3/4] drivers/perf: add DesignWare PCIe PMU driver
Date: Mon, 29 May 2023 14:33:20 +0800	[thread overview]
Message-ID: <1a1af428-0794-514d-1d79-52e3796a0707@linux.alibaba.com> (raw)
In-Reply-To: <505a5d3a-c970-8d15-ea60-444a3630c199@linux.alibaba.com>



On 2023/5/29 14:13, Baolin Wang wrote:
> 
> 
> On 5/22/2023 11:54 AM, Shuai Xue wrote:
>> This commit adds the PCIe Performance Monitoring Unit (PMU) driver support
>> for T-Head Yitian SoC chip. Yitian is based on the Synopsys PCI Express
>> Core controller IP which provides statistics feature. The PMU is not a PCIe
>> Root Complex integrated End Point(RCiEP) device but only register counters
>> provided by each PCIe Root Port.
>>
>> To facilitate collection of statistics the controller provides the
>> following two features for each Root Port:
>>
>> - Time Based Analysis (RX/TX data throughput and time spent in each
>>    low-power LTSSM state)
>> - Event counters (Error and Non-Error for lanes)
>>
>> Note, only one counter for each type and does not overflow interrupt.
>>
>> This driver adds PMU devices for each PCIe Root Port. And the PMU device is
>> named based the BDF of Root Port. For example,
>>
>>      30:03.0 PCI bridge: Device 1ded:8000 (rev 01)
>>
>> the PMU device name for this Root Port is dwc_rootport_3018.
>>
>> Example usage of counting PCIe RX TLP data payload (Units of 16 bytes)::
>>
>>      $# perf stat -a -e dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/
>>
>> average RX bandwidth can be calculated like this:
>>
>>      PCIe TX Bandwidth = PCIE_TX_DATA * 16B / Measure_Time_Window
>>
>> Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com>
>> Reported-by: kernel test robot <lkp@intel.com>
>> Link: https://lore.kernel.org/oe-kbuild-all/202305170639.XU3djFZX-lkp@intel.com/
>> ---
> 
> [snip]
> 
>> +static int dwc_pcie_pmu_remove(struct platform_device *pdev)
>> +{
>> +    struct dwc_pcie_pmu_priv *priv = platform_get_drvdata(pdev);
>> +    struct dwc_pcie_pmu *pcie_pmu;
>> +
>> +    list_for_each_entry(pcie_pmu, &priv->pmu_nodes, pmu_node) {
>> +        cpuhp_state_remove_instance(dwc_pcie_pmu_hp_state,
>> +                        &pcie_pmu->cpuhp_node);
>> +        perf_pmu_unregister(&pcie_pmu->pmu);
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>> +static int dwc_pcie_pmu_probe(struct platform_device *pdev)
>> +{
>> +    struct dwc_pcie_pmu_priv *priv;
>> +
>> +    priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
>> +    if (!priv)
>> +        return -ENOMEM;
>> +
>> +    priv->dev = &pdev->dev;
>> +    platform_set_drvdata(pdev, priv);
>> +
>> +    /* If one PMU registration fails, remove all. */
>> +    if (__dwc_pcie_pmu_probe(priv))
>> +        dwc_pcie_pmu_remove(pdev);
> 
> In this case, you should return error from __dwc_pcie_pmu_probe() instead of returning 0, to release the requested resources of the PMU deivce.

You are right, will fix it in next version.

> 
>> +
>> +    return 0;
>> +}
>> +
>> +static void dwc_pcie_pmu_migrate(struct dwc_pcie_pmu *pcie_pmu, unsigned int cpu)
>> +{
>> +    /* This PMU does NOT support interrupt, just migrate context. */
>> +    perf_pmu_migrate_context(&pcie_pmu->pmu, pcie_pmu->oncpu, cpu);
>> +    pcie_pmu->oncpu = cpu;
>> +}
>> +
>> +static int dwc_pcie_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
>> +{
>> +    struct dwc_pcie_pmu *pcie_pmu;
>> +    struct pci_dev *pdev;
>> +    int node;
>> +
>> +    pcie_pmu = hlist_entry_safe(cpuhp_node, struct dwc_pcie_pmu, cpuhp_node);
>> +    pdev = pcie_pmu->pdev;
>> +    node = dev_to_node(&pdev->dev);
>> +
>> +    if (node != NUMA_NO_NODE && cpu_to_node(pcie_pmu->oncpu) != node &&
>> +        cpu_to_node(cpu) == node)
>> +        dwc_pcie_pmu_migrate(pcie_pmu, cpu);
>> +
>> +    return 0;
>> +}
>> +
>> +static int dwc_pcie_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
>> +{
>> +    struct dwc_pcie_pmu *pcie_pmu;
>> +    struct pci_dev *pdev;
>> +    int node;
>> +    cpumask_t mask;
>> +    unsigned int target;
>> +
>> +    pcie_pmu = hlist_entry_safe(cpuhp_node, struct dwc_pcie_pmu, cpuhp_node);
>> +    if (cpu != pcie_pmu->oncpu)
>> +        return 0;
>> +
>> +    pdev = pcie_pmu->pdev;
>> +    node = dev_to_node(&pdev->dev);
>> +    if (cpumask_and(&mask, cpumask_of_node(node), cpu_online_mask) &&
>> +        cpumask_andnot(&mask, &mask, cpumask_of(cpu)))
>> +        target = cpumask_any(&mask);
>> +    else
>> +        target = cpumask_any_but(cpu_online_mask, cpu);
>> +    if (target < nr_cpu_ids)
>> +        dwc_pcie_pmu_migrate(pcie_pmu, target);
>> +
>> +    return 0;
>> +}
>> +
>> +static struct platform_driver dwc_pcie_pmu_driver = {
>> +    .probe = dwc_pcie_pmu_probe,
>> +    .remove = dwc_pcie_pmu_remove,
>> +    .driver = {.name = "dwc_pcie_pmu",},
>> +};
>> +
>> +static int __init dwc_pcie_pmu_init(void)
>> +{
>> +    int ret;
>> +
>> +    ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
>> +                      "perf/dwc_pcie_pmu:online",
>> +                      dwc_pcie_pmu_online_cpu,
>> +                      dwc_pcie_pmu_offline_cpu);
>> +    if (ret < 0)
>> +        return ret;
>> +
>> +    dwc_pcie_pmu_hp_state = ret;
>> +
>> +    ret = platform_driver_register(&dwc_pcie_pmu_driver);
>> +    if (ret) {
>> +        cpuhp_remove_multi_state(dwc_pcie_pmu_hp_state);
>> +        return ret;
>> +    }
>> +
>> +    dwc_pcie_pmu_dev = platform_device_register_simple(
>> +                "dwc_pcie_pmu", PLATFORM_DEVID_NONE, NULL, 0);
>> +    if (IS_ERR(dwc_pcie_pmu_dev)) {
>> +        platform_driver_unregister(&dwc_pcie_pmu_driver);
>> +        return PTR_ERR(dwc_pcie_pmu_dev);
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>> +static void __exit dwc_pcie_pmu_exit(void)
>> +{
>> +    platform_device_unregister(dwc_pcie_pmu_dev);
>> +    platform_driver_unregister(&dwc_pcie_pmu_driver);
> 
> You should also call 'cpuhp_remove_multi_state()' when exiting the driver.

Good catch, will add it in next version.


> 
> With above issues fixed, you can add:
> Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>

Thank you :)

Best Regards,
Shuai

WARNING: multiple messages have this Message-ID (diff)
From: Shuai Xue <xueshuai@linux.alibaba.com>
To: Baolin Wang <baolin.wang@linux.alibaba.com>,
	chengyou@linux.alibaba.com, kaishen@linux.alibaba.com,
	helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org,
	Jonathan.Cameron@huawei.com, robin.murphy@arm.com
Cc: linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
	rdunlap@infradead.org, mark.rutland@arm.com,
	zhuo.song@linux.alibaba.com
Subject: Re: [PATCH v5 3/4] drivers/perf: add DesignWare PCIe PMU driver
Date: Mon, 29 May 2023 14:33:20 +0800	[thread overview]
Message-ID: <1a1af428-0794-514d-1d79-52e3796a0707@linux.alibaba.com> (raw)
In-Reply-To: <505a5d3a-c970-8d15-ea60-444a3630c199@linux.alibaba.com>



On 2023/5/29 14:13, Baolin Wang wrote:
> 
> 
> On 5/22/2023 11:54 AM, Shuai Xue wrote:
>> This commit adds the PCIe Performance Monitoring Unit (PMU) driver support
>> for T-Head Yitian SoC chip. Yitian is based on the Synopsys PCI Express
>> Core controller IP which provides statistics feature. The PMU is not a PCIe
>> Root Complex integrated End Point(RCiEP) device but only register counters
>> provided by each PCIe Root Port.
>>
>> To facilitate collection of statistics the controller provides the
>> following two features for each Root Port:
>>
>> - Time Based Analysis (RX/TX data throughput and time spent in each
>>    low-power LTSSM state)
>> - Event counters (Error and Non-Error for lanes)
>>
>> Note, only one counter for each type and does not overflow interrupt.
>>
>> This driver adds PMU devices for each PCIe Root Port. And the PMU device is
>> named based the BDF of Root Port. For example,
>>
>>      30:03.0 PCI bridge: Device 1ded:8000 (rev 01)
>>
>> the PMU device name for this Root Port is dwc_rootport_3018.
>>
>> Example usage of counting PCIe RX TLP data payload (Units of 16 bytes)::
>>
>>      $# perf stat -a -e dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/
>>
>> average RX bandwidth can be calculated like this:
>>
>>      PCIe TX Bandwidth = PCIE_TX_DATA * 16B / Measure_Time_Window
>>
>> Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com>
>> Reported-by: kernel test robot <lkp@intel.com>
>> Link: https://lore.kernel.org/oe-kbuild-all/202305170639.XU3djFZX-lkp@intel.com/
>> ---
> 
> [snip]
> 
>> +static int dwc_pcie_pmu_remove(struct platform_device *pdev)
>> +{
>> +    struct dwc_pcie_pmu_priv *priv = platform_get_drvdata(pdev);
>> +    struct dwc_pcie_pmu *pcie_pmu;
>> +
>> +    list_for_each_entry(pcie_pmu, &priv->pmu_nodes, pmu_node) {
>> +        cpuhp_state_remove_instance(dwc_pcie_pmu_hp_state,
>> +                        &pcie_pmu->cpuhp_node);
>> +        perf_pmu_unregister(&pcie_pmu->pmu);
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>> +static int dwc_pcie_pmu_probe(struct platform_device *pdev)
>> +{
>> +    struct dwc_pcie_pmu_priv *priv;
>> +
>> +    priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
>> +    if (!priv)
>> +        return -ENOMEM;
>> +
>> +    priv->dev = &pdev->dev;
>> +    platform_set_drvdata(pdev, priv);
>> +
>> +    /* If one PMU registration fails, remove all. */
>> +    if (__dwc_pcie_pmu_probe(priv))
>> +        dwc_pcie_pmu_remove(pdev);
> 
> In this case, you should return error from __dwc_pcie_pmu_probe() instead of returning 0, to release the requested resources of the PMU deivce.

You are right, will fix it in next version.

> 
>> +
>> +    return 0;
>> +}
>> +
>> +static void dwc_pcie_pmu_migrate(struct dwc_pcie_pmu *pcie_pmu, unsigned int cpu)
>> +{
>> +    /* This PMU does NOT support interrupt, just migrate context. */
>> +    perf_pmu_migrate_context(&pcie_pmu->pmu, pcie_pmu->oncpu, cpu);
>> +    pcie_pmu->oncpu = cpu;
>> +}
>> +
>> +static int dwc_pcie_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
>> +{
>> +    struct dwc_pcie_pmu *pcie_pmu;
>> +    struct pci_dev *pdev;
>> +    int node;
>> +
>> +    pcie_pmu = hlist_entry_safe(cpuhp_node, struct dwc_pcie_pmu, cpuhp_node);
>> +    pdev = pcie_pmu->pdev;
>> +    node = dev_to_node(&pdev->dev);
>> +
>> +    if (node != NUMA_NO_NODE && cpu_to_node(pcie_pmu->oncpu) != node &&
>> +        cpu_to_node(cpu) == node)
>> +        dwc_pcie_pmu_migrate(pcie_pmu, cpu);
>> +
>> +    return 0;
>> +}
>> +
>> +static int dwc_pcie_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
>> +{
>> +    struct dwc_pcie_pmu *pcie_pmu;
>> +    struct pci_dev *pdev;
>> +    int node;
>> +    cpumask_t mask;
>> +    unsigned int target;
>> +
>> +    pcie_pmu = hlist_entry_safe(cpuhp_node, struct dwc_pcie_pmu, cpuhp_node);
>> +    if (cpu != pcie_pmu->oncpu)
>> +        return 0;
>> +
>> +    pdev = pcie_pmu->pdev;
>> +    node = dev_to_node(&pdev->dev);
>> +    if (cpumask_and(&mask, cpumask_of_node(node), cpu_online_mask) &&
>> +        cpumask_andnot(&mask, &mask, cpumask_of(cpu)))
>> +        target = cpumask_any(&mask);
>> +    else
>> +        target = cpumask_any_but(cpu_online_mask, cpu);
>> +    if (target < nr_cpu_ids)
>> +        dwc_pcie_pmu_migrate(pcie_pmu, target);
>> +
>> +    return 0;
>> +}
>> +
>> +static struct platform_driver dwc_pcie_pmu_driver = {
>> +    .probe = dwc_pcie_pmu_probe,
>> +    .remove = dwc_pcie_pmu_remove,
>> +    .driver = {.name = "dwc_pcie_pmu",},
>> +};
>> +
>> +static int __init dwc_pcie_pmu_init(void)
>> +{
>> +    int ret;
>> +
>> +    ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
>> +                      "perf/dwc_pcie_pmu:online",
>> +                      dwc_pcie_pmu_online_cpu,
>> +                      dwc_pcie_pmu_offline_cpu);
>> +    if (ret < 0)
>> +        return ret;
>> +
>> +    dwc_pcie_pmu_hp_state = ret;
>> +
>> +    ret = platform_driver_register(&dwc_pcie_pmu_driver);
>> +    if (ret) {
>> +        cpuhp_remove_multi_state(dwc_pcie_pmu_hp_state);
>> +        return ret;
>> +    }
>> +
>> +    dwc_pcie_pmu_dev = platform_device_register_simple(
>> +                "dwc_pcie_pmu", PLATFORM_DEVID_NONE, NULL, 0);
>> +    if (IS_ERR(dwc_pcie_pmu_dev)) {
>> +        platform_driver_unregister(&dwc_pcie_pmu_driver);
>> +        return PTR_ERR(dwc_pcie_pmu_dev);
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>> +static void __exit dwc_pcie_pmu_exit(void)
>> +{
>> +    platform_device_unregister(dwc_pcie_pmu_dev);
>> +    platform_driver_unregister(&dwc_pcie_pmu_driver);
> 
> You should also call 'cpuhp_remove_multi_state()' when exiting the driver.

Good catch, will add it in next version.


> 
> With above issues fixed, you can add:
> Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>

Thank you :)

Best Regards,
Shuai

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  reply	other threads:[~2023-05-29  6:33 UTC|newest]

Thread overview: 158+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-17 12:10 [PATCH v1 0/3] drivers/perf: add Synopsys DesignWare PCIe PMU driver support Shuai Xue
2022-09-17 12:10 ` Shuai Xue
2022-09-17 12:10 ` [PATCH v1 1/3] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Shuai Xue
2022-09-17 12:10   ` Shuai Xue
2022-09-22 13:25   ` Will Deacon
2022-09-22 13:25     ` Will Deacon
2022-09-23 13:51     ` Shuai Xue
2022-09-23 13:51       ` Shuai Xue
2022-11-07 15:28       ` Will Deacon
2022-11-07 15:28         ` Will Deacon
2022-09-23  1:27   ` Yicong Yang
2022-09-23  1:27     ` Yicong Yang
2022-09-23 14:47     ` Shuai Xue
2022-09-23 14:47       ` Shuai Xue
2022-09-17 12:10 ` [PATCH v1 2/3] drivers/perf: add " Shuai Xue
2022-09-17 12:10   ` Shuai Xue
2022-09-22 15:58   ` Jonathan Cameron
2022-09-22 15:58     ` Jonathan Cameron
2022-09-22 17:32     ` Bjorn Helgaas
2022-09-22 17:32       ` Bjorn Helgaas
2022-09-23  3:35       ` Yicong Yang
2022-09-23  3:35         ` Yicong Yang
2022-09-23 10:56         ` Jonathan Cameron
2022-09-23 10:56           ` Jonathan Cameron
2022-09-23 13:45     ` Shuai Xue
2022-09-23 13:45       ` Shuai Xue
2022-09-23 15:54       ` Jonathan Cameron
2022-09-23 15:54         ` Jonathan Cameron
2022-09-26 13:31         ` Shuai Xue
2022-09-26 13:31           ` Shuai Xue
2022-09-26 14:32           ` Robin Murphy
2022-09-26 14:32             ` Robin Murphy
2022-09-26 17:18           ` Bjorn Helgaas
2022-09-26 17:18             ` Bjorn Helgaas
2022-09-27  5:13             ` Shuai Xue
2022-09-27  5:13               ` Shuai Xue
2022-09-27 10:04               ` Jonathan Cameron
2022-09-27 10:04                 ` Jonathan Cameron
2022-09-27 10:14                 ` Robin Murphy
2022-09-27 10:14                   ` Robin Murphy
2022-09-27 12:49                   ` Shuai Xue
2022-09-27 12:49                     ` Shuai Xue
2022-09-27 13:39                     ` Jonathan Cameron
2022-09-27 13:39                       ` Jonathan Cameron
2022-09-27 12:29                 ` Shuai Xue
2022-09-27 12:29                   ` Shuai Xue
2022-09-27 10:03             ` Jonathan Cameron
2022-09-27 10:03               ` Jonathan Cameron
2022-09-22 17:36   ` Bjorn Helgaas
2022-09-22 17:36     ` Bjorn Helgaas
2022-09-23 14:46     ` Shuai Xue
2022-09-23 14:46       ` Shuai Xue
2022-09-23 18:51       ` Bjorn Helgaas
2022-09-23 18:51         ` Bjorn Helgaas
2022-09-27  6:01         ` Shuai Xue
2022-09-27  6:01           ` Shuai Xue
2022-09-23  3:30   ` Yicong Yang
2022-09-23  3:30     ` Yicong Yang
2022-09-23 15:43     ` Shuai Xue
2022-09-23 15:43       ` Shuai Xue
2022-09-24  8:00       ` Yicong Yang
2022-09-24  8:00         ` Yicong Yang
2022-09-26 11:39         ` Shuai Xue
2022-09-26 11:39           ` Shuai Xue
2022-09-17 12:10 ` [PATCH v1 3/3] MAINTAINERS: add maintainers for " Shuai Xue
2022-09-17 12:10   ` Shuai Xue
2023-04-10  3:16 ` [PATCH v2 0/3] drivers/perf: add Synopsys DesignWare PCIe PMU driver support Shuai Xue
2023-04-10  3:16   ` Shuai Xue
2023-04-10  3:17 ` [PATCH v2 1/3] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Shuai Xue
2023-04-10  3:17   ` Shuai Xue
2023-04-10  3:17 ` [PATCH v2 2/3] drivers/perf: add " Shuai Xue
2023-04-10  3:17   ` Shuai Xue
2023-04-10  7:25   ` kernel test robot
2023-04-10  7:25     ` kernel test robot
2023-04-11  3:17   ` Baolin Wang
2023-04-11  3:17     ` Baolin Wang
2023-04-17  1:16     ` Shuai Xue
2023-04-17  1:16       ` Shuai Xue
2023-04-18  1:51       ` Baolin Wang
2023-04-18  1:51         ` Baolin Wang
2023-04-19  1:39         ` Shuai Xue
2023-04-19  1:39           ` Shuai Xue
2023-04-10  3:17 ` [PATCH v2 3/3] MAINTAINERS: add maintainers for " Shuai Xue
2023-04-10  3:17   ` Shuai Xue
2023-04-17  6:17 ` [PATCH v3 0/3] drivers/perf: add Synopsys DesignWare PCIe PMU driver support Shuai Xue
2023-04-17  6:17   ` Shuai Xue
2023-04-17  6:17 ` [PATCH v3 1/3] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Shuai Xue
2023-04-17  6:17   ` Shuai Xue
2023-05-16 14:32   ` Jonathan Cameron
2023-05-16 14:32     ` Jonathan Cameron
2023-05-17  1:27     ` Shuai Xue
2023-05-17  1:27       ` Shuai Xue
2023-04-17  6:17 ` [PATCH v3 2/3] drivers/perf: add " Shuai Xue
2023-04-17  6:17   ` Shuai Xue
2023-04-18 23:30   ` Robin Murphy
2023-04-18 23:30     ` Robin Murphy
2023-04-27  6:33     ` Shuai Xue
2023-04-27  6:33       ` Shuai Xue
2023-05-09  2:02       ` Shuai Xue
2023-05-16 15:03       ` Jonathan Cameron
2023-05-16 15:03         ` Jonathan Cameron
2023-05-16 19:17         ` Bjorn Helgaas
2023-05-16 19:17           ` Bjorn Helgaas
2023-05-17  9:54           ` Jonathan Cameron
2023-05-17  9:54             ` Jonathan Cameron
2023-05-17 16:27             ` Bjorn Helgaas
2023-05-17 16:27               ` Bjorn Helgaas
2023-05-19 10:08               ` Shuai Xue
2023-05-19 10:08                 ` Shuai Xue
2023-04-17  6:17 ` [PATCH v3 3/3] MAINTAINERS: add maintainers for " Shuai Xue
2023-04-17  6:17   ` Shuai Xue
2023-05-16 13:01 ` [PATCH v4 0/4] drivers/perf: add Synopsys DesignWare PCIe PMU driver support Shuai Xue
2023-05-16 13:01   ` Shuai Xue
2023-05-16 13:01 ` [PATCH v4 1/4] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Shuai Xue
2023-05-16 13:01   ` Shuai Xue
2023-05-16 13:01 ` [PATCH v4 2/4] PCI: move Alibaba Vendor ID linux/pci_ids.h Shuai Xue
2023-05-16 13:01   ` Shuai Xue
2023-05-16 13:01 ` [PATCH v4 3/4] drivers/perf: add DesignWare PCIe PMU driver Shuai Xue
2023-05-16 13:01   ` Shuai Xue
2023-05-16 19:19   ` Bjorn Helgaas
2023-05-16 19:19     ` Bjorn Helgaas
2023-05-17  2:35     ` Shuai Xue
2023-05-17  2:35       ` Shuai Xue
2023-05-16 23:21   ` kernel test robot
2023-05-17  3:37     ` Shuai Xue
2023-05-17  3:37       ` Shuai Xue
2023-05-16 13:01 ` [PATCH v4 4/4] MAINTAINERS: add maintainers for " Shuai Xue
2023-05-16 13:01   ` Shuai Xue
2023-05-22  3:54 ` [PATCH v5 0/4] drivers/perf: add Synopsys DesignWare PCIe PMU driver support Shuai Xue
2023-05-22  3:54   ` Shuai Xue
2023-05-22 14:28   ` Jonathan Cameron
2023-05-22 14:28     ` Jonathan Cameron
2023-05-23  2:57     ` Shuai Xue
2023-05-23  2:57       ` Shuai Xue
2023-05-22  3:54 ` [PATCH v5 1/4] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Shuai Xue
2023-05-22  3:54   ` Shuai Xue
2023-05-29  3:45   ` Baolin Wang
2023-05-29  3:45     ` Baolin Wang
2023-05-29  6:31     ` Shuai Xue
2023-05-29  6:31       ` Shuai Xue
2023-05-22  3:54 ` [PATCH v5 2/4] PCI: move Alibaba Vendor ID linux/pci_ids.h Shuai Xue
2023-05-22  3:54   ` Shuai Xue
2023-05-22 16:04   ` Bjorn Helgaas
2023-05-22 16:04     ` Bjorn Helgaas
2023-05-23  3:22     ` Shuai Xue
2023-05-23  3:22       ` Shuai Xue
2023-05-23 11:54       ` Bjorn Helgaas
2023-05-23 11:54         ` Bjorn Helgaas
2023-05-23 12:49         ` Shuai Xue
2023-05-23 12:49           ` Shuai Xue
2023-05-22  3:54 ` [PATCH v5 3/4] drivers/perf: add DesignWare PCIe PMU driver Shuai Xue
2023-05-22  3:54   ` Shuai Xue
2023-05-29  6:13   ` Baolin Wang
2023-05-29  6:13     ` Baolin Wang
2023-05-29  6:33     ` Shuai Xue [this message]
2023-05-29  6:33       ` Shuai Xue
2023-05-22  3:54 ` [PATCH v5 4/4] MAINTAINERS: add maintainers for " Shuai Xue
2023-05-22  3:54   ` Shuai Xue

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