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From: Will Deacon <will@kernel.org>
To: Shuai Xue <xueshuai@linux.alibaba.com>
Cc: Jonathan.Cameron@Huawei.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, rdunlap@infradead.org,
	robin.murphy@arm.com, mark.rutland@arm.com,
	baolin.wang@linux.alibaba.com, zhuo.song@linux.alibaba.com
Subject: Re: [PATCH v1 1/3] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver
Date: Mon, 7 Nov 2022 15:28:10 +0000	[thread overview]
Message-ID: <20221107152809.GE21002@willie-the-truck> (raw)
In-Reply-To: <a01eae44-5daf-08bb-ea28-eeacd7006ab9@linux.alibaba.com>

On Fri, Sep 23, 2022 at 09:51:40PM +0800, Shuai Xue wrote:
> 
> 
> 在 2022/9/22 PM9:25, Will Deacon 写道:
> > On Sat, Sep 17, 2022 at 08:10:34PM +0800, Shuai Xue wrote:
> >> Alibaba's T-Head Yitan 710 SoC is built on Synopsys' widely deployed and
> >> silicon-proven DesignWare Core PCIe controller which implements PMU for
> >> performance and functional debugging to facilitate system maintenance.
> >> Document it to provide guidance on how to use it.
> >>
> >> Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com>
> >> ---
> >>  .../admin-guide/perf/dwc_pcie_pmu.rst         | 61 +++++++++++++++++++
> >>  Documentation/admin-guide/perf/index.rst      |  1 +
> >>  2 files changed, 62 insertions(+)
> >>  create mode 100644 Documentation/admin-guide/perf/dwc_pcie_pmu.rst
> >>
> >> diff --git a/Documentation/admin-guide/perf/dwc_pcie_pmu.rst b/Documentation/admin-guide/perf/dwc_pcie_pmu.rst
> >> new file mode 100644
> >> index 000000000000..fbcbf10b23b7
> >> --- /dev/null
> >> +++ b/Documentation/admin-guide/perf/dwc_pcie_pmu.rst
> >> @@ -0,0 +1,61 @@
> >> +======================================================================
> >> +Synopsys DesignWare Cores (DWC) PCIe Performance Monitoring Unit (PMU)
> >> +======================================================================
> >> +
> >> +DesignWare Cores (DWC) PCIe PMU
> >> +===============================
> >> +
> >> +To facilitate collection of statistics, Synopsys DesignWare Cores PCIe
> >> +controller provides the following two features:
> >> +
> >> +- Time Based Analysis (RX/TX data throughput and time spent in each
> >> +  low-power LTSSM state)
> >> +- Lane Event counters (Error and Non-Error for lanes)
> >> +
> >> +The PMU is not a PCIe Root Complex integrated End Point (RCiEP) device but
> >> +only register counters provided by each PCIe Root Port.
> >> +
> >> +Time Based Analysis
> >> +-------------------
> >> +
> >> +Using this feature you can obtain information regarding RX/TX data
> >> +throughput and time spent in each low-power LTSSM state by the controller.
> >> +
> >> +The counters are 64-bit width and measure data in two categories,
> >> +
> >> +- percentage of time does the controller stay in LTSSM state in a
> >> +  configurable duration. The measurement range of each Event in Group#0.
> >> +- amount of data processed (Units of 16 bytes). The measurement range of
> >> +  each Event in Group#1.
> >> +
> >> +Lane Event counters
> >> +-------------------
> >> +
> >> +Using this feature you can obtain Error and Non-Error information in
> >> +specific lane by the controller.
> >> +
> >> +The counters are 32-bit width and the measured event is select by:
> >> +
> >> +- Group i
> >> +- Event j within the Group i
> >> +- and Lank k
> >> +
> >> +Some of the event counters only exist for specific configurations.
> >> +
> >> +DesignWare Cores (DWC) PCIe PMU Driver
> >> +=======================================
> >> +
> >> +This driver add PMU devices for each PCIe Root Port. And the PMU device is
> >> +named based the BDF of Root Port. For example,
> >> +
> >> +    10:00.0 PCI bridge: Device 1ded:8000 (rev 01)
> >> +
> >> +the PMU device name for this Root Port is pcie_bdf_100000.
> >> +
> >> +Example usage of counting PCIe RX TLP data payload (Units of 16 bytes)::
> >> +
> >> +    $# perf stat -a -e pcie_bdf_200/Rx_PCIe_TLP_Data_Payload/
> > 
> > Do you really need to expose a separate PMU instance to userspace for each
> > BDF? I think it would be much cleaner if you could follow the approach used
> > by hisilicon/hisi_pcie_pmu.c and hide these details in the driver, exposing
> > a `bdf=' selector to userspace instead.
> 
> Thank you for your valuable comments.
> 
> It's a good idea to encode bdf in bitmap and exposing a `bdf=' selector to userspace.
> The problem of bdf selector is that the user need to compute bdf from lanes, do you
> think it is user friendly? I'm worried about increasing the burden of users.

I don't see this as being an issue, particularly if you document how to do
it.

Will

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Shuai Xue <xueshuai@linux.alibaba.com>
Cc: Jonathan.Cameron@Huawei.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, rdunlap@infradead.org,
	robin.murphy@arm.com, mark.rutland@arm.com,
	baolin.wang@linux.alibaba.com, zhuo.song@linux.alibaba.com
Subject: Re: [PATCH v1 1/3] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver
Date: Mon, 7 Nov 2022 15:28:10 +0000	[thread overview]
Message-ID: <20221107152809.GE21002@willie-the-truck> (raw)
In-Reply-To: <a01eae44-5daf-08bb-ea28-eeacd7006ab9@linux.alibaba.com>

On Fri, Sep 23, 2022 at 09:51:40PM +0800, Shuai Xue wrote:
> 
> 
> 在 2022/9/22 PM9:25, Will Deacon 写道:
> > On Sat, Sep 17, 2022 at 08:10:34PM +0800, Shuai Xue wrote:
> >> Alibaba's T-Head Yitan 710 SoC is built on Synopsys' widely deployed and
> >> silicon-proven DesignWare Core PCIe controller which implements PMU for
> >> performance and functional debugging to facilitate system maintenance.
> >> Document it to provide guidance on how to use it.
> >>
> >> Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com>
> >> ---
> >>  .../admin-guide/perf/dwc_pcie_pmu.rst         | 61 +++++++++++++++++++
> >>  Documentation/admin-guide/perf/index.rst      |  1 +
> >>  2 files changed, 62 insertions(+)
> >>  create mode 100644 Documentation/admin-guide/perf/dwc_pcie_pmu.rst
> >>
> >> diff --git a/Documentation/admin-guide/perf/dwc_pcie_pmu.rst b/Documentation/admin-guide/perf/dwc_pcie_pmu.rst
> >> new file mode 100644
> >> index 000000000000..fbcbf10b23b7
> >> --- /dev/null
> >> +++ b/Documentation/admin-guide/perf/dwc_pcie_pmu.rst
> >> @@ -0,0 +1,61 @@
> >> +======================================================================
> >> +Synopsys DesignWare Cores (DWC) PCIe Performance Monitoring Unit (PMU)
> >> +======================================================================
> >> +
> >> +DesignWare Cores (DWC) PCIe PMU
> >> +===============================
> >> +
> >> +To facilitate collection of statistics, Synopsys DesignWare Cores PCIe
> >> +controller provides the following two features:
> >> +
> >> +- Time Based Analysis (RX/TX data throughput and time spent in each
> >> +  low-power LTSSM state)
> >> +- Lane Event counters (Error and Non-Error for lanes)
> >> +
> >> +The PMU is not a PCIe Root Complex integrated End Point (RCiEP) device but
> >> +only register counters provided by each PCIe Root Port.
> >> +
> >> +Time Based Analysis
> >> +-------------------
> >> +
> >> +Using this feature you can obtain information regarding RX/TX data
> >> +throughput and time spent in each low-power LTSSM state by the controller.
> >> +
> >> +The counters are 64-bit width and measure data in two categories,
> >> +
> >> +- percentage of time does the controller stay in LTSSM state in a
> >> +  configurable duration. The measurement range of each Event in Group#0.
> >> +- amount of data processed (Units of 16 bytes). The measurement range of
> >> +  each Event in Group#1.
> >> +
> >> +Lane Event counters
> >> +-------------------
> >> +
> >> +Using this feature you can obtain Error and Non-Error information in
> >> +specific lane by the controller.
> >> +
> >> +The counters are 32-bit width and the measured event is select by:
> >> +
> >> +- Group i
> >> +- Event j within the Group i
> >> +- and Lank k
> >> +
> >> +Some of the event counters only exist for specific configurations.
> >> +
> >> +DesignWare Cores (DWC) PCIe PMU Driver
> >> +=======================================
> >> +
> >> +This driver add PMU devices for each PCIe Root Port. And the PMU device is
> >> +named based the BDF of Root Port. For example,
> >> +
> >> +    10:00.0 PCI bridge: Device 1ded:8000 (rev 01)
> >> +
> >> +the PMU device name for this Root Port is pcie_bdf_100000.
> >> +
> >> +Example usage of counting PCIe RX TLP data payload (Units of 16 bytes)::
> >> +
> >> +    $# perf stat -a -e pcie_bdf_200/Rx_PCIe_TLP_Data_Payload/
> > 
> > Do you really need to expose a separate PMU instance to userspace for each
> > BDF? I think it would be much cleaner if you could follow the approach used
> > by hisilicon/hisi_pcie_pmu.c and hide these details in the driver, exposing
> > a `bdf=' selector to userspace instead.
> 
> Thank you for your valuable comments.
> 
> It's a good idea to encode bdf in bitmap and exposing a `bdf=' selector to userspace.
> The problem of bdf selector is that the user need to compute bdf from lanes, do you
> think it is user friendly? I'm worried about increasing the burden of users.

I don't see this as being an issue, particularly if you document how to do
it.

Will

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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
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  reply	other threads:[~2022-11-07 15:28 UTC|newest]

Thread overview: 158+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-17 12:10 [PATCH v1 0/3] drivers/perf: add Synopsys DesignWare PCIe PMU driver support Shuai Xue
2022-09-17 12:10 ` Shuai Xue
2022-09-17 12:10 ` [PATCH v1 1/3] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Shuai Xue
2022-09-17 12:10   ` Shuai Xue
2022-09-22 13:25   ` Will Deacon
2022-09-22 13:25     ` Will Deacon
2022-09-23 13:51     ` Shuai Xue
2022-09-23 13:51       ` Shuai Xue
2022-11-07 15:28       ` Will Deacon [this message]
2022-11-07 15:28         ` Will Deacon
2022-09-23  1:27   ` Yicong Yang
2022-09-23  1:27     ` Yicong Yang
2022-09-23 14:47     ` Shuai Xue
2022-09-23 14:47       ` Shuai Xue
2022-09-17 12:10 ` [PATCH v1 2/3] drivers/perf: add " Shuai Xue
2022-09-17 12:10   ` Shuai Xue
2022-09-22 15:58   ` Jonathan Cameron
2022-09-22 15:58     ` Jonathan Cameron
2022-09-22 17:32     ` Bjorn Helgaas
2022-09-22 17:32       ` Bjorn Helgaas
2022-09-23  3:35       ` Yicong Yang
2022-09-23  3:35         ` Yicong Yang
2022-09-23 10:56         ` Jonathan Cameron
2022-09-23 10:56           ` Jonathan Cameron
2022-09-23 13:45     ` Shuai Xue
2022-09-23 13:45       ` Shuai Xue
2022-09-23 15:54       ` Jonathan Cameron
2022-09-23 15:54         ` Jonathan Cameron
2022-09-26 13:31         ` Shuai Xue
2022-09-26 13:31           ` Shuai Xue
2022-09-26 14:32           ` Robin Murphy
2022-09-26 14:32             ` Robin Murphy
2022-09-26 17:18           ` Bjorn Helgaas
2022-09-26 17:18             ` Bjorn Helgaas
2022-09-27  5:13             ` Shuai Xue
2022-09-27  5:13               ` Shuai Xue
2022-09-27 10:04               ` Jonathan Cameron
2022-09-27 10:04                 ` Jonathan Cameron
2022-09-27 10:14                 ` Robin Murphy
2022-09-27 10:14                   ` Robin Murphy
2022-09-27 12:49                   ` Shuai Xue
2022-09-27 12:49                     ` Shuai Xue
2022-09-27 13:39                     ` Jonathan Cameron
2022-09-27 13:39                       ` Jonathan Cameron
2022-09-27 12:29                 ` Shuai Xue
2022-09-27 12:29                   ` Shuai Xue
2022-09-27 10:03             ` Jonathan Cameron
2022-09-27 10:03               ` Jonathan Cameron
2022-09-22 17:36   ` Bjorn Helgaas
2022-09-22 17:36     ` Bjorn Helgaas
2022-09-23 14:46     ` Shuai Xue
2022-09-23 14:46       ` Shuai Xue
2022-09-23 18:51       ` Bjorn Helgaas
2022-09-23 18:51         ` Bjorn Helgaas
2022-09-27  6:01         ` Shuai Xue
2022-09-27  6:01           ` Shuai Xue
2022-09-23  3:30   ` Yicong Yang
2022-09-23  3:30     ` Yicong Yang
2022-09-23 15:43     ` Shuai Xue
2022-09-23 15:43       ` Shuai Xue
2022-09-24  8:00       ` Yicong Yang
2022-09-24  8:00         ` Yicong Yang
2022-09-26 11:39         ` Shuai Xue
2022-09-26 11:39           ` Shuai Xue
2022-09-17 12:10 ` [PATCH v1 3/3] MAINTAINERS: add maintainers for " Shuai Xue
2022-09-17 12:10   ` Shuai Xue
2023-04-10  3:16 ` [PATCH v2 0/3] drivers/perf: add Synopsys DesignWare PCIe PMU driver support Shuai Xue
2023-04-10  3:16   ` Shuai Xue
2023-04-10  3:17 ` [PATCH v2 1/3] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Shuai Xue
2023-04-10  3:17   ` Shuai Xue
2023-04-10  3:17 ` [PATCH v2 2/3] drivers/perf: add " Shuai Xue
2023-04-10  3:17   ` Shuai Xue
2023-04-10  7:25   ` kernel test robot
2023-04-10  7:25     ` kernel test robot
2023-04-11  3:17   ` Baolin Wang
2023-04-11  3:17     ` Baolin Wang
2023-04-17  1:16     ` Shuai Xue
2023-04-17  1:16       ` Shuai Xue
2023-04-18  1:51       ` Baolin Wang
2023-04-18  1:51         ` Baolin Wang
2023-04-19  1:39         ` Shuai Xue
2023-04-19  1:39           ` Shuai Xue
2023-04-10  3:17 ` [PATCH v2 3/3] MAINTAINERS: add maintainers for " Shuai Xue
2023-04-10  3:17   ` Shuai Xue
2023-04-17  6:17 ` [PATCH v3 0/3] drivers/perf: add Synopsys DesignWare PCIe PMU driver support Shuai Xue
2023-04-17  6:17   ` Shuai Xue
2023-04-17  6:17 ` [PATCH v3 1/3] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Shuai Xue
2023-04-17  6:17   ` Shuai Xue
2023-05-16 14:32   ` Jonathan Cameron
2023-05-16 14:32     ` Jonathan Cameron
2023-05-17  1:27     ` Shuai Xue
2023-05-17  1:27       ` Shuai Xue
2023-04-17  6:17 ` [PATCH v3 2/3] drivers/perf: add " Shuai Xue
2023-04-17  6:17   ` Shuai Xue
2023-04-18 23:30   ` Robin Murphy
2023-04-18 23:30     ` Robin Murphy
2023-04-27  6:33     ` Shuai Xue
2023-04-27  6:33       ` Shuai Xue
2023-05-09  2:02       ` Shuai Xue
2023-05-16 15:03       ` Jonathan Cameron
2023-05-16 15:03         ` Jonathan Cameron
2023-05-16 19:17         ` Bjorn Helgaas
2023-05-16 19:17           ` Bjorn Helgaas
2023-05-17  9:54           ` Jonathan Cameron
2023-05-17  9:54             ` Jonathan Cameron
2023-05-17 16:27             ` Bjorn Helgaas
2023-05-17 16:27               ` Bjorn Helgaas
2023-05-19 10:08               ` Shuai Xue
2023-05-19 10:08                 ` Shuai Xue
2023-04-17  6:17 ` [PATCH v3 3/3] MAINTAINERS: add maintainers for " Shuai Xue
2023-04-17  6:17   ` Shuai Xue
2023-05-16 13:01 ` [PATCH v4 0/4] drivers/perf: add Synopsys DesignWare PCIe PMU driver support Shuai Xue
2023-05-16 13:01   ` Shuai Xue
2023-05-16 13:01 ` [PATCH v4 1/4] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Shuai Xue
2023-05-16 13:01   ` Shuai Xue
2023-05-16 13:01 ` [PATCH v4 2/4] PCI: move Alibaba Vendor ID linux/pci_ids.h Shuai Xue
2023-05-16 13:01   ` Shuai Xue
2023-05-16 13:01 ` [PATCH v4 3/4] drivers/perf: add DesignWare PCIe PMU driver Shuai Xue
2023-05-16 13:01   ` Shuai Xue
2023-05-16 19:19   ` Bjorn Helgaas
2023-05-16 19:19     ` Bjorn Helgaas
2023-05-17  2:35     ` Shuai Xue
2023-05-17  2:35       ` Shuai Xue
2023-05-16 23:21   ` kernel test robot
2023-05-17  3:37     ` Shuai Xue
2023-05-17  3:37       ` Shuai Xue
2023-05-16 13:01 ` [PATCH v4 4/4] MAINTAINERS: add maintainers for " Shuai Xue
2023-05-16 13:01   ` Shuai Xue
2023-05-22  3:54 ` [PATCH v5 0/4] drivers/perf: add Synopsys DesignWare PCIe PMU driver support Shuai Xue
2023-05-22  3:54   ` Shuai Xue
2023-05-22 14:28   ` Jonathan Cameron
2023-05-22 14:28     ` Jonathan Cameron
2023-05-23  2:57     ` Shuai Xue
2023-05-23  2:57       ` Shuai Xue
2023-05-22  3:54 ` [PATCH v5 1/4] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Shuai Xue
2023-05-22  3:54   ` Shuai Xue
2023-05-29  3:45   ` Baolin Wang
2023-05-29  3:45     ` Baolin Wang
2023-05-29  6:31     ` Shuai Xue
2023-05-29  6:31       ` Shuai Xue
2023-05-22  3:54 ` [PATCH v5 2/4] PCI: move Alibaba Vendor ID linux/pci_ids.h Shuai Xue
2023-05-22  3:54   ` Shuai Xue
2023-05-22 16:04   ` Bjorn Helgaas
2023-05-22 16:04     ` Bjorn Helgaas
2023-05-23  3:22     ` Shuai Xue
2023-05-23  3:22       ` Shuai Xue
2023-05-23 11:54       ` Bjorn Helgaas
2023-05-23 11:54         ` Bjorn Helgaas
2023-05-23 12:49         ` Shuai Xue
2023-05-23 12:49           ` Shuai Xue
2023-05-22  3:54 ` [PATCH v5 3/4] drivers/perf: add DesignWare PCIe PMU driver Shuai Xue
2023-05-22  3:54   ` Shuai Xue
2023-05-29  6:13   ` Baolin Wang
2023-05-29  6:13     ` Baolin Wang
2023-05-29  6:33     ` Shuai Xue
2023-05-29  6:33       ` Shuai Xue
2023-05-22  3:54 ` [PATCH v5 4/4] MAINTAINERS: add maintainers for " Shuai Xue
2023-05-22  3:54   ` Shuai Xue

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