Re: [PATCH v2 1/5] phy: amlogic: enable/disable clkin during Amlogic USB PHY init/exit

[neil.armstrong@linaro.org]

On 18/04/2023 13:16, Dmitry Rokosov wrote:
> Previously, all Amlogic boards used the XTAL clock as the default board
> clock for the USB PHY input, so there was no need to enable it.
> However, with the introduction of new Amlogic SoCs like the A1 family,
> the USB PHY now uses a gated clock. Hence, it is necessary to enable
> this gated clock during the PHY initialization sequence, or disable it
> during the PHY exit, as appropriate.
> 
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
>   drivers/phy/amlogic/phy-meson-g12a-usb2.c | 13 +++++++++++--
>   1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
> index 9d1efa0d9394..80938751da4f 100644
> --- a/drivers/phy/amlogic/phy-meson-g12a-usb2.c
> +++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
> @@ -172,10 +172,16 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
>   	int ret;
>   	unsigned int value;
>   
> -	ret = reset_control_reset(priv->reset);
> +	ret = clk_prepare_enable(priv->clk);
>   	if (ret)
>   		return ret;
>   
> +	ret = reset_control_reset(priv->reset);
> +	if (ret) {
> +		clk_disable_unprepare(priv->clk);
> +		return ret;
> +	}
> +
>   	udelay(RESET_COMPLETE_TIME);
>   
>   	/* usb2_otg_aca_en == 0 */
> @@ -277,8 +283,11 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
>   static int phy_meson_g12a_usb2_exit(struct phy *phy)
>   {
>   	struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy);
> +	int ret = reset_control_reset(priv->reset);
> +
> +	clk_disable_unprepare(priv->clk);
>   
> -	return reset_control_reset(priv->reset);
> +	return ret;
>   }
>   
>   /* set_mode is not needed, mode setting is handled via the UTMI bus */

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>