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From: Russell King - ARM Linux <linux@arm.linux.org.uk>
To: Chanho Min <chanho0207@gmail.com>
Cc: Alan Cox <alan@linux.intel.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com>,
	"Kim, Jong-Sung" <neidhard.kim@lge.com>,
	linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org
Subject: Re: [PATCH] Clear previous interrupts after fifo is disabled
Date: Tue, 28 Feb 2012 08:35:45 +0000	[thread overview]
Message-ID: <20120228083545.GA18045@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <CAOAMb1BjC2bF=rpJAhRUrB_U2mp8HGWxfcp+=TZ1etWzjUEwig@mail.gmail.com>

On Tue, Feb 28, 2012 at 10:35:30AM +0900, Chanho Min wrote:
> On Mon, Feb 27, 2012 at 8:02 PM, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
> > On Mon, Feb 27, 2012 at 10:48:58AM +0000, Russell King - ARM Linux wrote:
> >> I'd much prefer to only clear those interrupts which actually need to be
> >> cleared at this point.  So, I'd suggest this approach instead:
> >
> > Thinking about this a little more, we definitely want to mask and clear
> > interrupts at probe time as well:
> >
> I'm not satisfied with this completely. RIS has some pending
> interrupts even if interrupts are masked/disabled in IMSC. If your
> patch is applied, interrupt can be pended as bellows and RXFE of the
> flag register is set as well.

RXFE _will_ be set.  Think about it - RXFE means Receive Fifo Empty.
If the receive fifo is empty, it _will_ be set.

And RIS is the _Raw_ interrupt status.  That's the status _before_ the
mask is acted upon.

> writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
>        UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
> ...
> Interrupt is occured and pended in RIS

But it won't be delivered because the mask register is zero.

> ..
> writew(uap->im, uap->port.membase + UART011_IMSC);
> 
> Root cause is that Rx interrupt set but Rx fifo is empty. If we just
> remove the sentence for clearing LCRH, nothing happens and interrupt
> handler don't this misbehave.

No.

WARNING: multiple messages have this Message-ID (diff)
From: Russell King - ARM Linux <linux@arm.linux.org.uk>
To: Chanho Min <chanho0207@gmail.com>
Cc: Alan Cox <alan@linux.intel.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com>,
	"Kim, Jong-Sung" <neidhard.kim@lge.com>,
	linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org
Subject: Re: [PATCH] Clear previous interrupts after fifo is disabled
Date: Tue, 28 Feb 2012 08:35:45 +0000	[thread overview]
Message-ID: <20120228083545.GA18045@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <CAOAMb1BjC2bF=rpJAhRUrB_U2mp8HGWxfcp+=TZ1etWzjUEwig@mail.gmail.com>

On Tue, Feb 28, 2012 at 10:35:30AM +0900, Chanho Min wrote:
> On Mon, Feb 27, 2012 at 8:02 PM, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
> > On Mon, Feb 27, 2012 at 10:48:58AM +0000, Russell King - ARM Linux wrote:
> >> I'd much prefer to only clear those interrupts which actually need to be
> >> cleared at this point.  So, I'd suggest this approach instead:
> >
> > Thinking about this a little more, we definitely want to mask and clear
> > interrupts at probe time as well:
> >
> I'm not satisfied with this completely. RIS has some pending
> interrupts even if interrupts are masked/disabled in IMSC. If your
> patch is applied, interrupt can be pended as bellows and RXFE of the
> flag register is set as well.

RXFE _will_ be set.  Think about it - RXFE means Receive Fifo Empty.
If the receive fifo is empty, it _will_ be set.

And RIS is the _Raw_ interrupt status.  That's the status _before_ the
mask is acted upon.

> writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
>        UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
> ...
> Interrupt is occured and pended in RIS

But it won't be delivered because the mask register is zero.

> ..
> writew(uap->im, uap->port.membase + UART011_IMSC);
> 
> Root cause is that Rx interrupt set but Rx fifo is empty. If we just
> remove the sentence for clearing LCRH, nothing happens and interrupt
> handler don't this misbehave.

No.
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  reply	other threads:[~2012-02-28  8:36 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-02-27  9:30 [PATCH] Clear previous interrupts after fifo is disabled Chanho Min
2012-02-27 10:45 ` Linus Walleij
2012-02-27 10:45   ` Linus Walleij
2012-02-27 10:48 ` Russell King - ARM Linux
2012-02-27 11:02   ` Russell King - ARM Linux
2012-02-27 13:54     ` Linus Walleij
2012-02-28  1:35     ` Chanho Min
2012-02-28  8:35       ` Russell King - ARM Linux [this message]
2012-02-28  8:35         ` Russell King - ARM Linux
2012-02-28  9:16         ` Chanho Min
2012-02-28  9:16           ` Chanho Min
2012-02-28  9:21           ` Russell King - ARM Linux
2012-02-28  9:46             ` Chanho Min
2012-02-28 10:23               ` Russell King - ARM Linux
2012-02-29  2:47                 ` Chanho Min
2012-02-29  2:47                   ` Chanho Min
2012-03-08  9:02 ` Kim, Jong-Sung
2012-03-08  9:02   ` Kim, Jong-Sung
2012-03-08 18:49 ` Greg Kroah-Hartman
2012-03-09 16:34   ` Linus Walleij
2012-03-09 16:34     ` Linus Walleij
2012-03-09 16:37     ` Greg Kroah-Hartman
2012-03-09 16:37       ` Greg Kroah-Hartman
2012-03-10  2:14       ` Chanho Min
2012-03-12  1:24         ` Kim, Jong-Sung
2012-03-12  1:24           ` Kim, Jong-Sung
2012-03-12  8:29   ` Linus Walleij

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