* [PATCH] drm/i915: implement Disable4x2SubspanOptimization w/a for ivb, too
@ 2012-04-24 14:00 Daniel Vetter
2012-04-24 15:57 ` Ben Widawsky
0 siblings, 1 reply; 5+ messages in thread
From: Daniel Vetter @ 2012-04-24 14:00 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter, Ben Widawsky
Copy&pasted from the vlv setup code. According to docs, we need that
on ivb, too.
v2: Use new masked bit handling macros.
Cc: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a26bf49..93d4ce3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2776,6 +2776,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
}
gen7_setup_fixed_func_scheduler(dev_priv);
+
+ /* WaDisable4x2SubspanOptimization */
+ I915_WRITE(CACHE_MODE_1,
+ _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
}
static void valleyview_init_clock_gating(struct drm_device *dev)
--
1.7.9
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: implement Disable4x2SubspanOptimization w/a for ivb, too
2012-04-24 14:00 [PATCH] drm/i915: implement Disable4x2SubspanOptimization w/a for ivb, too Daniel Vetter
@ 2012-04-24 15:57 ` Ben Widawsky
2012-04-24 16:26 ` Daniel Vetter
0 siblings, 1 reply; 5+ messages in thread
From: Ben Widawsky @ 2012-04-24 15:57 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
On Tue, 24 Apr 2012 16:00:21 +0200
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Copy&pasted from the vlv setup code. According to docs, we need that
> on ivb, too.
>
> v2: Use new masked bit handling macros.
>
> Cc: Ben Widawsky <ben@bwidawsk.net>
> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: implement Disable4x2SubspanOptimization w/a for ivb, too
2012-04-24 15:57 ` Ben Widawsky
@ 2012-04-24 16:26 ` Daniel Vetter
0 siblings, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2012-04-24 16:26 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Daniel Vetter, Intel Graphics Development
On Tue, Apr 24, 2012 at 08:57:42AM -0700, Ben Widawsky wrote:
> On Tue, 24 Apr 2012 16:00:21 +0200
> Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
>
> > Copy&pasted from the vlv setup code. According to docs, we need that
> > on ivb, too.
> >
> > v2: Use new masked bit handling macros.
> >
> > Cc: Ben Widawsky <ben@bwidawsk.net>
> > Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Queued for -next, thanks for the review.
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: implement Disable4x2SubspanOptimization w/a for ivb, too
2012-04-14 22:54 Daniel Vetter
@ 2012-04-18 9:21 ` Daniel Vetter
0 siblings, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2012-04-18 9:21 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter, Ben Widawsky
On Sun, Apr 15, 2012 at 12:54:00AM +0200, Daniel Vetter wrote:
> Copy&pasted from the vlv setup code. According to docs, we need that
> on ivb, too.
>
> Cc: Ben Widawsky <ben@bwidawsk.net>
> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben, can you please take a look at this?
Thanks, Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 33aaad3..7be1d1a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8938,6 +8938,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> DISPPLANE_TRICKLE_FEED_DISABLE);
> intel_flush_display_plane(dev_priv, pipe);
> }
> +
> + /* WaDisable4x2SubspanOptimization */
> + I915_WRITE(CACHE_MODE_1, I915_READ(CACHE_MODE_1) |
> + (PIXEL_SUBSPAN_COLLECT_OPT_DISABLE << 16) |
> + PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
> }
>
> static void valleyview_init_clock_gating(struct drm_device *dev)
> --
> 1.7.10
>
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] drm/i915: implement Disable4x2SubspanOptimization w/a for ivb, too
@ 2012-04-14 22:54 Daniel Vetter
2012-04-18 9:21 ` Daniel Vetter
0 siblings, 1 reply; 5+ messages in thread
From: Daniel Vetter @ 2012-04-14 22:54 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter, Ben Widawsky
Copy&pasted from the vlv setup code. According to docs, we need that
on ivb, too.
Cc: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 33aaad3..7be1d1a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8938,6 +8938,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
DISPPLANE_TRICKLE_FEED_DISABLE);
intel_flush_display_plane(dev_priv, pipe);
}
+
+ /* WaDisable4x2SubspanOptimization */
+ I915_WRITE(CACHE_MODE_1, I915_READ(CACHE_MODE_1) |
+ (PIXEL_SUBSPAN_COLLECT_OPT_DISABLE << 16) |
+ PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
}
static void valleyview_init_clock_gating(struct drm_device *dev)
--
1.7.10
^ permalink raw reply related [flat|nested] 5+ messages in thread
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2012-04-24 14:00 [PATCH] drm/i915: implement Disable4x2SubspanOptimization w/a for ivb, too Daniel Vetter
2012-04-24 15:57 ` Ben Widawsky
2012-04-24 16:26 ` Daniel Vetter
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2012-04-14 22:54 Daniel Vetter
2012-04-18 9:21 ` Daniel Vetter
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