All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH] drm/i915: implement Disable4x2SubspanOptimization w/a for ivb, too
@ 2012-04-24 14:00 Daniel Vetter
  2012-04-24 15:57 ` Ben Widawsky
  0 siblings, 1 reply; 5+ messages in thread
From: Daniel Vetter @ 2012-04-24 14:00 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter, Ben Widawsky

Copy&pasted from the vlv setup code. According to docs, we need that
on ivb, too.

v2: Use new masked bit handling macros.

Cc: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_pm.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a26bf49..93d4ce3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2776,6 +2776,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	}
 
 	gen7_setup_fixed_func_scheduler(dev_priv);
+
+	/* WaDisable4x2SubspanOptimization */
+	I915_WRITE(CACHE_MODE_1,
+		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
 }
 
 static void valleyview_init_clock_gating(struct drm_device *dev)
-- 
1.7.9

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH] drm/i915: implement Disable4x2SubspanOptimization w/a for ivb, too
@ 2012-04-14 22:54 Daniel Vetter
  2012-04-18  9:21 ` Daniel Vetter
  0 siblings, 1 reply; 5+ messages in thread
From: Daniel Vetter @ 2012-04-14 22:54 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter, Ben Widawsky

Copy&pasted from the vlv setup code. According to docs, we need that
on ivb, too.

Cc: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 33aaad3..7be1d1a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8938,6 +8938,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 			   DISPPLANE_TRICKLE_FEED_DISABLE);
 		intel_flush_display_plane(dev_priv, pipe);
 	}
+
+	/* WaDisable4x2SubspanOptimization */
+	I915_WRITE(CACHE_MODE_1, I915_READ(CACHE_MODE_1) |
+		   (PIXEL_SUBSPAN_COLLECT_OPT_DISABLE << 16) |
+		   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
 }
 
 static void valleyview_init_clock_gating(struct drm_device *dev)
-- 
1.7.10

^ permalink raw reply related	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2012-04-24 16:25 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-04-24 14:00 [PATCH] drm/i915: implement Disable4x2SubspanOptimization w/a for ivb, too Daniel Vetter
2012-04-24 15:57 ` Ben Widawsky
2012-04-24 16:26   ` Daniel Vetter
  -- strict thread matches above, loose matches on Subject: below --
2012-04-14 22:54 Daniel Vetter
2012-04-18  9:21 ` Daniel Vetter

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.