[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

If l2x0 controller has been enabled when calling l2x0_init, the aux ctrl
register will not be saved in l2x0_saved_regs. Therefore we can not use
l2x0_saved_regs.aux_ctrl for resume later. This patch fixed the problem
by saving aux ctrl in l2x0_saved_regs just after it's being read from
the register.

Signed-off-by: Yilu Mao <ylmao@marvell.com>
---
 arch/arm/mm/cache-l2x0.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index a53fd2a..3034b06 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -320,6 +320,12 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
 	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
+	/* In case l2x controller is enabled, the aux ctrl register
+	 * can't be set. So the original value should be stored in
+	 * the l2x0_saved_regs for restoring when resume.
+	 */
+	l2x0_saved_regs.aux_ctrl = aux;
+
 	aux &= aux_mask;
 	aux |= aux_val;
 
-- 
1.7.5.4

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

If l2x0 controller has been enabled when calling l2x0_init, the aux ctrl
register will not be saved in l2x0_saved_regs. Therefore we can not use
l2x0_saved_regs.aux_ctrl for resume later. This patch fixed the problem
by saving aux ctrl in l2x0_saved_regs just after it's being read from
the register.

Signed-off-by: Yilu Mao <ylmao@marvell.com>
---
 arch/arm/mm/cache-l2x0.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index a53fd2a..3034b06 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -320,6 +320,12 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
 	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
+	/* In case l2x controller is enabled, the aux ctrl register
+	 * can't be set. So the original value should be stored in
+	 * the l2x0_saved_regs for restoring when resume.
+	 */
+	l2x0_saved_regs.aux_ctrl = aux;
+
 	aux &= aux_mask;
 	aux |= aux_val;
 
-- 
1.7.5.4

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Catalin Marinas]

On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
> If l2x0 controller has been enabled when calling l2x0_init, the aux ctrl
> register will not be saved in l2x0_saved_regs. Therefore we can not use
> l2x0_saved_regs.aux_ctrl for resume later. This patch fixed the problem
> by saving aux ctrl in l2x0_saved_regs just after it's being read from
> the register.
> 
> Signed-off-by: Yilu Mao <ylmao@marvell.com>
> ---
>  arch/arm/mm/cache-l2x0.c |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index a53fd2a..3034b06 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -320,6 +320,12 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
>  	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
>  	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
>  
> +	/* In case l2x controller is enabled, the aux ctrl register
> +	 * can't be set. So the original value should be stored in
> +	 * the l2x0_saved_regs for restoring when resume.
> +	 */

Even better like this ;)

+	/*
+	 * In case l2x controller is enabled, the aux ctrl register
+	 * can't be set. So the original value should be stored in
+	 * the l2x0_saved_regs for restoring when resume.
+	 */


> +	l2x0_saved_regs.aux_ctrl = aux;
> +
>  	aux &= aux_mask;
>  	aux |= aux_val;

I think that's the wrong place to save it, it should be after the
masking was done.

Anyway, if we cannot write this register in l2x0_init() because the L2
was enabled, do we expect the L2 to be disabled during resume?

-- 
Catalin

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Catalin Marinas]

On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
> If l2x0 controller has been enabled when calling l2x0_init, the aux ctrl
> register will not be saved in l2x0_saved_regs. Therefore we can not use
> l2x0_saved_regs.aux_ctrl for resume later. This patch fixed the problem
> by saving aux ctrl in l2x0_saved_regs just after it's being read from
> the register.
> 
> Signed-off-by: Yilu Mao <ylmao@marvell.com>
> ---
>  arch/arm/mm/cache-l2x0.c |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index a53fd2a..3034b06 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -320,6 +320,12 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
>  	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
>  	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
>  
> +	/* In case l2x controller is enabled, the aux ctrl register
> +	 * can't be set. So the original value should be stored in
> +	 * the l2x0_saved_regs for restoring when resume.
> +	 */

Even better like this ;)

+	/*
+	 * In case l2x controller is enabled, the aux ctrl register
+	 * can't be set. So the original value should be stored in
+	 * the l2x0_saved_regs for restoring when resume.
+	 */


> +	l2x0_saved_regs.aux_ctrl = aux;
> +
>  	aux &= aux_mask;
>  	aux |= aux_val;

I think that's the wrong place to save it, it should be after the
masking was done.

Anyway, if we cannot write this register in l2x0_init() because the L2
was enabled, do we expect the L2 to be disabled during resume?

-- 
Catalin

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/24/2012 04:28 PM, Catalin Marinas wrote:
> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>> If l2x0 controller has been enabled when calling l2x0_init, the aux ctrl
>> register will not be saved in l2x0_saved_regs. Therefore we can not use
>> l2x0_saved_regs.aux_ctrl for resume later. This patch fixed the problem
>> by saving aux ctrl in l2x0_saved_regs just after it's being read from
>> the register.
>>
>> Signed-off-by: Yilu Mao<ylmao@marvell.com>
>> ---
>>   arch/arm/mm/cache-l2x0.c |    6 ++++++
>>   1 files changed, 6 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
>> index a53fd2a..3034b06 100644
>> --- a/arch/arm/mm/cache-l2x0.c
>> +++ b/arch/arm/mm/cache-l2x0.c
>> @@ -320,6 +320,12 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
>>   	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
>>   	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
>>
>> +	/* In case l2x controller is enabled, the aux ctrl register
>> +	 * can't be set. So the original value should be stored in
>> +	 * the l2x0_saved_regs for restoring when resume.
>> +	 */
>
> Even better like this ;)
>
> +	/*
> +	 * In case l2x controller is enabled, the aux ctrl register
> +	 * can't be set. So the original value should be stored in
> +	 * the l2x0_saved_regs for restoring when resume.
> +	 */
>
>
>> +	l2x0_saved_regs.aux_ctrl = aux;
>> +
>>   	aux&= aux_mask;
>>   	aux |= aux_val;
>
> I think that's the wrong place to save it, it should be after the
> masking was done.
>
> Anyway, if we cannot write this register in l2x0_init() because the L2
> was enabled, do we expect the L2 to be disabled during resume?
>
Sorry, I don't think so.
This is the right place to save it because we must make sure the saved 
aux_ctrl is the same as what it is set.
If we save it after masking was done, the saved value will be different 
because we can't actually change the real setting.

What do you think?

-- 
Thanks.

Best Wishes,
Yilu Mao

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/24/2012 04:28 PM, Catalin Marinas wrote:
> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>> If l2x0 controller has been enabled when calling l2x0_init, the aux ctrl
>> register will not be saved in l2x0_saved_regs. Therefore we can not use
>> l2x0_saved_regs.aux_ctrl for resume later. This patch fixed the problem
>> by saving aux ctrl in l2x0_saved_regs just after it's being read from
>> the register.
>>
>> Signed-off-by: Yilu Mao<ylmao@marvell.com>
>> ---
>>   arch/arm/mm/cache-l2x0.c |    6 ++++++
>>   1 files changed, 6 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
>> index a53fd2a..3034b06 100644
>> --- a/arch/arm/mm/cache-l2x0.c
>> +++ b/arch/arm/mm/cache-l2x0.c
>> @@ -320,6 +320,12 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
>>   	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
>>   	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
>>
>> +	/* In case l2x controller is enabled, the aux ctrl register
>> +	 * can't be set. So the original value should be stored in
>> +	 * the l2x0_saved_regs for restoring when resume.
>> +	 */
>
> Even better like this ;)
>
> +	/*
> +	 * In case l2x controller is enabled, the aux ctrl register
> +	 * can't be set. So the original value should be stored in
> +	 * the l2x0_saved_regs for restoring when resume.
> +	 */
>
>
>> +	l2x0_saved_regs.aux_ctrl = aux;
>> +
>>   	aux&= aux_mask;
>>   	aux |= aux_val;
>
> I think that's the wrong place to save it, it should be after the
> masking was done.
>
> Anyway, if we cannot write this register in l2x0_init() because the L2
> was enabled, do we expect the L2 to be disabled during resume?
>
Sorry, I don't think so.
This is the right place to save it because we must make sure the saved 
aux_ctrl is the same as what it is set.
If we save it after masking was done, the saved value will be different 
because we can't actually change the real setting.

What do you think?

-- 
Thanks.

Best Wishes,
Yilu Mao

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Catalin Marinas]

On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
> > On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
> >> +	l2x0_saved_regs.aux_ctrl = aux;
> >> +
> >>   	aux&= aux_mask;
> >>   	aux |= aux_val;
> >
> > I think that's the wrong place to save it, it should be after the
> > masking was done.
> >
> > Anyway, if we cannot write this register in l2x0_init() because the L2
> > was enabled, do we expect the L2 to be disabled during resume?
> >
> Sorry, I don't think so.
> This is the right place to save it because we must make sure the saved 
> aux_ctrl is the same as what it is set.
> If we save it after masking was done, the saved value will be different 
> because we can't actually change the real setting.

And since we can't actually change the real setting on the resume path,
why do we need to save it anyway. Is your L2 cache disabled on the
resume path but not on the cold boot one?

-- 
Catalin

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Catalin Marinas]

On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
> > On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
> >> +	l2x0_saved_regs.aux_ctrl = aux;
> >> +
> >>   	aux&= aux_mask;
> >>   	aux |= aux_val;
> >
> > I think that's the wrong place to save it, it should be after the
> > masking was done.
> >
> > Anyway, if we cannot write this register in l2x0_init() because the L2
> > was enabled, do we expect the L2 to be disabled during resume?
> >
> Sorry, I don't think so.
> This is the right place to save it because we must make sure the saved 
> aux_ctrl is the same as what it is set.
> If we save it after masking was done, the saved value will be different 
> because we can't actually change the real setting.

And since we can't actually change the real setting on the resume path,
why do we need to save it anyway. Is your L2 cache disabled on the
resume path but not on the cold boot one?

-- 
Catalin

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/26/2012 04:35 PM, Catalin Marinas wrote:
> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>>>> +	l2x0_saved_regs.aux_ctrl = aux;
>>>> +
>>>>    	aux&= aux_mask;
>>>>    	aux |= aux_val;
>>>
>>> I think that's the wrong place to save it, it should be after the
>>> masking was done.
>>>
>>> Anyway, if we cannot write this register in l2x0_init() because the L2
>>> was enabled, do we expect the L2 to be disabled during resume?
>>>
>> Sorry, I don't think so.
>> This is the right place to save it because we must make sure the saved
>> aux_ctrl is the same as what it is set.
>> If we save it after masking was done, the saved value will be different
>> because we can't actually change the real setting.
>
> And since we can't actually change the real setting on the resume path,
> why do we need to save it anyway. Is your L2 cache disabled on the
> resume path but not on the cold boot one?
>
We can't change L2 aux ctrl setting when do init because it has been 
enabled. But we have the requirement to handle core idle. For CA9 core 
idle, L2 controller may be reset. So we need to restore the L2 
controller registers base on l2x0_saved_regs. This is why we need to 
keep the value in l2x0_saved_regs to be the same as real setting.

-- 
Thanks.

Best Wishes,
Yilu Mao

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/26/2012 04:35 PM, Catalin Marinas wrote:
> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>>>> +	l2x0_saved_regs.aux_ctrl = aux;
>>>> +
>>>>    	aux&= aux_mask;
>>>>    	aux |= aux_val;
>>>
>>> I think that's the wrong place to save it, it should be after the
>>> masking was done.
>>>
>>> Anyway, if we cannot write this register in l2x0_init() because the L2
>>> was enabled, do we expect the L2 to be disabled during resume?
>>>
>> Sorry, I don't think so.
>> This is the right place to save it because we must make sure the saved
>> aux_ctrl is the same as what it is set.
>> If we save it after masking was done, the saved value will be different
>> because we can't actually change the real setting.
>
> And since we can't actually change the real setting on the resume path,
> why do we need to save it anyway. Is your L2 cache disabled on the
> resume path but not on the cold boot one?
>
We can't change L2 aux ctrl setting when do init because it has been 
enabled. But we have the requirement to handle core idle. For CA9 core 
idle, L2 controller may be reset. So we need to restore the L2 
controller registers base on l2x0_saved_regs. This is why we need to 
keep the value in l2x0_saved_regs to be the same as real setting.

-- 
Thanks.

Best Wishes,
Yilu Mao

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Catalin Marinas]

On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
> > On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
> >> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
> >>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
> >>>> +	l2x0_saved_regs.aux_ctrl = aux;
> >>>> +
> >>>>    	aux&= aux_mask;
> >>>>    	aux |= aux_val;
> >>>
> >>> I think that's the wrong place to save it, it should be after the
> >>> masking was done.
> >>>
> >>> Anyway, if we cannot write this register in l2x0_init() because the L2
> >>> was enabled, do we expect the L2 to be disabled during resume?
> >>>
> >> Sorry, I don't think so.
> >> This is the right place to save it because we must make sure the saved
> >> aux_ctrl is the same as what it is set.
> >> If we save it after masking was done, the saved value will be different
> >> because we can't actually change the real setting.
> >
> > And since we can't actually change the real setting on the resume path,
> > why do we need to save it anyway. Is your L2 cache disabled on the
> > resume path but not on the cold boot one?
>
> We can't change L2 aux ctrl setting when do init because it has been 
> enabled.

This is normally for the case where the kernel running in non-secure
mode is not allowed to write the L2 aux ctrl register. Does this
permission change with core idle?

-- 
Catalin

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Catalin Marinas]

On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
> > On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
> >> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
> >>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
> >>>> +	l2x0_saved_regs.aux_ctrl = aux;
> >>>> +
> >>>>    	aux&= aux_mask;
> >>>>    	aux |= aux_val;
> >>>
> >>> I think that's the wrong place to save it, it should be after the
> >>> masking was done.
> >>>
> >>> Anyway, if we cannot write this register in l2x0_init() because the L2
> >>> was enabled, do we expect the L2 to be disabled during resume?
> >>>
> >> Sorry, I don't think so.
> >> This is the right place to save it because we must make sure the saved
> >> aux_ctrl is the same as what it is set.
> >> If we save it after masking was done, the saved value will be different
> >> because we can't actually change the real setting.
> >
> > And since we can't actually change the real setting on the resume path,
> > why do we need to save it anyway. Is your L2 cache disabled on the
> > resume path but not on the cold boot one?
>
> We can't change L2 aux ctrl setting when do init because it has been 
> enabled.

This is normally for the case where the kernel running in non-secure
mode is not allowed to write the L2 aux ctrl register. Does this
permission change with core idle?

-- 
Catalin

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/26/2012 05:44 PM, Catalin Marinas wrote:
> On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
>> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
>>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
>>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
>>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
>>>>>> +
>>>>>>     	aux&= aux_mask;
>>>>>>     	aux |= aux_val;
>>>>>
>>>>> I think that's the wrong place to save it, it should be after the
>>>>> masking was done.
>>>>>
>>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
>>>>> was enabled, do we expect the L2 to be disabled during resume?
>>>>>
>>>> Sorry, I don't think so.
>>>> This is the right place to save it because we must make sure the saved
>>>> aux_ctrl is the same as what it is set.
>>>> If we save it after masking was done, the saved value will be different
>>>> because we can't actually change the real setting.
>>>
>>> And since we can't actually change the real setting on the resume path,
>>> why do we need to save it anyway. Is your L2 cache disabled on the
>>> resume path but not on the cold boot one?
>>
>> We can't change L2 aux ctrl setting when do init because it has been
>> enabled.
>
> This is normally for the case where the kernel running in non-secure
> mode is not allowed to write the L2 aux ctrl register. Does this
> permission change with core idle?
>
Yes, your understanding of previous mail is right. The L2 is enabled on 
code boot and it is disabled on the resume in our case.
So if we don't have such patch, when core idle exit, L2 cache aux ctrl 
register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not 
initialized.

-- 
Thanks.

Best Wishes,
Yilu Mao

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/26/2012 05:44 PM, Catalin Marinas wrote:
> On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
>> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
>>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
>>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
>>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
>>>>>> +
>>>>>>     	aux&= aux_mask;
>>>>>>     	aux |= aux_val;
>>>>>
>>>>> I think that's the wrong place to save it, it should be after the
>>>>> masking was done.
>>>>>
>>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
>>>>> was enabled, do we expect the L2 to be disabled during resume?
>>>>>
>>>> Sorry, I don't think so.
>>>> This is the right place to save it because we must make sure the saved
>>>> aux_ctrl is the same as what it is set.
>>>> If we save it after masking was done, the saved value will be different
>>>> because we can't actually change the real setting.
>>>
>>> And since we can't actually change the real setting on the resume path,
>>> why do we need to save it anyway. Is your L2 cache disabled on the
>>> resume path but not on the cold boot one?
>>
>> We can't change L2 aux ctrl setting when do init because it has been
>> enabled.
>
> This is normally for the case where the kernel running in non-secure
> mode is not allowed to write the L2 aux ctrl register. Does this
> permission change with core idle?
>
Yes, your understanding of previous mail is right. The L2 is enabled on 
code boot and it is disabled on the resume in our case.
So if we don't have such patch, when core idle exit, L2 cache aux ctrl 
register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not 
initialized.

-- 
Thanks.

Best Wishes,
Yilu Mao

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Catalin Marinas]

On Thu, Apr 26, 2012 at 11:09:26AM +0100, Yilu Mao wrote:
> On 04/26/2012 05:44 PM, Catalin Marinas wrote:
> > On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
> >> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
> >>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
> >>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
> >>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
> >>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
> >>>>>> +
> >>>>>>     	aux&= aux_mask;
> >>>>>>     	aux |= aux_val;
> >>>>>
> >>>>> I think that's the wrong place to save it, it should be after the
> >>>>> masking was done.
> >>>>>
> >>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
> >>>>> was enabled, do we expect the L2 to be disabled during resume?
> >>>>>
> >>>> Sorry, I don't think so.
> >>>> This is the right place to save it because we must make sure the saved
> >>>> aux_ctrl is the same as what it is set.
> >>>> If we save it after masking was done, the saved value will be different
> >>>> because we can't actually change the real setting.
> >>>
> >>> And since we can't actually change the real setting on the resume path,
> >>> why do we need to save it anyway. Is your L2 cache disabled on the
> >>> resume path but not on the cold boot one?
> >>
> >> We can't change L2 aux ctrl setting when do init because it has been
> >> enabled.
> >
> > This is normally for the case where the kernel running in non-secure
> > mode is not allowed to write the L2 aux ctrl register. Does this
> > permission change with core idle?
> >
> Yes, your understanding of previous mail is right. The L2 is enabled on 
> code boot and it is disabled on the resume in our case.

But the kernel either runs in secure mode or the non-secure access to
this register is allowed.

> So if we don't have such patch, when core idle exit, L2 cache aux ctrl 
> register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not 
> initialized.

You could still make sure that the mask passed doesn't affect the
original setting and save it after masking.

-- 
Catalin

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Catalin Marinas]

On Thu, Apr 26, 2012 at 11:09:26AM +0100, Yilu Mao wrote:
> On 04/26/2012 05:44 PM, Catalin Marinas wrote:
> > On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
> >> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
> >>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
> >>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
> >>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
> >>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
> >>>>>> +
> >>>>>>     	aux&= aux_mask;
> >>>>>>     	aux |= aux_val;
> >>>>>
> >>>>> I think that's the wrong place to save it, it should be after the
> >>>>> masking was done.
> >>>>>
> >>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
> >>>>> was enabled, do we expect the L2 to be disabled during resume?
> >>>>>
> >>>> Sorry, I don't think so.
> >>>> This is the right place to save it because we must make sure the saved
> >>>> aux_ctrl is the same as what it is set.
> >>>> If we save it after masking was done, the saved value will be different
> >>>> because we can't actually change the real setting.
> >>>
> >>> And since we can't actually change the real setting on the resume path,
> >>> why do we need to save it anyway. Is your L2 cache disabled on the
> >>> resume path but not on the cold boot one?
> >>
> >> We can't change L2 aux ctrl setting when do init because it has been
> >> enabled.
> >
> > This is normally for the case where the kernel running in non-secure
> > mode is not allowed to write the L2 aux ctrl register. Does this
> > permission change with core idle?
> >
> Yes, your understanding of previous mail is right. The L2 is enabled on 
> code boot and it is disabled on the resume in our case.

But the kernel either runs in secure mode or the non-secure access to
this register is allowed.

> So if we don't have such patch, when core idle exit, L2 cache aux ctrl 
> register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not 
> initialized.

You could still make sure that the mask passed doesn't affect the
original setting and save it after masking.

-- 
Catalin

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/26/2012 06:28 PM, Catalin Marinas wrote:
> On Thu, Apr 26, 2012 at 11:09:26AM +0100, Yilu Mao wrote:
>> On 04/26/2012 05:44 PM, Catalin Marinas wrote:
>>> On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
>>>> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
>>>>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
>>>>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
>>>>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>>>>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
>>>>>>>> +
>>>>>>>>      	aux&= aux_mask;
>>>>>>>>      	aux |= aux_val;
>>>>>>>
>>>>>>> I think that's the wrong place to save it, it should be after the
>>>>>>> masking was done.
>>>>>>>
>>>>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
>>>>>>> was enabled, do we expect the L2 to be disabled during resume?
>>>>>>>
>>>>>> Sorry, I don't think so.
>>>>>> This is the right place to save it because we must make sure the saved
>>>>>> aux_ctrl is the same as what it is set.
>>>>>> If we save it after masking was done, the saved value will be different
>>>>>> because we can't actually change the real setting.
>>>>>
>>>>> And since we can't actually change the real setting on the resume path,
>>>>> why do we need to save it anyway. Is your L2 cache disabled on the
>>>>> resume path but not on the cold boot one?
>>>>
>>>> We can't change L2 aux ctrl setting when do init because it has been
>>>> enabled.
>>>
>>> This is normally for the case where the kernel running in non-secure
>>> mode is not allowed to write the L2 aux ctrl register. Does this
>>> permission change with core idle?
>>>
>> Yes, your understanding of previous mail is right. The L2 is enabled on
>> code boot and it is disabled on the resume in our case.
>
> But the kernel either runs in secure mode or the non-secure access to
> this register is allowed.
>
>> So if we don't have such patch, when core idle exit, L2 cache aux ctrl
>> register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not
>> initialized.
>
> You could still make sure that the mask passed doesn't affect the
> original setting and save it after masking.
>
Do you mean the code is like this:
aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
aux &= aux_mask;
l2x0_saved_regs.aux_ctrl = aux;

Then the saved value is not the same as real setting. So the restored 
value after core idle will not the same as before... This is not what we 
expected.

-- 
Thanks.

Best Wishes,
Yilu Mao

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/26/2012 06:28 PM, Catalin Marinas wrote:
> On Thu, Apr 26, 2012 at 11:09:26AM +0100, Yilu Mao wrote:
>> On 04/26/2012 05:44 PM, Catalin Marinas wrote:
>>> On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
>>>> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
>>>>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
>>>>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
>>>>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>>>>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
>>>>>>>> +
>>>>>>>>      	aux&= aux_mask;
>>>>>>>>      	aux |= aux_val;
>>>>>>>
>>>>>>> I think that's the wrong place to save it, it should be after the
>>>>>>> masking was done.
>>>>>>>
>>>>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
>>>>>>> was enabled, do we expect the L2 to be disabled during resume?
>>>>>>>
>>>>>> Sorry, I don't think so.
>>>>>> This is the right place to save it because we must make sure the saved
>>>>>> aux_ctrl is the same as what it is set.
>>>>>> If we save it after masking was done, the saved value will be different
>>>>>> because we can't actually change the real setting.
>>>>>
>>>>> And since we can't actually change the real setting on the resume path,
>>>>> why do we need to save it anyway. Is your L2 cache disabled on the
>>>>> resume path but not on the cold boot one?
>>>>
>>>> We can't change L2 aux ctrl setting when do init because it has been
>>>> enabled.
>>>
>>> This is normally for the case where the kernel running in non-secure
>>> mode is not allowed to write the L2 aux ctrl register. Does this
>>> permission change with core idle?
>>>
>> Yes, your understanding of previous mail is right. The L2 is enabled on
>> code boot and it is disabled on the resume in our case.
>
> But the kernel either runs in secure mode or the non-secure access to
> this register is allowed.
>
>> So if we don't have such patch, when core idle exit, L2 cache aux ctrl
>> register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not
>> initialized.
>
> You could still make sure that the mask passed doesn't affect the
> original setting and save it after masking.
>
Do you mean the code is like this:
aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
aux &= aux_mask;
l2x0_saved_regs.aux_ctrl = aux;

Then the saved value is not the same as real setting. So the restored 
value after core idle will not the same as before... This is not what we 
expected.

-- 
Thanks.

Best Wishes,
Yilu Mao

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Catalin Marinas]

On Thu, Apr 26, 2012 at 11:35:39AM +0100, Yilu Mao wrote:
> On 04/26/2012 06:28 PM, Catalin Marinas wrote:
> > On Thu, Apr 26, 2012 at 11:09:26AM +0100, Yilu Mao wrote:
> >> On 04/26/2012 05:44 PM, Catalin Marinas wrote:
> >>> On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
> >>>> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
> >>>>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
> >>>>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
> >>>>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
> >>>>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
> >>>>>>>> +
> >>>>>>>>      	aux&= aux_mask;
> >>>>>>>>      	aux |= aux_val;
> >>>>>>>
> >>>>>>> I think that's the wrong place to save it, it should be after the
> >>>>>>> masking was done.
> >>>>>>>
> >>>>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
> >>>>>>> was enabled, do we expect the L2 to be disabled during resume?
> >>>>>>>
> >>>>>> Sorry, I don't think so.
> >>>>>> This is the right place to save it because we must make sure the saved
> >>>>>> aux_ctrl is the same as what it is set.
> >>>>>> If we save it after masking was done, the saved value will be different
> >>>>>> because we can't actually change the real setting.
> >>>>>
> >>>>> And since we can't actually change the real setting on the resume path,
> >>>>> why do we need to save it anyway. Is your L2 cache disabled on the
> >>>>> resume path but not on the cold boot one?
> >>>>
> >>>> We can't change L2 aux ctrl setting when do init because it has been
> >>>> enabled.
> >>>
> >>> This is normally for the case where the kernel running in non-secure
> >>> mode is not allowed to write the L2 aux ctrl register. Does this
> >>> permission change with core idle?
> >>>
> >> Yes, your understanding of previous mail is right. The L2 is enabled on
> >> code boot and it is disabled on the resume in our case.
> >
> > But the kernel either runs in secure mode or the non-secure access to
> > this register is allowed.
> >
> >> So if we don't have such patch, when core idle exit, L2 cache aux ctrl
> >> register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not
> >> initialized.
> >
> > You could still make sure that the mask passed doesn't affect the
> > original setting and save it after masking.
> >
> Do you mean the code is like this:
> aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
> aux &= aux_mask;
> l2x0_saved_regs.aux_ctrl = aux;
> 
> Then the saved value is not the same as real setting. So the restored 
> value after core idle will not the same as before... This is not what we 
> expected.

My point was that on your platform you pass an aux_mask that is meant to
change the already set aux_ctlr value. Why do you pass such mask to be
anything other than ~0UL in this case?

-- 
Catalin

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Catalin Marinas]

On Thu, Apr 26, 2012 at 11:35:39AM +0100, Yilu Mao wrote:
> On 04/26/2012 06:28 PM, Catalin Marinas wrote:
> > On Thu, Apr 26, 2012 at 11:09:26AM +0100, Yilu Mao wrote:
> >> On 04/26/2012 05:44 PM, Catalin Marinas wrote:
> >>> On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
> >>>> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
> >>>>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
> >>>>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
> >>>>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
> >>>>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
> >>>>>>>> +
> >>>>>>>>      	aux&= aux_mask;
> >>>>>>>>      	aux |= aux_val;
> >>>>>>>
> >>>>>>> I think that's the wrong place to save it, it should be after the
> >>>>>>> masking was done.
> >>>>>>>
> >>>>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
> >>>>>>> was enabled, do we expect the L2 to be disabled during resume?
> >>>>>>>
> >>>>>> Sorry, I don't think so.
> >>>>>> This is the right place to save it because we must make sure the saved
> >>>>>> aux_ctrl is the same as what it is set.
> >>>>>> If we save it after masking was done, the saved value will be different
> >>>>>> because we can't actually change the real setting.
> >>>>>
> >>>>> And since we can't actually change the real setting on the resume path,
> >>>>> why do we need to save it anyway. Is your L2 cache disabled on the
> >>>>> resume path but not on the cold boot one?
> >>>>
> >>>> We can't change L2 aux ctrl setting when do init because it has been
> >>>> enabled.
> >>>
> >>> This is normally for the case where the kernel running in non-secure
> >>> mode is not allowed to write the L2 aux ctrl register. Does this
> >>> permission change with core idle?
> >>>
> >> Yes, your understanding of previous mail is right. The L2 is enabled on
> >> code boot and it is disabled on the resume in our case.
> >
> > But the kernel either runs in secure mode or the non-secure access to
> > this register is allowed.
> >
> >> So if we don't have such patch, when core idle exit, L2 cache aux ctrl
> >> register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not
> >> initialized.
> >
> > You could still make sure that the mask passed doesn't affect the
> > original setting and save it after masking.
> >
> Do you mean the code is like this:
> aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
> aux &= aux_mask;
> l2x0_saved_regs.aux_ctrl = aux;
> 
> Then the saved value is not the same as real setting. So the restored 
> value after core idle will not the same as before... This is not what we 
> expected.

My point was that on your platform you pass an aux_mask that is meant to
change the already set aux_ctlr value. Why do you pass such mask to be
anything other than ~0UL in this case?

-- 
Catalin

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/26/2012 06:38 PM, Catalin Marinas wrote:
> On Thu, Apr 26, 2012 at 11:35:39AM +0100, Yilu Mao wrote:
>> On 04/26/2012 06:28 PM, Catalin Marinas wrote:
>>> On Thu, Apr 26, 2012 at 11:09:26AM +0100, Yilu Mao wrote:
>>>> On 04/26/2012 05:44 PM, Catalin Marinas wrote:
>>>>> On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
>>>>>> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
>>>>>>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
>>>>>>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
>>>>>>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>>>>>>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
>>>>>>>>>> +
>>>>>>>>>>       	aux&= aux_mask;
>>>>>>>>>>       	aux |= aux_val;
>>>>>>>>>
>>>>>>>>> I think that's the wrong place to save it, it should be after the
>>>>>>>>> masking was done.
>>>>>>>>>
>>>>>>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
>>>>>>>>> was enabled, do we expect the L2 to be disabled during resume?
>>>>>>>>>
>>>>>>>> Sorry, I don't think so.
>>>>>>>> This is the right place to save it because we must make sure the saved
>>>>>>>> aux_ctrl is the same as what it is set.
>>>>>>>> If we save it after masking was done, the saved value will be different
>>>>>>>> because we can't actually change the real setting.
>>>>>>>
>>>>>>> And since we can't actually change the real setting on the resume path,
>>>>>>> why do we need to save it anyway. Is your L2 cache disabled on the
>>>>>>> resume path but not on the cold boot one?
>>>>>>
>>>>>> We can't change L2 aux ctrl setting when do init because it has been
>>>>>> enabled.
>>>>>
>>>>> This is normally for the case where the kernel running in non-secure
>>>>> mode is not allowed to write the L2 aux ctrl register. Does this
>>>>> permission change with core idle?
>>>>>
>>>> Yes, your understanding of previous mail is right. The L2 is enabled on
>>>> code boot and it is disabled on the resume in our case.
>>>
>>> But the kernel either runs in secure mode or the non-secure access to
>>> this register is allowed.
>>>
>>>> So if we don't have such patch, when core idle exit, L2 cache aux ctrl
>>>> register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not
>>>> initialized.
>>>
>>> You could still make sure that the mask passed doesn't affect the
>>> original setting and save it after masking.
>>>
>> Do you mean the code is like this:
>> aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
>> aux&= aux_mask;
>> l2x0_saved_regs.aux_ctrl = aux;
>>
>> Then the saved value is not the same as real setting. So the restored
>> value after core idle will not the same as before... This is not what we
>> expected.
>
> My point was that on your platform you pass an aux_mask that is meant to
> change the already set aux_ctlr value. Why do you pass such mask to be
> anything other than ~0UL in this case?
>
Sorry I still can't catch your point...
In our platform, we actually use ~0UL as aux mask.

Anyway, the two arguments, aux_value and aux_mask, are both for changing 
the original value set before kernel bootup. If L2 cache is enabled in 
cold boot, both two arguments are useless because we can't set the 
register. So we must make sure we can restore the original value after 
core idle.

-- 
Thanks.

Best Wishes,
Yilu Mao

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/26/2012 06:38 PM, Catalin Marinas wrote:
> On Thu, Apr 26, 2012 at 11:35:39AM +0100, Yilu Mao wrote:
>> On 04/26/2012 06:28 PM, Catalin Marinas wrote:
>>> On Thu, Apr 26, 2012 at 11:09:26AM +0100, Yilu Mao wrote:
>>>> On 04/26/2012 05:44 PM, Catalin Marinas wrote:
>>>>> On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
>>>>>> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
>>>>>>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
>>>>>>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
>>>>>>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>>>>>>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
>>>>>>>>>> +
>>>>>>>>>>       	aux&= aux_mask;
>>>>>>>>>>       	aux |= aux_val;
>>>>>>>>>
>>>>>>>>> I think that's the wrong place to save it, it should be after the
>>>>>>>>> masking was done.
>>>>>>>>>
>>>>>>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
>>>>>>>>> was enabled, do we expect the L2 to be disabled during resume?
>>>>>>>>>
>>>>>>>> Sorry, I don't think so.
>>>>>>>> This is the right place to save it because we must make sure the saved
>>>>>>>> aux_ctrl is the same as what it is set.
>>>>>>>> If we save it after masking was done, the saved value will be different
>>>>>>>> because we can't actually change the real setting.
>>>>>>>
>>>>>>> And since we can't actually change the real setting on the resume path,
>>>>>>> why do we need to save it anyway. Is your L2 cache disabled on the
>>>>>>> resume path but not on the cold boot one?
>>>>>>
>>>>>> We can't change L2 aux ctrl setting when do init because it has been
>>>>>> enabled.
>>>>>
>>>>> This is normally for the case where the kernel running in non-secure
>>>>> mode is not allowed to write the L2 aux ctrl register. Does this
>>>>> permission change with core idle?
>>>>>
>>>> Yes, your understanding of previous mail is right. The L2 is enabled on
>>>> code boot and it is disabled on the resume in our case.
>>>
>>> But the kernel either runs in secure mode or the non-secure access to
>>> this register is allowed.
>>>
>>>> So if we don't have such patch, when core idle exit, L2 cache aux ctrl
>>>> register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not
>>>> initialized.
>>>
>>> You could still make sure that the mask passed doesn't affect the
>>> original setting and save it after masking.
>>>
>> Do you mean the code is like this:
>> aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
>> aux&= aux_mask;
>> l2x0_saved_regs.aux_ctrl = aux;
>>
>> Then the saved value is not the same as real setting. So the restored
>> value after core idle will not the same as before... This is not what we
>> expected.
>
> My point was that on your platform you pass an aux_mask that is meant to
> change the already set aux_ctlr value. Why do you pass such mask to be
> anything other than ~0UL in this case?
>
Sorry I still can't catch your point...
In our platform, we actually use ~0UL as aux mask.

Anyway, the two arguments, aux_value and aux_mask, are both for changing 
the original value set before kernel bootup. If L2 cache is enabled in 
cold boot, both two arguments are useless because we can't set the 
register. So we must make sure we can restore the original value after 
core idle.

-- 
Thanks.

Best Wishes,
Yilu Mao

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Catalin Marinas]

On Thu, Apr 26, 2012 at 11:48:18AM +0100, Yilu Mao wrote:
> On 04/26/2012 06:38 PM, Catalin Marinas wrote:
> > On Thu, Apr 26, 2012 at 11:35:39AM +0100, Yilu Mao wrote:
> >> On 04/26/2012 06:28 PM, Catalin Marinas wrote:
> >>> On Thu, Apr 26, 2012 at 11:09:26AM +0100, Yilu Mao wrote:
> >>>> On 04/26/2012 05:44 PM, Catalin Marinas wrote:
> >>>>> On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
> >>>>>> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
> >>>>>>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
> >>>>>>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
> >>>>>>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
> >>>>>>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
> >>>>>>>>>> +
> >>>>>>>>>>       	aux&= aux_mask;
> >>>>>>>>>>       	aux |= aux_val;
> >>>>>>>>>
> >>>>>>>>> I think that's the wrong place to save it, it should be after the
> >>>>>>>>> masking was done.
> >>>>>>>>>
> >>>>>>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
> >>>>>>>>> was enabled, do we expect the L2 to be disabled during resume?
> >>>>>>>>>
> >>>>>>>> Sorry, I don't think so.
> >>>>>>>> This is the right place to save it because we must make sure the saved
> >>>>>>>> aux_ctrl is the same as what it is set.
> >>>>>>>> If we save it after masking was done, the saved value will be different
> >>>>>>>> because we can't actually change the real setting.
> >>>>>>>
> >>>>>>> And since we can't actually change the real setting on the resume path,
> >>>>>>> why do we need to save it anyway. Is your L2 cache disabled on the
> >>>>>>> resume path but not on the cold boot one?
> >>>>>>
> >>>>>> We can't change L2 aux ctrl setting when do init because it has been
> >>>>>> enabled.
> >>>>>
> >>>>> This is normally for the case where the kernel running in non-secure
> >>>>> mode is not allowed to write the L2 aux ctrl register. Does this
> >>>>> permission change with core idle?
> >>>>>
> >>>> Yes, your understanding of previous mail is right. The L2 is enabled on
> >>>> code boot and it is disabled on the resume in our case.
> >>>
> >>> But the kernel either runs in secure mode or the non-secure access to
> >>> this register is allowed.
> >>>
> >>>> So if we don't have such patch, when core idle exit, L2 cache aux ctrl
> >>>> register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not
> >>>> initialized.
> >>>
> >>> You could still make sure that the mask passed doesn't affect the
> >>> original setting and save it after masking.
> >>>
> >> Do you mean the code is like this:
> >> aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
> >> aux&= aux_mask;
> >> l2x0_saved_regs.aux_ctrl = aux;
> >>
> >> Then the saved value is not the same as real setting. So the restored
> >> value after core idle will not the same as before... This is not what we
> >> expected.
> >
> > My point was that on your platform you pass an aux_mask that is meant to
> > change the already set aux_ctlr value. Why do you pass such mask to be
> > anything other than ~0UL in this case?
> >
> Sorry I still can't catch your point...
> In our platform, we actually use ~0UL as aux mask.
> 
> Anyway, the two arguments, aux_value and aux_mask, are both for changing 
> the original value set before kernel bootup. If L2 cache is enabled in 
> cold boot, both two arguments are useless because we can't set the 
> register. So we must make sure we can restore the original value after 
> core idle.

So if your platform passes aux_mask = ~0UL and aux_val = 0, there is no
change to the read aux_ctlr value.

If for whatever reason (same binary running in different configuration)
you need to pass the aux_mask and aux_val different from the above, then
your argument makes sense. But I just want to be clear.

-- 
Catalin

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Catalin Marinas]

On Thu, Apr 26, 2012 at 11:48:18AM +0100, Yilu Mao wrote:
> On 04/26/2012 06:38 PM, Catalin Marinas wrote:
> > On Thu, Apr 26, 2012 at 11:35:39AM +0100, Yilu Mao wrote:
> >> On 04/26/2012 06:28 PM, Catalin Marinas wrote:
> >>> On Thu, Apr 26, 2012 at 11:09:26AM +0100, Yilu Mao wrote:
> >>>> On 04/26/2012 05:44 PM, Catalin Marinas wrote:
> >>>>> On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
> >>>>>> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
> >>>>>>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
> >>>>>>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
> >>>>>>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
> >>>>>>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
> >>>>>>>>>> +
> >>>>>>>>>>       	aux&= aux_mask;
> >>>>>>>>>>       	aux |= aux_val;
> >>>>>>>>>
> >>>>>>>>> I think that's the wrong place to save it, it should be after the
> >>>>>>>>> masking was done.
> >>>>>>>>>
> >>>>>>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
> >>>>>>>>> was enabled, do we expect the L2 to be disabled during resume?
> >>>>>>>>>
> >>>>>>>> Sorry, I don't think so.
> >>>>>>>> This is the right place to save it because we must make sure the saved
> >>>>>>>> aux_ctrl is the same as what it is set.
> >>>>>>>> If we save it after masking was done, the saved value will be different
> >>>>>>>> because we can't actually change the real setting.
> >>>>>>>
> >>>>>>> And since we can't actually change the real setting on the resume path,
> >>>>>>> why do we need to save it anyway. Is your L2 cache disabled on the
> >>>>>>> resume path but not on the cold boot one?
> >>>>>>
> >>>>>> We can't change L2 aux ctrl setting when do init because it has been
> >>>>>> enabled.
> >>>>>
> >>>>> This is normally for the case where the kernel running in non-secure
> >>>>> mode is not allowed to write the L2 aux ctrl register. Does this
> >>>>> permission change with core idle?
> >>>>>
> >>>> Yes, your understanding of previous mail is right. The L2 is enabled on
> >>>> code boot and it is disabled on the resume in our case.
> >>>
> >>> But the kernel either runs in secure mode or the non-secure access to
> >>> this register is allowed.
> >>>
> >>>> So if we don't have such patch, when core idle exit, L2 cache aux ctrl
> >>>> register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not
> >>>> initialized.
> >>>
> >>> You could still make sure that the mask passed doesn't affect the
> >>> original setting and save it after masking.
> >>>
> >> Do you mean the code is like this:
> >> aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
> >> aux&= aux_mask;
> >> l2x0_saved_regs.aux_ctrl = aux;
> >>
> >> Then the saved value is not the same as real setting. So the restored
> >> value after core idle will not the same as before... This is not what we
> >> expected.
> >
> > My point was that on your platform you pass an aux_mask that is meant to
> > change the already set aux_ctlr value. Why do you pass such mask to be
> > anything other than ~0UL in this case?
> >
> Sorry I still can't catch your point...
> In our platform, we actually use ~0UL as aux mask.
> 
> Anyway, the two arguments, aux_value and aux_mask, are both for changing 
> the original value set before kernel bootup. If L2 cache is enabled in 
> cold boot, both two arguments are useless because we can't set the 
> register. So we must make sure we can restore the original value after 
> core idle.

So if your platform passes aux_mask = ~0UL and aux_val = 0, there is no
change to the read aux_ctlr value.

If for whatever reason (same binary running in different configuration)
you need to pass the aux_mask and aux_val different from the above, then
your argument makes sense. But I just want to be clear.

-- 
Catalin

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/26/2012 06:56 PM, Catalin Marinas wrote:
> On Thu, Apr 26, 2012 at 11:48:18AM +0100, Yilu Mao wrote:
>> On 04/26/2012 06:38 PM, Catalin Marinas wrote:
>>> On Thu, Apr 26, 2012 at 11:35:39AM +0100, Yilu Mao wrote:
>>>> On 04/26/2012 06:28 PM, Catalin Marinas wrote:
>>>>> On Thu, Apr 26, 2012 at 11:09:26AM +0100, Yilu Mao wrote:
>>>>>> On 04/26/2012 05:44 PM, Catalin Marinas wrote:
>>>>>>> On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
>>>>>>>> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
>>>>>>>>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
>>>>>>>>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
>>>>>>>>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>>>>>>>>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
>>>>>>>>>>>> +
>>>>>>>>>>>>        	aux&= aux_mask;
>>>>>>>>>>>>        	aux |= aux_val;
>>>>>>>>>>>
>>>>>>>>>>> I think that's the wrong place to save it, it should be after the
>>>>>>>>>>> masking was done.
>>>>>>>>>>>
>>>>>>>>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
>>>>>>>>>>> was enabled, do we expect the L2 to be disabled during resume?
>>>>>>>>>>>
>>>>>>>>>> Sorry, I don't think so.
>>>>>>>>>> This is the right place to save it because we must make sure the saved
>>>>>>>>>> aux_ctrl is the same as what it is set.
>>>>>>>>>> If we save it after masking was done, the saved value will be different
>>>>>>>>>> because we can't actually change the real setting.
>>>>>>>>>
>>>>>>>>> And since we can't actually change the real setting on the resume path,
>>>>>>>>> why do we need to save it anyway. Is your L2 cache disabled on the
>>>>>>>>> resume path but not on the cold boot one?
>>>>>>>>
>>>>>>>> We can't change L2 aux ctrl setting when do init because it has been
>>>>>>>> enabled.
>>>>>>>
>>>>>>> This is normally for the case where the kernel running in non-secure
>>>>>>> mode is not allowed to write the L2 aux ctrl register. Does this
>>>>>>> permission change with core idle?
>>>>>>>
>>>>>> Yes, your understanding of previous mail is right. The L2 is enabled on
>>>>>> code boot and it is disabled on the resume in our case.
>>>>>
>>>>> But the kernel either runs in secure mode or the non-secure access to
>>>>> this register is allowed.
>>>>>
>>>>>> So if we don't have such patch, when core idle exit, L2 cache aux ctrl
>>>>>> register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not
>>>>>> initialized.
>>>>>
>>>>> You could still make sure that the mask passed doesn't affect the
>>>>> original setting and save it after masking.
>>>>>
>>>> Do you mean the code is like this:
>>>> aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
>>>> aux&= aux_mask;
>>>> l2x0_saved_regs.aux_ctrl = aux;
>>>>
>>>> Then the saved value is not the same as real setting. So the restored
>>>> value after core idle will not the same as before... This is not what we
>>>> expected.
>>>
>>> My point was that on your platform you pass an aux_mask that is meant to
>>> change the already set aux_ctlr value. Why do you pass such mask to be
>>> anything other than ~0UL in this case?
>>>
>> Sorry I still can't catch your point...
>> In our platform, we actually use ~0UL as aux mask.
>>
>> Anyway, the two arguments, aux_value and aux_mask, are both for changing
>> the original value set before kernel bootup. If L2 cache is enabled in
>> cold boot, both two arguments are useless because we can't set the
>> register. So we must make sure we can restore the original value after
>> core idle.
>
> So if your platform passes aux_mask = ~0UL and aux_val = 0, there is no
> change to the read aux_ctlr value.
>
> If for whatever reason (same binary running in different configuration)
> you need to pass the aux_mask and aux_val different from the above, then
> your argument makes sense. But I just want to be clear.
>
Actually, our arguments are aux_value = 0x30000000 and aux_mask = ~0UL.
I think it is also ok with my patch.
What do you think?

-- 
Thanks.

Best Wishes,
Yilu Mao

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/26/2012 06:56 PM, Catalin Marinas wrote:
> On Thu, Apr 26, 2012 at 11:48:18AM +0100, Yilu Mao wrote:
>> On 04/26/2012 06:38 PM, Catalin Marinas wrote:
>>> On Thu, Apr 26, 2012 at 11:35:39AM +0100, Yilu Mao wrote:
>>>> On 04/26/2012 06:28 PM, Catalin Marinas wrote:
>>>>> On Thu, Apr 26, 2012 at 11:09:26AM +0100, Yilu Mao wrote:
>>>>>> On 04/26/2012 05:44 PM, Catalin Marinas wrote:
>>>>>>> On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
>>>>>>>> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
>>>>>>>>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
>>>>>>>>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
>>>>>>>>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>>>>>>>>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
>>>>>>>>>>>> +
>>>>>>>>>>>>        	aux&= aux_mask;
>>>>>>>>>>>>        	aux |= aux_val;
>>>>>>>>>>>
>>>>>>>>>>> I think that's the wrong place to save it, it should be after the
>>>>>>>>>>> masking was done.
>>>>>>>>>>>
>>>>>>>>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
>>>>>>>>>>> was enabled, do we expect the L2 to be disabled during resume?
>>>>>>>>>>>
>>>>>>>>>> Sorry, I don't think so.
>>>>>>>>>> This is the right place to save it because we must make sure the saved
>>>>>>>>>> aux_ctrl is the same as what it is set.
>>>>>>>>>> If we save it after masking was done, the saved value will be different
>>>>>>>>>> because we can't actually change the real setting.
>>>>>>>>>
>>>>>>>>> And since we can't actually change the real setting on the resume path,
>>>>>>>>> why do we need to save it anyway. Is your L2 cache disabled on the
>>>>>>>>> resume path but not on the cold boot one?
>>>>>>>>
>>>>>>>> We can't change L2 aux ctrl setting when do init because it has been
>>>>>>>> enabled.
>>>>>>>
>>>>>>> This is normally for the case where the kernel running in non-secure
>>>>>>> mode is not allowed to write the L2 aux ctrl register. Does this
>>>>>>> permission change with core idle?
>>>>>>>
>>>>>> Yes, your understanding of previous mail is right. The L2 is enabled on
>>>>>> code boot and it is disabled on the resume in our case.
>>>>>
>>>>> But the kernel either runs in secure mode or the non-secure access to
>>>>> this register is allowed.
>>>>>
>>>>>> So if we don't have such patch, when core idle exit, L2 cache aux ctrl
>>>>>> register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not
>>>>>> initialized.
>>>>>
>>>>> You could still make sure that the mask passed doesn't affect the
>>>>> original setting and save it after masking.
>>>>>
>>>> Do you mean the code is like this:
>>>> aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
>>>> aux&= aux_mask;
>>>> l2x0_saved_regs.aux_ctrl = aux;
>>>>
>>>> Then the saved value is not the same as real setting. So the restored
>>>> value after core idle will not the same as before... This is not what we
>>>> expected.
>>>
>>> My point was that on your platform you pass an aux_mask that is meant to
>>> change the already set aux_ctlr value. Why do you pass such mask to be
>>> anything other than ~0UL in this case?
>>>
>> Sorry I still can't catch your point...
>> In our platform, we actually use ~0UL as aux mask.
>>
>> Anyway, the two arguments, aux_value and aux_mask, are both for changing
>> the original value set before kernel bootup. If L2 cache is enabled in
>> cold boot, both two arguments are useless because we can't set the
>> register. So we must make sure we can restore the original value after
>> core idle.
>
> So if your platform passes aux_mask = ~0UL and aux_val = 0, there is no
> change to the read aux_ctlr value.
>
> If for whatever reason (same binary running in different configuration)
> you need to pass the aux_mask and aux_val different from the above, then
> your argument makes sense. But I just want to be clear.
>
Actually, our arguments are aux_value = 0x30000000 and aux_mask = ~0UL.
I think it is also ok with my patch.
What do you think?

-- 
Thanks.

Best Wishes,
Yilu Mao

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/26/2012 07:03 PM, Lu Mao wrote:
> On 04/26/2012 06:56 PM, Catalin Marinas wrote:
>> On Thu, Apr 26, 2012 at 11:48:18AM +0100, Yilu Mao wrote:
>>> On 04/26/2012 06:38 PM, Catalin Marinas wrote:
>>>> On Thu, Apr 26, 2012 at 11:35:39AM +0100, Yilu Mao wrote:
>>>>> On 04/26/2012 06:28 PM, Catalin Marinas wrote:
>>>>>> On Thu, Apr 26, 2012 at 11:09:26AM +0100, Yilu Mao wrote:
>>>>>>> On 04/26/2012 05:44 PM, Catalin Marinas wrote:
>>>>>>>> On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
>>>>>>>>> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
>>>>>>>>>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
>>>>>>>>>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
>>>>>>>>>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>>>>>>>>>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
>>>>>>>>>>>>> +
>>>>>>>>>>>>>         	aux&= aux_mask;
>>>>>>>>>>>>>         	aux |= aux_val;
>>>>>>>>>>>>
>>>>>>>>>>>> I think that's the wrong place to save it, it should be after the
>>>>>>>>>>>> masking was done.
>>>>>>>>>>>>
>>>>>>>>>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
>>>>>>>>>>>> was enabled, do we expect the L2 to be disabled during resume?
>>>>>>>>>>>>
>>>>>>>>>>> Sorry, I don't think so.
>>>>>>>>>>> This is the right place to save it because we must make sure the saved
>>>>>>>>>>> aux_ctrl is the same as what it is set.
>>>>>>>>>>> If we save it after masking was done, the saved value will be different
>>>>>>>>>>> because we can't actually change the real setting.
>>>>>>>>>>
>>>>>>>>>> And since we can't actually change the real setting on the resume path,
>>>>>>>>>> why do we need to save it anyway. Is your L2 cache disabled on the
>>>>>>>>>> resume path but not on the cold boot one?
>>>>>>>>>
>>>>>>>>> We can't change L2 aux ctrl setting when do init because it has been
>>>>>>>>> enabled.
>>>>>>>>
>>>>>>>> This is normally for the case where the kernel running in non-secure
>>>>>>>> mode is not allowed to write the L2 aux ctrl register. Does this
>>>>>>>> permission change with core idle?
>>>>>>>>
>>>>>>> Yes, your understanding of previous mail is right. The L2 is enabled on
>>>>>>> code boot and it is disabled on the resume in our case.
>>>>>>
>>>>>> But the kernel either runs in secure mode or the non-secure access to
>>>>>> this register is allowed.
>>>>>>
>>>>>>> So if we don't have such patch, when core idle exit, L2 cache aux ctrl
>>>>>>> register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not
>>>>>>> initialized.
>>>>>>
>>>>>> You could still make sure that the mask passed doesn't affect the
>>>>>> original setting and save it after masking.
>>>>>>
>>>>> Do you mean the code is like this:
>>>>> aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
>>>>> aux&= aux_mask;
>>>>> l2x0_saved_regs.aux_ctrl = aux;
>>>>>
>>>>> Then the saved value is not the same as real setting. So the restored
>>>>> value after core idle will not the same as before... This is not what we
>>>>> expected.
>>>>
>>>> My point was that on your platform you pass an aux_mask that is meant to
>>>> change the already set aux_ctlr value. Why do you pass such mask to be
>>>> anything other than ~0UL in this case?
>>>>
>>> Sorry I still can't catch your point...
>>> In our platform, we actually use ~0UL as aux mask.
>>>
>>> Anyway, the two arguments, aux_value and aux_mask, are both for changing
>>> the original value set before kernel bootup. If L2 cache is enabled in
>>> cold boot, both two arguments are useless because we can't set the
>>> register. So we must make sure we can restore the original value after
>>> core idle.
>>
>> So if your platform passes aux_mask = ~0UL and aux_val = 0, there is no
>> change to the read aux_ctlr value.
>>
>> If for whatever reason (same binary running in different configuration)
>> you need to pass the aux_mask and aux_val different from the above, then
>> your argument makes sense. But I just want to be clear.
>>
> Actually, our arguments are aux_value = 0x30000000 and aux_mask = ~0UL.
> I think it is also ok with my patch.
> What do you think?
>
Hi Catalin,

Do you agree with this patch to be merged?

-- 
Thanks.

Best Wishes,
Yilu Mao

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/26/2012 07:03 PM, Lu Mao wrote:
> On 04/26/2012 06:56 PM, Catalin Marinas wrote:
>> On Thu, Apr 26, 2012 at 11:48:18AM +0100, Yilu Mao wrote:
>>> On 04/26/2012 06:38 PM, Catalin Marinas wrote:
>>>> On Thu, Apr 26, 2012 at 11:35:39AM +0100, Yilu Mao wrote:
>>>>> On 04/26/2012 06:28 PM, Catalin Marinas wrote:
>>>>>> On Thu, Apr 26, 2012 at 11:09:26AM +0100, Yilu Mao wrote:
>>>>>>> On 04/26/2012 05:44 PM, Catalin Marinas wrote:
>>>>>>>> On Thu, Apr 26, 2012 at 10:25:31AM +0100, Yilu Mao wrote:
>>>>>>>>> On 04/26/2012 04:35 PM, Catalin Marinas wrote:
>>>>>>>>>> On Thu, Apr 26, 2012 at 06:00:09AM +0100, Yilu Mao wrote:
>>>>>>>>>>> On 04/24/2012 04:28 PM, Catalin Marinas wrote:
>>>>>>>>>>>> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>>>>>>>>>>>>> +	l2x0_saved_regs.aux_ctrl = aux;
>>>>>>>>>>>>> +
>>>>>>>>>>>>>         	aux&= aux_mask;
>>>>>>>>>>>>>         	aux |= aux_val;
>>>>>>>>>>>>
>>>>>>>>>>>> I think that's the wrong place to save it, it should be after the
>>>>>>>>>>>> masking was done.
>>>>>>>>>>>>
>>>>>>>>>>>> Anyway, if we cannot write this register in l2x0_init() because the L2
>>>>>>>>>>>> was enabled, do we expect the L2 to be disabled during resume?
>>>>>>>>>>>>
>>>>>>>>>>> Sorry, I don't think so.
>>>>>>>>>>> This is the right place to save it because we must make sure the saved
>>>>>>>>>>> aux_ctrl is the same as what it is set.
>>>>>>>>>>> If we save it after masking was done, the saved value will be different
>>>>>>>>>>> because we can't actually change the real setting.
>>>>>>>>>>
>>>>>>>>>> And since we can't actually change the real setting on the resume path,
>>>>>>>>>> why do we need to save it anyway. Is your L2 cache disabled on the
>>>>>>>>>> resume path but not on the cold boot one?
>>>>>>>>>
>>>>>>>>> We can't change L2 aux ctrl setting when do init because it has been
>>>>>>>>> enabled.
>>>>>>>>
>>>>>>>> This is normally for the case where the kernel running in non-secure
>>>>>>>> mode is not allowed to write the L2 aux ctrl register. Does this
>>>>>>>> permission change with core idle?
>>>>>>>>
>>>>>>> Yes, your understanding of previous mail is right. The L2 is enabled on
>>>>>>> code boot and it is disabled on the resume in our case.
>>>>>>
>>>>>> But the kernel either runs in secure mode or the non-secure access to
>>>>>> this register is allowed.
>>>>>>
>>>>>>> So if we don't have such patch, when core idle exit, L2 cache aux ctrl
>>>>>>> register will be set to 0x0 because l2x0_saved_regs.aux_ctrl is not
>>>>>>> initialized.
>>>>>>
>>>>>> You could still make sure that the mask passed doesn't affect the
>>>>>> original setting and save it after masking.
>>>>>>
>>>>> Do you mean the code is like this:
>>>>> aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
>>>>> aux&= aux_mask;
>>>>> l2x0_saved_regs.aux_ctrl = aux;
>>>>>
>>>>> Then the saved value is not the same as real setting. So the restored
>>>>> value after core idle will not the same as before... This is not what we
>>>>> expected.
>>>>
>>>> My point was that on your platform you pass an aux_mask that is meant to
>>>> change the already set aux_ctlr value. Why do you pass such mask to be
>>>> anything other than ~0UL in this case?
>>>>
>>> Sorry I still can't catch your point...
>>> In our platform, we actually use ~0UL as aux mask.
>>>
>>> Anyway, the two arguments, aux_value and aux_mask, are both for changing
>>> the original value set before kernel bootup. If L2 cache is enabled in
>>> cold boot, both two arguments are useless because we can't set the
>>> register. So we must make sure we can restore the original value after
>>> core idle.
>>
>> So if your platform passes aux_mask = ~0UL and aux_val = 0, there is no
>> change to the read aux_ctlr value.
>>
>> If for whatever reason (same binary running in different configuration)
>> you need to pass the aux_mask and aux_val different from the above, then
>> your argument makes sense. But I just want to be clear.
>>
> Actually, our arguments are aux_value = 0x30000000 and aux_mask = ~0UL.
> I think it is also ok with my patch.
> What do you think?
>
Hi Catalin,

Do you agree with this patch to be merged?

-- 
Thanks.

Best Wishes,
Yilu Mao

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Catalin Marinas]

On Sat, Apr 28, 2012 at 07:24:28AM +0100, Yilu Mao wrote:
> Do you agree with this patch to be merged?

I would rather re-read the aux_ctrl register again after it was set (if
L2 is disabled) and store this value. It makes sense if some of the bits
are reserved, at least we have the real value.

-- 
Catalin

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Catalin Marinas]

On Sat, Apr 28, 2012 at 07:24:28AM +0100, Yilu Mao wrote:
> Do you agree with this patch to be merged?

I would rather re-read the aux_ctrl register again after it was set (if
L2 is disabled) and store this value. It makes sense if some of the bits
are reserved, at least we have the real value.

-- 
Catalin

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/30/2012 08:11 PM, Catalin Marinas wrote:
> On Sat, Apr 28, 2012 at 07:24:28AM +0100, Yilu Mao wrote:
>> Do you agree with this patch to be merged?
>
> I would rather re-read the aux_ctrl register again after it was set (if
> L2 is disabled) and store this value. It makes sense if some of the bits
> are reserved, at least we have the real value.
>
Ok, I have provided a V4 patch including this.
Please help to review.

-- 
Thanks.

Best Wishes,
Yilu Mao

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/30/2012 08:11 PM, Catalin Marinas wrote:
> On Sat, Apr 28, 2012 at 07:24:28AM +0100, Yilu Mao wrote:
>> Do you agree with this patch to be merged?
>
> I would rather re-read the aux_ctrl register again after it was set (if
> L2 is disabled) and store this value. It makes sense if some of the bits
> are reserved, at least we have the real value.
>
Ok, I have provided a V4 patch including this.
Please help to review.

-- 
Thanks.

Best Wishes,
Yilu Mao

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/24/2012 04:28 PM, Catalin Marinas wrote:
> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>> If l2x0 controller has been enabled when calling l2x0_init, the aux ctrl
>> register will not be saved in l2x0_saved_regs. Therefore we can not use
>> l2x0_saved_regs.aux_ctrl for resume later. This patch fixed the problem
>> by saving aux ctrl in l2x0_saved_regs just after it's being read from
>> the register.
>>
>> Signed-off-by: Yilu Mao<ylmao@marvell.com>
>> ---
>>   arch/arm/mm/cache-l2x0.c |    6 ++++++
>>   1 files changed, 6 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
>> index a53fd2a..3034b06 100644
>> --- a/arch/arm/mm/cache-l2x0.c
>> +++ b/arch/arm/mm/cache-l2x0.c
>> @@ -320,6 +320,12 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
>>   	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
>>   	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
>>
>> +	/* In case l2x controller is enabled, the aux ctrl register
>> +	 * can't be set. So the original value should be stored in
>> +	 * the l2x0_saved_regs for restoring when resume.
>> +	 */
>
> Even better like this ;)
>
> +	/*
> +	 * In case l2x controller is enabled, the aux ctrl register
> +	 * can't be set. So the original value should be stored in
> +	 * the l2x0_saved_regs for restoring when resume.
> +	 */
>
>
>> +	l2x0_saved_regs.aux_ctrl = aux;
>> +
>>   	aux&= aux_mask;
>>   	aux |= aux_val;
>
> I think that's the wrong place to save it, it should be after the
> masking was done.
>
> Anyway, if we cannot write this register in l2x0_init() because the L2
> was enabled, do we expect the L2 to be disabled during resume?
>
Sorry, I don't think so.
This is the right place to save it because we must make sure the saved 
aux_ctrl is the same as what it is set.
If we save it after masking was done, the saved value will be different 
because we can't actually change the real setting.

What do you think?

-- 
Thanks.

Best Wishes,
Yilu Mao

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

On 04/24/2012 04:28 PM, Catalin Marinas wrote:
> On Tue, Apr 24, 2012 at 03:41:20AM +0100, Yilu Mao wrote:
>> If l2x0 controller has been enabled when calling l2x0_init, the aux ctrl
>> register will not be saved in l2x0_saved_regs. Therefore we can not use
>> l2x0_saved_regs.aux_ctrl for resume later. This patch fixed the problem
>> by saving aux ctrl in l2x0_saved_regs just after it's being read from
>> the register.
>>
>> Signed-off-by: Yilu Mao<ylmao@marvell.com>
>> ---
>>   arch/arm/mm/cache-l2x0.c |    6 ++++++
>>   1 files changed, 6 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
>> index a53fd2a..3034b06 100644
>> --- a/arch/arm/mm/cache-l2x0.c
>> +++ b/arch/arm/mm/cache-l2x0.c
>> @@ -320,6 +320,12 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
>>   	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
>>   	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
>>
>> +	/* In case l2x controller is enabled, the aux ctrl register
>> +	 * can't be set. So the original value should be stored in
>> +	 * the l2x0_saved_regs for restoring when resume.
>> +	 */
>
> Even better like this ;)
>
> +	/*
> +	 * In case l2x controller is enabled, the aux ctrl register
> +	 * can't be set. So the original value should be stored in
> +	 * the l2x0_saved_regs for restoring when resume.
> +	 */
>
>
>> +	l2x0_saved_regs.aux_ctrl = aux;
>> +
>>   	aux&= aux_mask;
>>   	aux |= aux_val;
>
> I think that's the wrong place to save it, it should be after the
> masking was done.
>
> Anyway, if we cannot write this register in l2x0_init() because the L2
> was enabled, do we expect the L2 to be disabled during resume?
>
Sorry, I don't think so.
This is the right place to save it because we must make sure the saved 
aux_ctrl is the same as what it is set.
If we save it after masking was done, the saved value will be different 
because we can't actually change the real setting.

What do you think?

-- 
Thanks.

Best Wishes,
Yilu Mao

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

If l2x0 controller has been enabled when calling l2x0_init, the aux ctrl
register will not be saved in l2x0_saved_regs. Therefore we can not use
l2x0_saved_regs.aux_ctrl for resume later. This patch fixed the problem
by saving aux ctrl in l2x0_saved_regs just after it's being read from
the register.

Signed-off-by: Yilu Mao <ylmao@marvell.com>
---
 arch/arm/mm/cache-l2x0.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 8936595..3b6428b 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -362,6 +362,11 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
 	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
+	/* In case l2x controller is enabled, the aux ctrl register
+	 * can't be set. So the original value should be stored in
+	 * the l2x0_saved_regs for restoring when resume. */
+	l2x0_saved_regs.aux_ctrl = aux;
+
 	aux &= aux_mask;
 	aux |= aux_val;
 
-- 
1.7.0.4

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Yilu Mao]

If l2x0 controller has been enabled when calling l2x0_init, the aux ctrl
register will not be saved in l2x0_saved_regs. Therefore we can not use
l2x0_saved_regs.aux_ctrl for resume later. This patch fixed the problem
by saving aux ctrl in l2x0_saved_regs just after it's being read from
the register.

Signed-off-by: Yilu Mao <ylmao@marvell.com>
---
 arch/arm/mm/cache-l2x0.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 8936595..3b6428b 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -362,6 +362,11 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
 	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
+	/* In case l2x controller is enabled, the aux ctrl register
+	 * can't be set. So the original value should be stored in
+	 * the l2x0_saved_regs for restoring when resume. */
+	l2x0_saved_regs.aux_ctrl = aux;
+
 	aux &= aux_mask;
 	aux |= aux_val;
 
-- 
1.7.0.4

Re: [PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Sergei Shtylyov]

Hello.

On 23-04-2012 11:43, Yilu Mao wrote:

> If l2x0 controller has been enabled when calling l2x0_init, the aux ctrl
> register will not be saved in l2x0_saved_regs. Therefore we can not use
> l2x0_saved_regs.aux_ctrl for resume later. This patch fixed the problem
> by saving aux ctrl in l2x0_saved_regs just after it's being read from
> the register.

> Signed-off-by: Yilu Mao<ylmao@marvell.com>
> ---
>   arch/arm/mm/cache-l2x0.c |    5 +++++
>   1 files changed, 5 insertions(+), 0 deletions(-)

> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 8936595..3b6428b 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -362,6 +362,11 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
>   	l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
>   	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
>
> +	/* In case l2x controller is enabled, the aux ctrl register
> +	 * can't be set. So the original value should be stored in
> +	 * the l2x0_saved_regs for restoring when resume. */

    The preferred style of multi-line comments is this:

/*
  * bla
  * bla
  */

WBR, Sergei

[PATCH] ARM: cache-l2x0.c: save aux ctrl for resume in case that l2x0 is enabled before init

[Sergei Shtylyov]

Hello.

On 23-04-2012 11:43, Yilu Mao wrote:

> If l2x0 controller has been enabled when calling l2x0_init, the aux ctrl
> register will not be saved in l2x0_saved_regs. Therefore we can not use
> l2x0_saved_regs.aux_ctrl for resume later. This patch fixed the problem
> by saving aux ctrl in l2x0_saved_regs just after it's being read from
> the register.

> Signed-off-by: Yilu Mao<ylmao@marvell.com>
> ---
>   arch/arm/mm/cache-l2x0.c |    5 +++++
>   1 files changed, 5 insertions(+), 0 deletions(-)

> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 8936595..3b6428b 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -362,6 +362,11 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
>   	l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
>   	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
>
> +	/* In case l2x controller is enabled, the aux ctrl register
> +	 * can't be set. So the original value should be stored in
> +	 * the l2x0_saved_regs for restoring when resume. */

    The preferred style of multi-line comments is this:

/*
  * bla
  * bla
  */

WBR, Sergei