* [PATCH 0/3] iommu/arm-smmu: Add driver for ARM SMMUv3 devices
@ 2015-05-08 18:00 ` Will Deacon
0 siblings, 0 replies; 40+ messages in thread
From: Will Deacon @ 2015-05-08 18:00 UTC (permalink / raw)
To: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA
Cc: Will Deacon, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Hi all,
SMMUv3 is a significant departure from previous ARM SMMU designs in that
the majority of the configuration data has been moved from MMIO registers
to in-memory data structures, with communication between the CPU and the
SMMU being mediated via in-memory circular queues. It also has native
support for MSI generation, PCI masters (e.g. ATS, PRI, PASIDs), ARM 8.1
architectural extensions (e.g. hardware translation table updates) and
optional RAS extensions. It is designed for large numbers of masters and
consequently uses a 32-bit StreamID.
This patch series adds an initial driver for ARM SMMUv3 devices, which
enables dma-mapping and VFIO for PCI masters. Unfortunately, there is
not yet any documentation available for the hardware, but I have tested
this successfully on internal simulation. Having the driver available at
this early stage is useful for ARM partners building implementations and
provides a common upstream base on which the driver can be developed.
Future work will look at:
- DMA to paged memory using PRI (for now we send a PRI_DENY response
and dump the transaction to the console)
- MSI generation from the SMMU (requires generic changes to the
irqdomain code)
- Support for non-PCI masters (pending core of_xlate rework as
discussed on linux-arm-kernel)
There's also the nested translation angle, but we should work out what
we're doing on SMMUv2 before implementing anything here.
All feedback welcome,
Will
--->8
Will Deacon (3):
Documentation: dt-bindings: Add device-tree binding for ARM SMMUv3
IOMMU
iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices
drivers/vfio: Allow type-1 IOMMU instantiation on top of an ARM SMMUv3
.../devicetree/bindings/iommu/arm,smmu-v3.txt | 37 +
MAINTAINERS | 3 +-
drivers/iommu/Kconfig | 13 +
drivers/iommu/Makefile | 1 +
drivers/iommu/arm-smmu-v3.c | 2599 ++++++++++++++++++++
drivers/vfio/Kconfig | 2 +-
6 files changed, 2653 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
create mode 100644 drivers/iommu/arm-smmu-v3.c
--
2.1.4
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH 0/3] iommu/arm-smmu: Add driver for ARM SMMUv3 devices @ 2015-05-08 18:00 ` Will Deacon 0 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-08 18:00 UTC (permalink / raw) To: linux-arm-kernel Hi all, SMMUv3 is a significant departure from previous ARM SMMU designs in that the majority of the configuration data has been moved from MMIO registers to in-memory data structures, with communication between the CPU and the SMMU being mediated via in-memory circular queues. It also has native support for MSI generation, PCI masters (e.g. ATS, PRI, PASIDs), ARM 8.1 architectural extensions (e.g. hardware translation table updates) and optional RAS extensions. It is designed for large numbers of masters and consequently uses a 32-bit StreamID. This patch series adds an initial driver for ARM SMMUv3 devices, which enables dma-mapping and VFIO for PCI masters. Unfortunately, there is not yet any documentation available for the hardware, but I have tested this successfully on internal simulation. Having the driver available at this early stage is useful for ARM partners building implementations and provides a common upstream base on which the driver can be developed. Future work will look at: - DMA to paged memory using PRI (for now we send a PRI_DENY response and dump the transaction to the console) - MSI generation from the SMMU (requires generic changes to the irqdomain code) - Support for non-PCI masters (pending core of_xlate rework as discussed on linux-arm-kernel) There's also the nested translation angle, but we should work out what we're doing on SMMUv2 before implementing anything here. All feedback welcome, Will --->8 Will Deacon (3): Documentation: dt-bindings: Add device-tree binding for ARM SMMUv3 IOMMU iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices drivers/vfio: Allow type-1 IOMMU instantiation on top of an ARM SMMUv3 .../devicetree/bindings/iommu/arm,smmu-v3.txt | 37 + MAINTAINERS | 3 +- drivers/iommu/Kconfig | 13 + drivers/iommu/Makefile | 1 + drivers/iommu/arm-smmu-v3.c | 2599 ++++++++++++++++++++ drivers/vfio/Kconfig | 2 +- 6 files changed, 2653 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt create mode 100644 drivers/iommu/arm-smmu-v3.c -- 2.1.4 ^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <1431108046-9675-1-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org>]
* [PATCH 1/3] Documentation: dt-bindings: Add device-tree binding for ARM SMMUv3 IOMMU 2015-05-08 18:00 ` Will Deacon @ 2015-05-08 18:00 ` Will Deacon -1 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-08 18:00 UTC (permalink / raw) To: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA Cc: Mark Rutland, Will Deacon, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r This patch adds device-tree bindings for ARM SMMUv3 IOMMU devices. Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> Signed-off-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> --- .../devicetree/bindings/iommu/arm,smmu-v3.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt new file mode 100644 index 000000000000..c03eec116872 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt @@ -0,0 +1,37 @@ +* ARM SMMUv3 Architecture Implementation + +The SMMUv3 architecture is a significant deparature from previous +revisions, replacing the MMIO register interface with in-memory command +and event queues and adding support for the ATS and PRI components of +the PCIe specification. + +** SMMUv3 required properties: + +- compatible : Should include: + + * "arm,smmu-v3" for any SMMUv3 compliant + implementation. This entry should be last in the + compatible list. + +- reg : Base address and size of the SMMU. + +- interrupts : Non-secure interrupt list describing the wired + interrupt sources corresponding to entries in + interrupt-names. If no wired interrupts are + present then this property may be omitted. + +- interrupt-names : When the interrupts property is present, should + include the following: + * "eventq" - Event Queue not empty + * "priq" - PRI Queue not empty + * "cmdq-sync" - CMD_SYNC complete + * "gerror" - Global Error activated + +** SMMUv3 optional properties: + +- dma-coherent : Present if DMA operations made by the SMMU (page + table walks, stream table accesses etc) are cache + coherent with the CPU. + + NOTE: this only applies to the SMMU itself, not + masters connected upstream of the SMMU. -- 2.1.4 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 1/3] Documentation: dt-bindings: Add device-tree binding for ARM SMMUv3 IOMMU @ 2015-05-08 18:00 ` Will Deacon 0 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-08 18:00 UTC (permalink / raw) To: linux-arm-kernel This patch adds device-tree bindings for ARM SMMUv3 IOMMU devices. Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> --- .../devicetree/bindings/iommu/arm,smmu-v3.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt new file mode 100644 index 000000000000..c03eec116872 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt @@ -0,0 +1,37 @@ +* ARM SMMUv3 Architecture Implementation + +The SMMUv3 architecture is a significant deparature from previous +revisions, replacing the MMIO register interface with in-memory command +and event queues and adding support for the ATS and PRI components of +the PCIe specification. + +** SMMUv3 required properties: + +- compatible : Should include: + + * "arm,smmu-v3" for any SMMUv3 compliant + implementation. This entry should be last in the + compatible list. + +- reg : Base address and size of the SMMU. + +- interrupts : Non-secure interrupt list describing the wired + interrupt sources corresponding to entries in + interrupt-names. If no wired interrupts are + present then this property may be omitted. + +- interrupt-names : When the interrupts property is present, should + include the following: + * "eventq" - Event Queue not empty + * "priq" - PRI Queue not empty + * "cmdq-sync" - CMD_SYNC complete + * "gerror" - Global Error activated + +** SMMUv3 optional properties: + +- dma-coherent : Present if DMA operations made by the SMMU (page + table walks, stream table accesses etc) are cache + coherent with the CPU. + + NOTE: this only applies to the SMMU itself, not + masters connected upstream of the SMMU. -- 2.1.4 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-05-08 18:00 ` Will Deacon @ 2015-05-08 18:00 ` Will Deacon -1 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-08 18:00 UTC (permalink / raw) To: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA Cc: Will Deacon, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Version three of the ARM SMMU architecture introduces significant changes and improvements over previous versions of the specification, necessitating a new driver in the Linux kernel. The main change to the programming interface is that the majority of the configuration data has been moved from MMIO registers to in-memory data structures, with communication between the CPU and the SMMU being mediated via in-memory circular queues. This patch adds an initial driver for SMMUv3 to Linux. We currently support pinned stage-1 (DMA) and stage-2 (KVM VFIO) mappings using the generic IO-pgtable code. Cc: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> Signed-off-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> --- MAINTAINERS | 3 +- drivers/iommu/Kconfig | 13 + drivers/iommu/Makefile | 1 + drivers/iommu/arm-smmu-v3.c | 2599 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 2615 insertions(+), 1 deletion(-) create mode 100644 drivers/iommu/arm-smmu-v3.c diff --git a/MAINTAINERS b/MAINTAINERS index 2e5bbc0d68b2..ad1acacba393 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1619,11 +1619,12 @@ F: drivers/i2c/busses/i2c-cadence.c F: drivers/mmc/host/sdhci-of-arasan.c F: drivers/edac/synopsys_edac.c -ARM SMMU DRIVER +ARM SMMU DRIVERS M: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> L: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated for non-subscribers) S: Maintained F: drivers/iommu/arm-smmu.c +F: drivers/iommu/arm-smmu-v3.c F: drivers/iommu/io-pgtable-arm.c ARM64 PORT (AARCH64 ARCHITECTURE) diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 1ae4e547b419..40f37a2b4a8a 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -339,6 +339,7 @@ config SPAPR_TCE_IOMMU Enables bits of IOMMU API required by VFIO. The iommu_ops is not implemented as it is not necessary for VFIO. +# ARM IOMMU support config ARM_SMMU bool "ARM Ltd. System MMU (SMMU) Support" depends on (ARM64 || ARM) && MMU @@ -352,4 +353,16 @@ config ARM_SMMU Say Y here if your SoC includes an IOMMU device implementing the ARM SMMU architecture. +config ARM_SMMU_V3 + bool "ARM Ltd. System MMU Version 3 (SMMUv3) Support" + depends on ARM64 && PCI + select IOMMU_API + select IOMMU_IO_PGTABLE_LPAE + help + Support for implementations of the ARM System MMU architecture + version 3 providing translation support to a PCIe root complex. + + Say Y here if your system includes an IOMMU device implementing + the ARM SMMUv3 architecture. + endif # IOMMU_SUPPORT diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 080ffab4ed1c..c6dcc513d711 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o msm_iommu_dev.o obj-$(CONFIG_AMD_IOMMU) += amd_iommu.o amd_iommu_init.o obj-$(CONFIG_AMD_IOMMU_V2) += amd_iommu_v2.o obj-$(CONFIG_ARM_SMMU) += arm-smmu.o +obj-$(CONFIG_ARM_SMMU_V3) += arm-smmu-v3.o obj-$(CONFIG_DMAR_TABLE) += dmar.o obj-$(CONFIG_INTEL_IOMMU) += intel-iommu.o obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c new file mode 100644 index 000000000000..c471000e5d3c --- /dev/null +++ b/drivers/iommu/arm-smmu-v3.c @@ -0,0 +1,2599 @@ +/* + * IOMMU API for ARM architected SMMUv3 implementations. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * Copyright (C) 2015 ARM Limited + * + * Author: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> + * + * This driver is powered by bad coffee and bombay mix. + */ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/iommu.h> +#include <linux/iopoll.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/pci.h> +#include <linux/platform_device.h> + +#include "io-pgtable.h" + +/* MMIO registers */ +#define ARM_SMMU_IDR0 0x0 +#define IDR0_ST_LVL_SHIFT 27 +#define IDR0_ST_LVL_MASK 0x3 +#define IDR0_ST_LVL_2LVL (1 << IDR0_ST_LVL_SHIFT) +#define IDR0_STALL_MODEL (3 << 24) +#define IDR0_TTENDIAN_SHIFT 21 +#define IDR0_TTENDIAN_MASK 0x3 +#define IDR0_TTENDIAN_LE (2 << IDR0_TTENDIAN_SHIFT) +#define IDR0_TTENDIAN_BE (3 << IDR0_TTENDIAN_SHIFT) +#define IDR0_TTENDIAN_MIXED (0 << IDR0_TTENDIAN_SHIFT) +#define IDR0_CD2L (1 << 19) +#define IDR0_VMID16 (1 << 18) +#define IDR0_PRI (1 << 16) +#define IDR0_SEV (1 << 14) +#define IDR0_MSI (1 << 13) +#define IDR0_ASID16 (1 << 12) +#define IDR0_ATS (1 << 10) +#define IDR0_COHACC (1 << 4) +#define IDR0_TTF_SHIFT 2 +#define IDR0_TTF_MASK 0x3 +#define IDR0_TTF_AARCH64 (2 << IDR0_TTF_SHIFT) +#define IDR0_S1P (1 << 1) +#define IDR0_S2P (1 << 0) + +#define ARM_SMMU_IDR1 0x4 +#define IDR1_TABLES_PRESET (1 << 30) +#define IDR1_QUEUES_PRESET (1 << 29) +#define IDR1_REL (1 << 28) +#define IDR1_CMDQ_SHIFT 21 +#define IDR1_CMDQ_MASK 0x1f +#define IDR1_EVTQ_SHIFT 16 +#define IDR1_EVTQ_MASK 0x1f +#define IDR1_PRIQ_SHIFT 11 +#define IDR1_PRIQ_MASK 0x1f +#define IDR1_SSID_SHIFT 6 +#define IDR1_SSID_MASK 0x1f +#define IDR1_SID_SHIFT 0 +#define IDR1_SID_MASK 0x3f + +#define ARM_SMMU_IDR5 0x14 +#define IDR5_STALL_MAX_SHIFT 16 +#define IDR5_STALL_MAX_MASK 0xffff +#define IDR5_GRAN64K (1 << 6) +#define IDR5_GRAN16K (1 << 5) +#define IDR5_GRAN4K (1 << 4) +#define IDR5_OAS_SHIFT 0 +#define IDR5_OAS_MASK 0x7 +#define IDR5_OAS_32_BIT (0 << IDR5_OAS_SHIFT) +#define IDR5_OAS_36_BIT (1 << IDR5_OAS_SHIFT) +#define IDR5_OAS_40_BIT (2 << IDR5_OAS_SHIFT) +#define IDR5_OAS_42_BIT (3 << IDR5_OAS_SHIFT) +#define IDR5_OAS_44_BIT (4 << IDR5_OAS_SHIFT) +#define IDR5_OAS_48_BIT (5 << IDR5_OAS_SHIFT) + +#define ARM_SMMU_CR0 0x20 +#define CR0_CMDQEN (1 << 3) +#define CR0_EVTQEN (1 << 2) +#define CR0_PRIQEN (1 << 1) +#define CR0_SMMUEN (1 << 0) + +#define ARM_SMMU_CR0ACK 0x24 + +#define ARM_SMMU_CR1 0x28 +#define CR1_SH_NSH 0 +#define CR1_SH_OSH 2 +#define CR1_SH_ISH 3 +#define CR1_CACHE_NC 0 +#define CR1_CACHE_WB 1 +#define CR1_CACHE_WT 2 +#define CR1_TABLE_SH_SHIFT 10 +#define CR1_TABLE_OC_SHIFT 8 +#define CR1_TABLE_IC_SHIFT 6 +#define CR1_QUEUE_SH_SHIFT 4 +#define CR1_QUEUE_OC_SHIFT 2 +#define CR1_QUEUE_IC_SHIFT 0 + +#define ARM_SMMU_CR2 0x2c +#define CR2_PTM (1 << 2) +#define CR2_RECINVMID (1 << 1) +#define CR2_E2H (1 << 0) + +#define ARM_SMMU_IRQ_CTRL 0x50 +#define IRQ_CTRL_EVTQ_IRQEN (1 << 2) +#define IRQ_CTRL_GERROR_IRQEN (1 << 0) + +#define ARM_SMMU_IRQ_CTRLACK 0x54 + +#define ARM_SMMU_GERROR 0x60 +#define GERROR_SFM_ERR (1 << 8) +#define GERROR_MSI_GERROR_ABT_ERR (1 << 7) +#define GERROR_MSI_PRIQ_ABT_ERR (1 << 6) +#define GERROR_MSI_EVTQ_ABT_ERR (1 << 5) +#define GERROR_MSI_CMDQ_ABT_ERR (1 << 4) +#define GERROR_PRIQ_ABT_ERR (1 << 3) +#define GERROR_EVTQ_ABT_ERR (1 << 2) +#define GERROR_CMDQ_ERR (1 << 0) +#define GERROR_ERR_MASK 0xfd + +#define ARM_SMMU_GERRORN 0x64 + +#define ARM_SMMU_GERROR_IRQ_CFG0 0x68 +#define ARM_SMMU_GERROR_IRQ_CFG1 0x70 +#define ARM_SMMU_GERROR_IRQ_CFG2 0x74 + +#define ARM_SMMU_STRTAB_BASE 0x80 +#define STRTAB_BASE_RA (1UL << 62) +#define STRTAB_BASE_ADDR_SHIFT 6 +#define STRTAB_BASE_ADDR_MASK 0x3ffffffffffUL + +#define ARM_SMMU_STRTAB_BASE_CFG 0x88 +#define STRTAB_BASE_CFG_LOG2SIZE_SHIFT 0 +#define STRTAB_BASE_CFG_LOG2SIZE_MASK 0x3f +#define STRTAB_BASE_CFG_SPLIT_SHIFT 6 +#define STRTAB_BASE_CFG_SPLIT_MASK 0x1f +#define STRTAB_BASE_CFG_FMT_SHIFT 16 +#define STRTAB_BASE_CFG_FMT_MASK 0x3 +#define STRTAB_BASE_CFG_FMT_LINEAR (0 << STRTAB_BASE_CFG_FMT_SHIFT) +#define STRTAB_BASE_CFG_FMT_2LVL (1 << STRTAB_BASE_CFG_FMT_SHIFT) + +#define ARM_SMMU_CMDQ_BASE 0x90 +#define ARM_SMMU_CMDQ_PROD 0x98 +#define ARM_SMMU_CMDQ_CONS 0x9c + +#define ARM_SMMU_EVTQ_BASE 0xa0 +#define ARM_SMMU_EVTQ_PROD 0x100a8 +#define ARM_SMMU_EVTQ_CONS 0x100ac +#define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0 +#define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8 +#define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc + +#define ARM_SMMU_PRIQ_BASE 0xc0 +#define ARM_SMMU_PRIQ_PROD 0x100c8 +#define ARM_SMMU_PRIQ_CONS 0x100cc +#define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0 +#define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 +#define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc + +/* Common MSI config fields */ +#define MSI_CFG0_SH_SHIFT 60 +#define MSI_CFG0_SH_NSH (0UL << MSI_CFG0_SH_SHIFT) +#define MSI_CFG0_SH_OSH (2UL << MSI_CFG0_SH_SHIFT) +#define MSI_CFG0_SH_ISH (3UL << MSI_CFG0_SH_SHIFT) +#define MSI_CFG0_MEMATTR_SHIFT 56 +#define MSI_CFG0_MEMATTR_DEVICE_nGnRE (0x1 << MSI_CFG0_MEMATTR_SHIFT) +#define MSI_CFG0_ADDR_SHIFT 2 +#define MSI_CFG0_ADDR_MASK 0x3fffffffffffUL + +#define Q_IDX(q, p) ((p) & ((1 << (q)->max_n_shift) - 1)) +#define Q_WRP(q, p) ((p) & (1 << (q)->max_n_shift)) +#define Q_OVERFLOW_FLAG (1 << 31) +#define Q_OVF(q, p) ((p) & Q_OVERFLOW_FLAG) +#define Q_ENT(q, p) ((q)->base + \ + Q_IDX(q, p) * (q)->ent_dwords) + +#define Q_BASE_RWA (1UL << 62) +#define Q_BASE_ADDR_SHIFT 5 +#define Q_BASE_ADDR_MASK 0xfffffffffffUL +#define Q_BASE_LOG2SIZE_SHIFT 0 +#define Q_BASE_LOG2SIZE_MASK 0x1fUL + +/* + * Stream table. + * + * Linear: 128 STEs + * 2lvl: 1024 L1 entries, 64 entries per table (covers a PCI host controller) + */ +#define STRTAB_L1_SZ_SHIFT 13 +#define STRTAB_SPLIT 6 + +#define STRTAB_L1_DESC_DWORDS 1 +#define STRTAB_L1_DESC_SPAN_SHIFT 0 +#define STRTAB_L1_DESC_SPAN_MASK 0x1fUL +#define STRTAB_L1_DESC_L2PTR_SHIFT 6 +#define STRTAB_L1_DESC_L2PTR_MASK 0x3ffffffffffUL + +#define STRTAB_STE_DWORDS 8 +#define STRTAB_STE_0_V (1UL << 0) +#define STRTAB_STE_0_CFG_SHIFT 1 +#define STRTAB_STE_0_CFG_MASK 0x7UL +#define STRTAB_STE_0_CFG_FAULT (0UL << STRTAB_STE_0_CFG_SHIFT) +#define STRTAB_STE_0_CFG_BYPASS (4UL << STRTAB_STE_0_CFG_SHIFT) +#define STRTAB_STE_0_CFG_S1_TRANS (5UL << STRTAB_STE_0_CFG_SHIFT) +#define STRTAB_STE_0_CFG_S2_TRANS (6UL << STRTAB_STE_0_CFG_SHIFT) + +#define STRTAB_STE_0_S1FMT_SHIFT 4 +#define STRTAB_STE_0_S1FMT_LINEAR (0UL << STRTAB_STE_0_S1FMT_SHIFT) +#define STRTAB_STE_0_S1CTXPTR_SHIFT 6 +#define STRTAB_STE_0_S1CTXPTR_MASK 0x3ffffffffffUL +#define STRTAB_STE_0_S1CDMAX_SHIFT 59 +#define STRTAB_STE_0_S1CDMAX_MASK 0x1fUL + +#define STRTAB_STE_1_S1C_CACHE_NC 0UL +#define STRTAB_STE_1_S1C_CACHE_WBRA 1UL +#define STRTAB_STE_1_S1C_CACHE_WT 2UL +#define STRTAB_STE_1_S1C_CACHE_WB 3UL +#define STRTAB_STE_1_S1C_SH_NSH 0UL +#define STRTAB_STE_1_S1C_SH_OSH 2UL +#define STRTAB_STE_1_S1C_SH_ISH 3UL +#define STRTAB_STE_1_S1CIR_SHIFT 2 +#define STRTAB_STE_1_S1COR_SHIFT 4 +#define STRTAB_STE_1_S1CSH_SHIFT 6 + +#define STRTAB_STE_1_S1STALLD (1UL << 27) + +#define STRTAB_STE_1_EATS_ABT 0UL +#define STRTAB_STE_1_EATS_TRANS 1UL +#define STRTAB_STE_1_EATS_S1CHK 2UL +#define STRTAB_STE_1_EATS_SHIFT 28 + +#define STRTAB_STE_1_STRW_NSEL1 0UL +#define STRTAB_STE_1_STRW_EL2 2UL +#define STRTAB_STE_1_STRW_SHIFT 30 + +#define STRTAB_STE_2_S2VMID_SHIFT 0 +#define STRTAB_STE_2_S2VMID_MASK 0xffffUL +#define STRTAB_STE_2_VTCR_SHIFT 32 +#define STRTAB_STE_2_VTCR_MASK 0x7ffffUL +#define STRTAB_STE_2_S2AA64 (1UL << 51) +#define STRTAB_STE_2_S2ENDI (1UL << 52) +#define STRTAB_STE_2_S2PTW (1UL << 54) +#define STRTAB_STE_2_S2R (1UL << 58) + +#define STRTAB_STE_3_S2TTB_SHIFT 4 +#define STRTAB_STE_3_S2TTB_MASK 0xfffffffffffUL + +/* Context descriptor (stage-1 only) */ +#define CTXDESC_CD_DWORDS 8 +#define CTXDESC_CD_0_TCR_T0SZ_SHIFT 0 +#define ARM64_TCR_T0SZ_SHIFT 0 +#define ARM64_TCR_T0SZ_MASK 0x1fUL +#define CTXDESC_CD_0_TCR_TG0_SHIFT 6 +#define ARM64_TCR_TG0_SHIFT 14 +#define ARM64_TCR_TG0_MASK 0x3UL +#define CTXDESC_CD_0_TCR_IRGN0_SHIFT 8 +#define ARM64_TCR_IRGN0_SHIFT 24 +#define ARM64_TCR_IRGN0_MASK 0x3UL +#define CTXDESC_CD_0_TCR_ORGN0_SHIFT 10 +#define ARM64_TCR_ORGN0_SHIFT 26 +#define ARM64_TCR_ORGN0_MASK 0x3UL +#define CTXDESC_CD_0_TCR_SH0_SHIFT 12 +#define ARM64_TCR_SH0_SHIFT 12 +#define ARM64_TCR_SH0_MASK 0x3UL +#define CTXDESC_CD_0_TCR_EPD0_SHIFT 14 +#define ARM64_TCR_EPD0_SHIFT 7 +#define ARM64_TCR_EPD0_MASK 0x1UL +#define CTXDESC_CD_0_TCR_EPD1_SHIFT 30 +#define ARM64_TCR_EPD1_SHIFT 23 +#define ARM64_TCR_EPD1_MASK 0x1UL + +#define CTXDESC_CD_0_ENDI (1UL << 15) +#define CTXDESC_CD_0_V (1UL << 31) + +#define CTXDESC_CD_0_TCR_IPS_SHIFT 32 +#define ARM64_TCR_IPS_SHIFT 32 +#define ARM64_TCR_IPS_MASK 0x7UL +#define CTXDESC_CD_0_TCR_TBI0_SHIFT 38 +#define ARM64_TCR_TBI0_SHIFT 37 +#define ARM64_TCR_TBI0_MASK 0x1UL + +#define CTXDESC_CD_0_AA64 (1UL << 41) +#define CTXDESC_CD_0_R (1UL << 45) +#define CTXDESC_CD_0_A (1UL << 46) +#define CTXDESC_CD_0_ASET_SHIFT 47 +#define CTXDESC_CD_0_ASET_SHARED (0UL << CTXDESC_CD_0_ASET_SHIFT) +#define CTXDESC_CD_0_ASET_PRIVATE (1UL << CTXDESC_CD_0_ASET_SHIFT) +#define CTXDESC_CD_0_ASID_SHIFT 48 +#define CTXDESC_CD_0_ASID_MASK 0xffffUL + +#define CTXDESC_CD_1_TTB0_SHIFT 4 +#define CTXDESC_CD_1_TTB0_MASK 0xfffffffffffUL + +#define CTXDESC_CD_3_MAIR_SHIFT 0 + +/* Convert between AArch64 (CPU) TCR format and SMMU CD format */ +#define ARM_SMMU_TCR2CD(tcr, fld) \ + (((tcr) >> ARM64_TCR_##fld##_SHIFT & ARM64_TCR_##fld##_MASK) \ + << CTXDESC_CD_0_TCR_##fld##_SHIFT) + +/* Command queue */ +#define CMDQ_ENT_DWORDS 2 +#define CMDQ_MAX_SZ_SHIFT 8 + +#define CMDQ_ERR_SHIFT 24 +#define CMDQ_ERR_MASK 0x7f +#define CMDQ_ERR_CERROR_NONE_IDX 0 +#define CMDQ_ERR_CERROR_ILL_IDX 1 +#define CMDQ_ERR_CERROR_ABT_IDX 2 + +#define CMDQ_0_OP_SHIFT 0 +#define CMDQ_0_OP_MASK 0xffUL +#define CMDQ_0_SSV (1UL << 11) + +#define CMDQ_PREFETCH_0_SID_SHIFT 32 +#define CMDQ_PREFETCH_1_SIZE_SHIFT 0 +#define CMDQ_PREFETCH_1_ADDR_MASK ~0xfffUL + +#define CMDQ_CFGI_0_SID_SHIFT 32 +#define CMDQ_CFGI_0_SID_MASK 0xffffffffUL +#define CMDQ_CFGI_1_LEAF (1UL << 0) +#define CMDQ_CFGI_1_RANGE_SHIFT 0 +#define CMDQ_CFGI_1_RANGE_MASK 0x1fUL + +#define CMDQ_TLBI_0_VMID_SHIFT 32 +#define CMDQ_TLBI_0_ASID_SHIFT 48 +#define CMDQ_TLBI_1_LEAF (1UL << 0) +#define CMDQ_TLBI_1_ADDR_MASK ~0xfffUL + +#define CMDQ_PRI_0_SSID_SHIFT 12 +#define CMDQ_PRI_0_SSID_MASK 0xfffffUL +#define CMDQ_PRI_0_SID_SHIFT 32 +#define CMDQ_PRI_0_SID_MASK 0xffffffffUL +#define CMDQ_PRI_1_GRPID_SHIFT 0 +#define CMDQ_PRI_1_GRPID_MASK 0x1ffUL +#define CMDQ_PRI_1_RESP_SHIFT 12 +#define CMDQ_PRI_1_RESP_DENY (0UL << CMDQ_PRI_1_RESP_SHIFT) +#define CMDQ_PRI_1_RESP_FAIL (1UL << CMDQ_PRI_1_RESP_SHIFT) +#define CMDQ_PRI_1_RESP_SUCC (2UL << CMDQ_PRI_1_RESP_SHIFT) + +#define CMDQ_SYNC_0_CS_SHIFT 12 +#define CMDQ_SYNC_0_CS_NONE (0UL << CMDQ_SYNC_0_CS_SHIFT) +#define CMDQ_SYNC_0_CS_SEV (2UL << CMDQ_SYNC_0_CS_SHIFT) + +/* Event queue */ +#define EVTQ_ENT_DWORDS 4 +#define EVTQ_MAX_SZ_SHIFT 7 + +#define EVTQ_0_ID_SHIFT 0 +#define EVTQ_0_ID_MASK 0xffUL + +/* PRI queue */ +#define PRIQ_ENT_DWORDS 2 +#define PRIQ_MAX_SZ_SHIFT 8 + +#define PRIQ_0_SID_SHIFT 0 +#define PRIQ_0_SID_MASK 0xffffffffUL +#define PRIQ_0_SSID_SHIFT 32 +#define PRIQ_0_SSID_MASK 0xfffffUL +#define PRIQ_0_OF (1UL << 57) +#define PRIQ_0_PERM_PRIV (1UL << 58) +#define PRIQ_0_PERM_EXEC (1UL << 59) +#define PRIQ_0_PERM_READ (1UL << 60) +#define PRIQ_0_PERM_WRITE (1UL << 61) +#define PRIQ_0_PRG_LAST (1UL << 62) +#define PRIQ_0_SSID_V (1UL << 63) + +#define PRIQ_1_PRG_IDX_SHIFT 0 +#define PRIQ_1_PRG_IDX_MASK 0x1ffUL +#define PRIQ_1_ADDR_SHIFT 12 +#define PRIQ_1_ADDR_MASK 0xfffffffffffffUL + +/* High-level queue structures */ +#define ARM_SMMU_POLL_TIMEOUT_US 100 + +enum pri_resp { + PRI_RESP_DENY, + PRI_RESP_FAIL, + PRI_RESP_SUCC, +}; + +struct arm_smmu_cmdq_ent { + /* Common fields */ + u8 opcode; + bool substream_valid; + + /* Command-specific fields */ + union { + #define CMDQ_OP_PREFETCH_CFG 0x1 + struct { + u32 sid; + u8 size; + u64 addr; + } prefetch; + + #define CMDQ_OP_CFGI_STE 0x3 + #define CMDQ_OP_CFGI_ALL 0x4 + struct { + u32 sid; + union { + bool leaf; + u8 span; + }; + } cfgi; + + #define CMDQ_OP_TLBI_NH_ASID 0x11 + #define CMDQ_OP_TLBI_NH_VA 0x12 + #define CMDQ_OP_TLBI_EL2_ALL 0x20 + #define CMDQ_OP_TLBI_S12_VMALL 0x28 + #define CMDQ_OP_TLBI_S2_IPA 0x2a + #define CMDQ_OP_TLBI_NSNH_ALL 0x30 + struct { + u16 asid; + u16 vmid; + bool leaf; + u64 addr; + } tlbi; + + #define CMDQ_OP_PRI_RESP 0x41 + struct { + u32 sid; + u32 ssid; + u16 grpid; + enum pri_resp resp; + } pri; + + #define CMDQ_OP_CMD_SYNC 0x46 + }; +}; + +struct arm_smmu_queue { + int irq; /* Wired interrupt */ + + __le64 *base; + dma_addr_t base_dma; + u64 q_base; + + size_t ent_dwords; + u32 max_n_shift; + u32 prod; + u32 cons; + + u32 __iomem *prod_reg; + u32 __iomem *cons_reg; +}; + +struct arm_smmu_cmdq { + struct arm_smmu_queue q; + spinlock_t lock; +}; + +struct arm_smmu_evtq { + struct arm_smmu_queue q; + u32 max_stalls; +}; + +struct arm_smmu_priq { + struct arm_smmu_queue q; +}; + +/* High-level stream table and context descriptor structures */ +struct arm_smmu_strtab_l1_desc { + u8 span; + + __le64 *l2ptr; + dma_addr_t l2ptr_dma; +}; + +struct arm_smmu_s1_cfg { + __le64 *cdptr; + dma_addr_t cdptr_dma; + + struct arm_smmu_ctx_desc { + u16 asid; + u64 ttbr; + u64 tcr; + u64 mair; + } cd; +}; + +struct arm_smmu_s2_cfg { + u16 vmid; + u64 vttbr; + u64 vtcr; +}; + +struct arm_smmu_strtab_ent { + bool valid; + + bool bypass; /* Overrides s1/s2 config */ + struct arm_smmu_s1_cfg *s1_cfg; + struct arm_smmu_s2_cfg *s2_cfg; +}; + +struct arm_smmu_strtab_cfg { + __le64 *strtab; + dma_addr_t strtab_dma; + struct arm_smmu_strtab_l1_desc *l1_desc; + unsigned int num_l1_descs; + + u64 strtab_base; + u32 strtab_base_cfg; +}; + +/* An SMMUv3 instance */ +struct arm_smmu_device { + struct device *dev; + void __iomem *base; + +#define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0) +#define ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1) +#define ARM_SMMU_FEAT_TT_LE (1 << 2) +#define ARM_SMMU_FEAT_TT_BE (1 << 3) +#define ARM_SMMU_FEAT_PRI (1 << 4) +#define ARM_SMMU_FEAT_ATS (1 << 5) +#define ARM_SMMU_FEAT_SEV (1 << 6) +#define ARM_SMMU_FEAT_MSI (1 << 7) +#define ARM_SMMU_FEAT_COHERENCY (1 << 8) +#define ARM_SMMU_FEAT_TRANS_S1 (1 << 9) +#define ARM_SMMU_FEAT_TRANS_S2 (1 << 10) +#define ARM_SMMU_FEAT_STALLS (1 << 11) + u32 features; + + struct arm_smmu_cmdq cmdq; + struct arm_smmu_evtq evtq; + struct arm_smmu_priq priq; + + int gerr_irq; + + unsigned long ias; /* IPA */ + unsigned long oas; /* PA */ + +#define ARM_SMMU_MAX_ASIDS (1 << 16) + unsigned int asid_bits; + DECLARE_BITMAP(asid_map, ARM_SMMU_MAX_ASIDS); + +#define ARM_SMMU_MAX_VMIDS (1 << 16) + unsigned int vmid_bits; + DECLARE_BITMAP(vmid_map, ARM_SMMU_MAX_VMIDS); + + unsigned int ssid_bits; + unsigned int sid_bits; + + struct arm_smmu_strtab_cfg strtab_cfg; + struct list_head list; +}; + +/* SMMU private data for an IOMMU group */ +struct arm_smmu_group { + struct arm_smmu_device *smmu; + struct arm_smmu_domain *domain; + int num_sids; + u32 *sids; + struct arm_smmu_strtab_ent ste; +}; + +/* SMMU private data for an IOMMU domain */ +enum arm_smmu_domain_stage { + ARM_SMMU_DOMAIN_S1 = 0, + ARM_SMMU_DOMAIN_S2, + ARM_SMMU_DOMAIN_NESTED, +}; + +struct arm_smmu_domain { + struct arm_smmu_device *smmu; + struct mutex init_mutex; /* Protects smmu pointer */ + + struct io_pgtable_ops *pgtbl_ops; + spinlock_t pgtbl_lock; + + enum arm_smmu_domain_stage stage; + union { + struct arm_smmu_s1_cfg s1_cfg; + struct arm_smmu_s2_cfg s2_cfg; + }; + + struct iommu_domain domain; +}; + +/* Our list of SMMU instances */ +static DEFINE_SPINLOCK(arm_smmu_devices_lock); +static LIST_HEAD(arm_smmu_devices); + +static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) +{ + return container_of(dom, struct arm_smmu_domain, domain); +} + +/* Low-level queue manipulation functions */ +static bool queue_full(struct arm_smmu_queue *q) +{ + return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) && + Q_WRP(q, q->prod) != Q_WRP(q, q->cons); +} + +static bool queue_empty(struct arm_smmu_queue *q) +{ + return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) && + Q_WRP(q, q->prod) == Q_WRP(q, q->cons); +} + +static void queue_sync_cons(struct arm_smmu_queue *q) +{ + q->cons = readl_relaxed(q->cons_reg); +} + +static void queue_inc_cons(struct arm_smmu_queue *q) +{ + u32 cons = (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1; + + q->cons = Q_OVF(q, q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons); + writel(q->cons, q->cons_reg); +} + +static int queue_sync_prod(struct arm_smmu_queue *q) +{ + int ret = 0; + u32 prod = readl_relaxed(q->prod_reg); + + if (Q_OVF(q, prod) != Q_OVF(q, q->prod)) + ret = -EOVERFLOW; + + q->prod = prod; + return ret; +} + +static void queue_inc_prod(struct arm_smmu_queue *q) +{ + u32 prod = (Q_WRP(q, q->prod) | Q_IDX(q, q->prod)) + 1; + + q->prod = Q_OVF(q, q->prod) | Q_WRP(q, prod) | Q_IDX(q, prod); + writel(q->prod, q->prod_reg); +} + +static bool __queue_cons_before(struct arm_smmu_queue *q, u32 until) +{ + if (Q_WRP(q, q->cons) == Q_WRP(q, until)) + return Q_IDX(q, q->cons) < Q_IDX(q, until); + + return Q_IDX(q, q->cons) >= Q_IDX(q, until); +} + +static int queue_poll_cons(struct arm_smmu_queue *q, u32 until, bool wfe) +{ + ktime_t timeout = ktime_add_us(ktime_get(), ARM_SMMU_POLL_TIMEOUT_US); + + while (queue_sync_cons(q), __queue_cons_before(q, until)) { + if (ktime_compare(ktime_get(), timeout) > 0) + return -ETIMEDOUT; + + if (wfe) { + wfe(); + } else { + cpu_relax(); + udelay(1); + } + } + + return 0; +} + +static void queue_write(__le64 *dst, u64 *src, size_t n_dwords) +{ + int i; + + for (i = 0; i < n_dwords; ++i) + *dst++ = cpu_to_le64(*src++); +} + +static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent) +{ + if (queue_full(q)) + return -ENOSPC; + + queue_write(Q_ENT(q, q->prod), ent, q->ent_dwords); + queue_inc_prod(q); + return 0; +} + +static void queue_read(__le64 *dst, u64 *src, size_t n_dwords) +{ + int i; + + for (i = 0; i < n_dwords; ++i) + *dst++ = le64_to_cpu(*src++); +} + +static int queue_remove_raw(struct arm_smmu_queue *q, u64 *ent) +{ + if (queue_empty(q)) + return -EAGAIN; + + queue_read(ent, Q_ENT(q, q->cons), q->ent_dwords); + queue_inc_cons(q); + return 0; +} + +/* High-level queue accessors */ +static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) +{ + memset(cmd, 0, CMDQ_ENT_DWORDS << 3); + cmd[0] |= (ent->opcode & CMDQ_0_OP_MASK) << CMDQ_0_OP_SHIFT; + + switch (ent->opcode) { + case CMDQ_OP_TLBI_EL2_ALL: + case CMDQ_OP_TLBI_NSNH_ALL: + break; + case CMDQ_OP_PREFETCH_CFG: + cmd[0] |= (u64)ent->prefetch.sid << CMDQ_PREFETCH_0_SID_SHIFT; + cmd[1] |= ent->prefetch.size << CMDQ_PREFETCH_1_SIZE_SHIFT; + cmd[1] |= ent->prefetch.addr & CMDQ_PREFETCH_1_ADDR_MASK; + break; + case CMDQ_OP_CFGI_STE: + cmd[0] |= (u64)ent->cfgi.sid << CMDQ_CFGI_0_SID_SHIFT; + cmd[1] |= ent->cfgi.leaf ? CMDQ_CFGI_1_LEAF : 0; + break; + case CMDQ_OP_CFGI_ALL: + /* Cover the entire SID range */ + cmd[1] |= CMDQ_CFGI_1_RANGE_MASK << CMDQ_CFGI_1_RANGE_SHIFT; + break; + case CMDQ_OP_TLBI_NH_VA: + cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT; + /* Fallthrough */ + case CMDQ_OP_TLBI_S2_IPA: + cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT; + cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0; + cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_ADDR_MASK; + break; + case CMDQ_OP_TLBI_NH_ASID: + cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT; + /* Fallthrough */ + case CMDQ_OP_TLBI_S12_VMALL: + cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT; + break; + case CMDQ_OP_PRI_RESP: + cmd[0] |= ent->substream_valid ? CMDQ_0_SSV : 0; + cmd[0] |= ent->pri.ssid << CMDQ_PRI_0_SSID_SHIFT; + cmd[0] |= (u64)ent->pri.sid << CMDQ_PRI_0_SID_SHIFT; + cmd[1] |= ent->pri.grpid << CMDQ_PRI_1_GRPID_SHIFT; + switch (ent->pri.resp) { + case PRI_RESP_DENY: + cmd[1] |= CMDQ_PRI_1_RESP_DENY; + break; + case PRI_RESP_FAIL: + cmd[1] |= CMDQ_PRI_1_RESP_FAIL; + break; + case PRI_RESP_SUCC: + cmd[1] |= CMDQ_PRI_1_RESP_SUCC; + break; + default: + return -EINVAL; + } + break; + case CMDQ_OP_CMD_SYNC: + cmd[0] |= CMDQ_SYNC_0_CS_SEV; + break; + default: + return -ENOENT; + } + + return 0; +} + +static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) +{ + static const char *cerror_str[] = { + [CMDQ_ERR_CERROR_NONE_IDX] = "No error", + [CMDQ_ERR_CERROR_ILL_IDX] = "Illegal command", + [CMDQ_ERR_CERROR_ABT_IDX] = "Abort on command fetch", + }; + + int i; + u64 cmd[CMDQ_ENT_DWORDS]; + struct arm_smmu_queue *q = &smmu->cmdq.q; + u32 cons = readl_relaxed(q->cons_reg); + u32 idx = cons >> CMDQ_ERR_SHIFT & CMDQ_ERR_MASK; + struct arm_smmu_cmdq_ent cmd_sync = { + .opcode = CMDQ_OP_CMD_SYNC, + }; + + dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, + cerror_str[idx]); + + switch (idx) { + case CMDQ_ERR_CERROR_ILL_IDX: + break; + case CMDQ_ERR_CERROR_ABT_IDX: + dev_err(smmu->dev, "retrying command fetch\n"); + case CMDQ_ERR_CERROR_NONE_IDX: + return; + } + + /* + * We may have concurrent producers, so we need to be careful + * not to touch any of the shadow cmdq state. + */ + queue_read(cmd, Q_ENT(q, idx), q->ent_dwords); + dev_err(smmu->dev, "skipping command in error state:\n"); + for (i = 0; i < ARRAY_SIZE(cmd); ++i) + dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); + + /* Convert the erroneous command into a CMD_SYNC */ + if (arm_smmu_cmdq_build_cmd(cmd, &cmd_sync)) { + dev_err(smmu->dev, "failed to convert to CMD_SYNC\n"); + return; + } + + queue_write(cmd, Q_ENT(q, idx), q->ent_dwords); +} + +static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_ent *ent) +{ + u32 until; + u64 cmd[CMDQ_ENT_DWORDS]; + bool wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV); + struct arm_smmu_queue *q = &smmu->cmdq.q; + + if (arm_smmu_cmdq_build_cmd(cmd, ent)) { + dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n", + ent->opcode); + return; + } + + spin_lock(&smmu->cmdq.lock); + while (until = q->prod + 1, queue_insert_raw(q, cmd) == -ENOSPC) { + /* + * Keep the queue locked, otherwise the producer could wrap + * twice and we could see a future consumer pointer that looks + * like it's behind us. + */ + if (queue_poll_cons(q, until, wfe)) + dev_err_ratelimited(smmu->dev, "CMDQ timeout\n"); + } + + if (ent->opcode == CMDQ_OP_CMD_SYNC && queue_poll_cons(q, until, wfe)) + dev_err_ratelimited(smmu->dev, "CMD_SYNC timeout\n"); + spin_unlock(&smmu->cmdq.lock); +} + +/* Context descriptor manipulation functions */ +static u64 arm_smmu_cpu_tcr_to_cd(u64 tcr) +{ + u64 val = 0; + + /* Repack the TCR. Just care about TTBR0 for now */ + val |= ARM_SMMU_TCR2CD(tcr, T0SZ); + val |= ARM_SMMU_TCR2CD(tcr, TG0); + val |= ARM_SMMU_TCR2CD(tcr, IRGN0); + val |= ARM_SMMU_TCR2CD(tcr, ORGN0); + val |= ARM_SMMU_TCR2CD(tcr, SH0); + val |= ARM_SMMU_TCR2CD(tcr, EPD0); + val |= ARM_SMMU_TCR2CD(tcr, EPD1); + val |= ARM_SMMU_TCR2CD(tcr, IPS); + val |= ARM_SMMU_TCR2CD(tcr, TBI0); + + return val; +} + +static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu, + struct arm_smmu_s1_cfg *cfg) +{ + u64 val; + + /* + * We don't need to issue any invalidation here, as we'll invalidate + * the STE when installing the new entry anyway. + */ + val = arm_smmu_cpu_tcr_to_cd(cfg->cd.tcr) | +#ifdef __BIG_ENDIAN + CTXDESC_CD_0_ENDI | +#endif + CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET_PRIVATE | + CTXDESC_CD_0_AA64 | (u64)cfg->cd.asid << CTXDESC_CD_0_ASID_SHIFT | + CTXDESC_CD_0_V; + cfg->cdptr[0] = cpu_to_le64(val); + + val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK << CTXDESC_CD_1_TTB0_SHIFT; + cfg->cdptr[1] = cpu_to_le64(val); + + cfg->cdptr[3] = cpu_to_le64(cfg->cd.mair << CTXDESC_CD_3_MAIR_SHIFT); +} + +/* Stream table manipulation functions */ +static void +arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc) +{ + u64 val = 0; + + val |= (desc->span & STRTAB_L1_DESC_SPAN_MASK) + << STRTAB_L1_DESC_SPAN_SHIFT; + val |= desc->l2ptr_dma & + STRTAB_L1_DESC_L2PTR_MASK << STRTAB_L1_DESC_L2PTR_SHIFT; + + *dst = cpu_to_le64(val); +} + +static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) +{ + struct arm_smmu_cmdq_ent cmd = { + .opcode = CMDQ_OP_CFGI_STE, + .cfgi = { + .sid = sid, + .leaf = true, + }, + }; + + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + cmd.opcode = CMDQ_OP_CMD_SYNC; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); +} + +static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid, + __le64 *dst, struct arm_smmu_strtab_ent *ste) +{ + /* + * This is hideously complicated, but we only really care about + * three cases at the moment: + * + * 1. Invalid (all zero) -> bypass (init) + * 2. Bypass -> translation (attach) + * 3. Translation -> bypass (detach) + * + * Given that we can't update the STE atomically and the SMMU + * doesn't read the thing in a defined order, that leaves us + * with the following maintenance requirements: + * + * 1. Update Config, return (init time STEs aren't live) + * 2. Write everything apart from dword 0, sync, write dword 0, sync + * 3. Update Config, sync + */ + u64 val = le64_to_cpu(dst[0]); + bool ste_live = false; + struct arm_smmu_cmdq_ent prefetch_cmd = { + .opcode = CMDQ_OP_PREFETCH_CFG, + .prefetch = { + .sid = sid, + }, + }; + + if (val & STRTAB_STE_0_V) { + u64 cfg; + + cfg = val & STRTAB_STE_0_CFG_MASK << STRTAB_STE_0_CFG_SHIFT; + switch (cfg) { + case STRTAB_STE_0_CFG_BYPASS: + break; + case STRTAB_STE_0_CFG_S1_TRANS: + case STRTAB_STE_0_CFG_S2_TRANS: + ste_live = true; + break; + default: + BUG(); /* STE corruption */ + } + } + + /* Nuke the existing Config, as we're going to rewrite it */ + val &= ~(STRTAB_STE_0_CFG_MASK << STRTAB_STE_0_CFG_SHIFT); + + if (ste->valid) + val |= STRTAB_STE_0_V; + else + val &= ~STRTAB_STE_0_V; + + if (ste->bypass) { + val |= STRTAB_STE_0_CFG_BYPASS; + dst[0] = cpu_to_le64(val); + dst[2] = 0; /* Nuke the VMID */ + if (ste_live) + arm_smmu_sync_ste_for_sid(smmu, sid); + return; + } + + if (ste->s1_cfg) { + BUG_ON(ste_live); + dst[1] = cpu_to_le64( + STRTAB_STE_1_S1C_CACHE_WBRA + << STRTAB_STE_1_S1CIR_SHIFT | + STRTAB_STE_1_S1C_CACHE_WBRA + << STRTAB_STE_1_S1COR_SHIFT | + STRTAB_STE_1_S1C_SH_ISH << STRTAB_STE_1_S1CSH_SHIFT | + STRTAB_STE_1_S1STALLD | +#ifdef CONFIG_PCI_ATS + STRTAB_STE_1_EATS_TRANS << STRTAB_STE_1_EATS_SHIFT | +#endif + STRTAB_STE_1_STRW_NSEL1 << STRTAB_STE_1_STRW_SHIFT); + + val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK + << STRTAB_STE_0_S1CTXPTR_SHIFT) | + STRTAB_STE_0_CFG_S1_TRANS; + + } + + if (ste->s2_cfg) { + BUG_ON(ste_live); + dst[2] = cpu_to_le64( + ste->s2_cfg->vmid << STRTAB_STE_2_S2VMID_SHIFT | + (ste->s2_cfg->vtcr & STRTAB_STE_2_VTCR_MASK) + << STRTAB_STE_2_VTCR_SHIFT | +#ifdef __BIG_ENDIAN + STRTAB_STE_2_S2ENDI | +#endif + STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 | + STRTAB_STE_2_S2R); + + dst[3] = cpu_to_le64(ste->s2_cfg->vttbr & + STRTAB_STE_3_S2TTB_MASK << STRTAB_STE_3_S2TTB_SHIFT); + + val |= STRTAB_STE_0_CFG_S2_TRANS; + } + + arm_smmu_sync_ste_for_sid(smmu, sid); + dst[0] = cpu_to_le64(val); + arm_smmu_sync_ste_for_sid(smmu, sid); + + /* It's likely that we'll want to use the new STE soon */ + arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd); +} + +/* IRQ and event handlers */ +static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev) +{ + int i; + struct arm_smmu_device *smmu = dev; + struct arm_smmu_queue *q = &smmu->evtq.q; + u64 evt[EVTQ_ENT_DWORDS]; + + while (!queue_remove_raw(q, evt)) { + u8 id = evt[0] >> EVTQ_0_ID_SHIFT & EVTQ_0_ID_MASK; + + dev_info(smmu->dev, "event 0x%02x received:\n", id); + for (i = 0; i < ARRAY_SIZE(evt); ++i) + dev_info(smmu->dev, "\t0x%016llx\n", + (unsigned long long)evt[i]); + } + + /* Sync our overflow flag, as we believe we're up to speed */ + q->cons = Q_OVF(q, q->prod) | Q_WRP(q, q->cons) | Q_IDX(q, q->cons); + return IRQ_HANDLED; +} + +static irqreturn_t arm_smmu_evtq_handler(int irq, void *dev) +{ + irqreturn_t ret = IRQ_WAKE_THREAD; + struct arm_smmu_device *smmu = dev; + struct arm_smmu_queue *q = &smmu->evtq.q; + + /* + * Not much we can do on overflow, so scream and pretend we're + * trying harder. + */ + if (queue_sync_prod(q) == -EOVERFLOW) + dev_err(smmu->dev, "EVTQ overflow detected -- events lost\n"); + else if (queue_empty(q)) + ret = IRQ_NONE; + + return ret; +} + +static irqreturn_t arm_smmu_priq_thread(int irq, void *dev) +{ + struct arm_smmu_device *smmu = dev; + struct arm_smmu_queue *q = &smmu->priq.q; + u64 evt[PRIQ_ENT_DWORDS]; + + while (!queue_remove_raw(q, evt)) { + u32 sid, ssid; + u16 grpid; + bool ssv, last; + + sid = evt[0] >> PRIQ_0_SID_SHIFT & PRIQ_0_SID_MASK; + ssv = evt[0] & PRIQ_0_SSID_V; + ssid = ssv ? evt[0] >> PRIQ_0_SSID_SHIFT & PRIQ_0_SSID_MASK : 0; + last = evt[0] & PRIQ_0_PRG_LAST; + grpid = evt[1] >> PRIQ_1_PRG_IDX_SHIFT & PRIQ_1_PRG_IDX_MASK; + + dev_info(smmu->dev, "unexpected PRI request received:\n"); + dev_info(smmu->dev, + "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016llx\n", + sid, ssid, grpid, last ? "L" : "", + evt[0] & PRIQ_0_PERM_PRIV ? "" : "un", + evt[0] & PRIQ_0_PERM_READ ? "R" : "", + evt[0] & PRIQ_0_PERM_WRITE ? "W" : "", + evt[0] & PRIQ_0_PERM_EXEC ? "X" : "", + evt[1] & PRIQ_1_ADDR_MASK << PRIQ_1_ADDR_SHIFT); + + if (last) { + struct arm_smmu_cmdq_ent cmd = { + .opcode = CMDQ_OP_PRI_RESP, + .substream_valid = ssv, + .pri = { + .sid = sid, + .ssid = ssid, + .grpid = grpid, + .resp = PRI_RESP_DENY, + }, + }; + + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + } + } + + /* Sync our overflow flag, as we believe we're up to speed */ + q->cons = Q_OVF(q, q->prod) | Q_WRP(q, q->cons) | Q_IDX(q, q->cons); + return IRQ_HANDLED; +} + +static irqreturn_t arm_smmu_priq_handler(int irq, void *dev) +{ + irqreturn_t ret = IRQ_WAKE_THREAD; + struct arm_smmu_device *smmu = dev; + struct arm_smmu_queue *q = &smmu->priq.q; + + /* PRIQ overflow indicates a programming error */ + if (queue_sync_prod(q) == -EOVERFLOW) + dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n"); + else if (queue_empty(q)) + ret = IRQ_NONE; + + return ret; +} + +static irqreturn_t arm_smmu_cmdq_sync_handler(int irq, void *dev) +{ + /* We don't actually use CMD_SYNC interrupts for anything */ + return IRQ_HANDLED; +} + +static int arm_smmu_device_disable(struct arm_smmu_device *smmu); + +static irqreturn_t arm_smmu_gerror_handler(int irq, void *dev) +{ + u32 gerror, gerrorn; + struct arm_smmu_device *smmu = dev; + + gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR); + gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); + + gerror ^= gerrorn; + if (!(gerror & GERROR_ERR_MASK)) + return IRQ_NONE; /* No errors pending */ + + dev_warn(smmu->dev, + "unexpected global error reported (0x%08x), this could be serious\n", + gerror); + + if (gerror & GERROR_SFM_ERR) { + dev_err(smmu->dev, "device has entered Service Failure Mode!\n"); + arm_smmu_device_disable(smmu); + } + + if (gerror & GERROR_MSI_GERROR_ABT_ERR) + dev_warn(smmu->dev, "GERROR MSI write aborted\n"); + + if (gerror & GERROR_MSI_PRIQ_ABT_ERR) { + dev_warn(smmu->dev, "PRIQ MSI write aborted\n"); + arm_smmu_priq_handler(irq, smmu->dev); + } + + if (gerror & GERROR_MSI_EVTQ_ABT_ERR) { + dev_warn(smmu->dev, "EVTQ MSI write aborted\n"); + arm_smmu_evtq_handler(irq, smmu->dev); + } + + if (gerror & GERROR_MSI_CMDQ_ABT_ERR) { + dev_warn(smmu->dev, "CMDQ MSI write aborted\n"); + arm_smmu_cmdq_sync_handler(irq, smmu->dev); + } + + if (gerror & GERROR_PRIQ_ABT_ERR) + dev_err(smmu->dev, "PRIQ write aborted -- events may have been lost\n"); + + if (gerror & GERROR_EVTQ_ABT_ERR) + dev_err(smmu->dev, "EVTQ write aborted -- events may have been lost\n"); + + if (gerror & GERROR_CMDQ_ERR) + arm_smmu_cmdq_skip_err(smmu); + + writel(gerror, smmu->base + ARM_SMMU_GERRORN); + return IRQ_HANDLED; +} + +/* IO_PGTABLE API */ +static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu) +{ + struct arm_smmu_cmdq_ent cmd; + + cmd.opcode = CMDQ_OP_CMD_SYNC; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); +} + +static void arm_smmu_tlb_sync(void *cookie) +{ + struct arm_smmu_domain *smmu_domain = cookie; + __arm_smmu_tlb_sync(smmu_domain->smmu); +} + +static void arm_smmu_tlb_inv_context(void *cookie) +{ + struct arm_smmu_domain *smmu_domain = cookie; + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_cmdq_ent cmd; + + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { + cmd.opcode = CMDQ_OP_TLBI_NH_ASID; + cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; + cmd.tlbi.vmid = 0; + } else { + cmd.opcode = CMDQ_OP_TLBI_S12_VMALL; + cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; + } + + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + __arm_smmu_tlb_sync(smmu); +} + +static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, + bool leaf, void *cookie) +{ + struct arm_smmu_domain *smmu_domain = cookie; + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_cmdq_ent cmd = { + .tlbi = { + .leaf = leaf, + .addr = iova, + }, + }; + + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { + cmd.opcode = CMDQ_OP_TLBI_NH_VA; + cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; + } else { + cmd.opcode = CMDQ_OP_TLBI_S2_IPA; + cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; + } + + arm_smmu_cmdq_issue_cmd(smmu, &cmd); +} + +static void arm_smmu_flush_pgtable(void *addr, size_t size, void *cookie) +{ + struct arm_smmu_domain *smmu_domain = cookie; + struct arm_smmu_device *smmu = smmu_domain->smmu; + unsigned long offset = (unsigned long)addr & ~PAGE_MASK; + + if (smmu->features & ARM_SMMU_FEAT_COHERENCY) { + dsb(ishst); + } else { + dma_addr_t dma_addr; + struct device *dev = smmu->dev; + + dma_addr = dma_map_page(dev, virt_to_page(addr), offset, size, + DMA_TO_DEVICE); + + if (dma_mapping_error(dev, dma_addr)) + dev_err(dev, "failed to flush pgtable at %p\n", addr); + else + dma_unmap_page(dev, dma_addr, size, DMA_TO_DEVICE); + } +} + +static struct iommu_gather_ops arm_smmu_gather_ops = { + .tlb_flush_all = arm_smmu_tlb_inv_context, + .tlb_add_flush = arm_smmu_tlb_inv_range_nosync, + .tlb_sync = arm_smmu_tlb_sync, + .flush_pgtable = arm_smmu_flush_pgtable, +}; + +/* IOMMU API */ +static bool arm_smmu_capable(enum iommu_cap cap) +{ + switch (cap) { + case IOMMU_CAP_CACHE_COHERENCY: + return true; + case IOMMU_CAP_INTR_REMAP: + return true; /* MSIs are just memory writes */ + case IOMMU_CAP_NOEXEC: + return true; + default: + return false; + } +} + +static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) +{ + struct arm_smmu_domain *smmu_domain; + + if (type != IOMMU_DOMAIN_UNMANAGED) + return NULL; + + /* + * Allocate the domain and initialise some of its data structures. + * We can't really do anything meaningful until we've added a + * master. + */ + smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); + if (!smmu_domain) + return NULL; + + mutex_init(&smmu_domain->init_mutex); + spin_lock_init(&smmu_domain->pgtbl_lock); + return &smmu_domain->domain; +} + +static int arm_smmu_bitmap_alloc(unsigned long *map, int span) +{ + int idx, size = 1 << span; + + do { + idx = find_first_zero_bit(map, size); + if (idx == size) + return -ENOSPC; + } while (test_and_set_bit(idx, map)); + + return idx; +} + +static void arm_smmu_bitmap_free(unsigned long *map, int idx) +{ + clear_bit(idx, map); +} + +static void arm_smmu_domain_free(struct iommu_domain *domain) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_device *smmu = smmu_domain->smmu; + + if (smmu_domain->pgtbl_ops) + free_io_pgtable_ops(smmu_domain->pgtbl_ops); + + /* Free the CD and ASID, if we allocated them */ + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { + struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; + + if (cfg->cdptr) { + dma_free_coherent(smmu_domain->smmu->dev, + CTXDESC_CD_DWORDS << 3, + cfg->cdptr, + cfg->cdptr_dma); + + arm_smmu_bitmap_free(smmu->asid_map, cfg->cd.asid); + } + } else { + struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; + if (cfg->vmid) + arm_smmu_bitmap_free(smmu->vmid_map, cfg->vmid); + } + + kfree(smmu_domain); +} + +static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, + struct io_pgtable_cfg *pgtbl_cfg) +{ + int ret; + u16 asid; + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; + + asid = arm_smmu_bitmap_alloc(smmu->asid_map, smmu->asid_bits); + if (IS_ERR_VALUE(asid)) + return asid; + + cfg->cdptr = dma_zalloc_coherent(smmu->dev, CTXDESC_CD_DWORDS << 3, + &cfg->cdptr_dma, GFP_KERNEL); + if (!cfg->cdptr) { + dev_warn(smmu->dev, "failed to allocate context descriptor\n"); + goto out_free_asid; + } + + cfg->cd.asid = asid; + cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; + cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr; + cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; + return 0; + +out_free_asid: + arm_smmu_bitmap_free(smmu->asid_map, asid); + return ret; +} + +static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, + struct io_pgtable_cfg *pgtbl_cfg) +{ + u16 vmid; + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; + + vmid = arm_smmu_bitmap_alloc(smmu->vmid_map, smmu->vmid_bits); + if (IS_ERR_VALUE(vmid)) + return vmid; + + cfg->vmid = vmid; + cfg->vttbr = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; + cfg->vtcr = pgtbl_cfg->arm_lpae_s2_cfg.vtcr; + return 0; +} + +static struct iommu_ops arm_smmu_ops; + +static int arm_smmu_domain_finalise(struct iommu_domain *domain) +{ + int ret; + unsigned long ias, oas; + enum io_pgtable_fmt fmt; + struct io_pgtable_cfg pgtbl_cfg; + struct io_pgtable_ops *pgtbl_ops; + int (*finalise_stage_fn)(struct arm_smmu_domain *, + struct io_pgtable_cfg *); + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_device *smmu = smmu_domain->smmu; + + /* Restrict the stage to what we can actually support */ + if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) + smmu_domain->stage = ARM_SMMU_DOMAIN_S2; + if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) + smmu_domain->stage = ARM_SMMU_DOMAIN_S1; + + switch (smmu_domain->stage) { + case ARM_SMMU_DOMAIN_S1: + ias = VA_BITS; + oas = smmu->ias; + fmt = ARM_64_LPAE_S1; + finalise_stage_fn = arm_smmu_domain_finalise_s1; + break; + case ARM_SMMU_DOMAIN_NESTED: + case ARM_SMMU_DOMAIN_S2: + ias = smmu->ias; + oas = smmu->oas; + fmt = ARM_64_LPAE_S2; + finalise_stage_fn = arm_smmu_domain_finalise_s2; + break; + default: + return -EINVAL; + } + + pgtbl_cfg = (struct io_pgtable_cfg) { + .pgsize_bitmap = arm_smmu_ops.pgsize_bitmap, + .ias = ias, + .oas = oas, + .tlb = &arm_smmu_gather_ops, + }; + + pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain); + if (!pgtbl_ops) + return -ENOMEM; + + arm_smmu_ops.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; + smmu_domain->pgtbl_ops = pgtbl_ops; + + ret = finalise_stage_fn(smmu_domain, &pgtbl_cfg); + if (IS_ERR_VALUE(ret)) + free_io_pgtable_ops(pgtbl_ops); + + return ret; +} + +static struct arm_smmu_group *arm_smmu_group_get(struct device *dev) +{ + struct iommu_group *group; + struct arm_smmu_group *smmu_group; + + group = iommu_group_get(dev); + if (!group) + return NULL; + + smmu_group = iommu_group_get_iommudata(group); + iommu_group_put(group); + return smmu_group; +} + +static __le64 *arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid) +{ + __le64 *step; + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; + + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { + struct arm_smmu_strtab_l1_desc *l1_desc; + int idx; + + /* Two-level walk */ + idx = (sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS; + l1_desc = &cfg->l1_desc[idx]; + idx = (sid & ((1 << STRTAB_SPLIT) - 1)) * STRTAB_STE_DWORDS; + step = &l1_desc->l2ptr[idx]; + } else { + /* Simple linear lookup */ + step = &cfg->strtab[sid * STRTAB_STE_DWORDS]; + } + + return step; +} + +static int arm_smmu_install_ste_for_group(struct arm_smmu_group *smmu_group) +{ + int i; + struct arm_smmu_domain *smmu_domain = smmu_group->domain; + struct arm_smmu_strtab_ent *ste = &smmu_group->ste; + struct arm_smmu_device *smmu = smmu_group->smmu; + + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { + ste->s1_cfg = &smmu_domain->s1_cfg; + ste->s2_cfg = NULL; + arm_smmu_write_ctx_desc(smmu, ste->s1_cfg); + } else { + ste->s1_cfg = NULL; + ste->s2_cfg = &smmu_domain->s2_cfg; + } + + for (i = 0; i < smmu_group->num_sids; ++i) { + u32 sid = smmu_group->sids[i]; + __le64 *step = arm_smmu_get_step_for_sid(smmu, sid); + + arm_smmu_write_strtab_ent(smmu, sid, step, ste); + } + + return 0; +} + +static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) +{ + int ret = 0; + struct arm_smmu_device *smmu; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_group *smmu_group = arm_smmu_group_get(dev); + + if (!smmu_group) + return -ENOENT; + + /* Already attached to a different domain? */ + if (smmu_group->domain && smmu_group->domain != smmu_domain) + return -EEXIST; + + smmu = smmu_group->smmu; + mutex_lock(&smmu_domain->init_mutex); + + if (!smmu_domain->smmu) { + smmu_domain->smmu = smmu; + ret = arm_smmu_domain_finalise(domain); + if (ret) { + smmu_domain->smmu = NULL; + goto out_unlock; + } + } else if (smmu_domain->smmu != smmu) { + dev_err(dev, + "cannot attach to SMMU %s (upstream of %s)\n", + dev_name(smmu_domain->smmu->dev), + dev_name(smmu->dev)); + ret = -ENXIO; + goto out_unlock; + } + + /* Group already attached to this domain? */ + if (smmu_group->domain) + goto out_unlock; + + smmu_group->domain = smmu_domain; + smmu_group->ste.bypass = false; + + ret = arm_smmu_install_ste_for_group(smmu_group); + if (IS_ERR_VALUE(ret)) + smmu_group->domain = NULL; + +out_unlock: + mutex_unlock(&smmu_domain->init_mutex); + return ret; +} + +static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_group *smmu_group = arm_smmu_group_get(dev); + + BUG_ON(!smmu_domain); + BUG_ON(!smmu_group); + + mutex_lock(&smmu_domain->init_mutex); + BUG_ON(smmu_group->domain != smmu_domain); + + smmu_group->ste.bypass = true; + if (IS_ERR_VALUE(arm_smmu_install_ste_for_group(smmu_group))) + dev_warn(dev, "failed to install bypass STE\n"); + + smmu_group->domain = NULL; + mutex_unlock(&smmu_domain->init_mutex); +} + +static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, + phys_addr_t paddr, size_t size, int prot) +{ + int ret; + unsigned long flags; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; + + if (!ops) + return -ENODEV; + + spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); + ret = ops->map(ops, iova, paddr, size, prot); + spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); + return ret; +} + +static size_t +arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size) +{ + size_t ret; + unsigned long flags; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; + + if (!ops) + return 0; + + spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); + ret = ops->unmap(ops, iova, size); + spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); + return ret; +} + +static phys_addr_t +arm_smmu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) +{ + phys_addr_t ret; + unsigned long flags; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; + + if (!ops) + return 0; + + spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); + ret = ops->iova_to_phys(ops, iova); + spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); + + return ret; +} + +static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *sidp) +{ + *(u32 *)sidp = alias; + return 0; /* Continue walking */ +} + +static void __arm_smmu_release_pci_iommudata(void *data) +{ + kfree(data); +} + +static struct arm_smmu_device *arm_smmu_get_for_pci_dev(struct pci_dev *pdev) +{ + struct device_node *of_node; + struct arm_smmu_device *curr, *smmu = NULL; + struct pci_bus *bus = pdev->bus; + + /* Walk up to the root bus */ + while (!pci_is_root_bus(bus)) + bus = bus->parent; + + /* Follow the "iommus" phandle from the host controller */ + of_node = of_parse_phandle(bus->bridge->parent->of_node, "iommus", 0); + if (!of_node) + return NULL; + + /* See if we can find an SMMU corresponding to the phandle */ + spin_lock(&arm_smmu_devices_lock); + list_for_each_entry(curr, &arm_smmu_devices, list) { + if (curr->dev->of_node == of_node) { + smmu = curr; + break; + } + } + spin_unlock(&arm_smmu_devices_lock); + of_node_put(of_node); + return smmu; +} + +static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) +{ + unsigned long limit; + + if (sid < (1UL << smmu->sid_bits)) + return true; + + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { + limit = 1UL << (STRTAB_L1_SZ_SHIFT - + (ilog2(STRTAB_L1_DESC_DWORDS) + 3) + + STRTAB_SPLIT); + } else { + limit = 1UL << (STRTAB_L1_SZ_SHIFT - + (ilog2(STRTAB_STE_DWORDS) + 3)); + } + + return sid < limit; +} + +static int arm_smmu_add_device(struct device *dev) +{ + int i, ret; + u32 sid, *sids; + struct pci_dev *pdev; + struct iommu_group *group; + struct arm_smmu_group *smmu_group; + + /* We only support PCI, for now */ + if (!dev_is_pci(dev)) + return -ENODEV; + + pdev = to_pci_dev(dev); + group = iommu_group_get_for_dev(dev); + if (IS_ERR(group)) + return PTR_ERR(group); + + smmu_group = iommu_group_get_iommudata(group); + if (!smmu_group) { + struct arm_smmu_device *smmu = arm_smmu_get_for_pci_dev(pdev); + if (!smmu) { + ret = -ENOENT; + goto out_put_group; + } + + smmu_group = kzalloc(sizeof(*smmu_group), GFP_KERNEL); + if (!smmu_group) { + ret = -ENOMEM; + goto out_put_group; + } + + smmu_group->ste.valid = true; + smmu_group->smmu = smmu; + iommu_group_set_iommudata(group, smmu_group, + __arm_smmu_release_pci_iommudata); + } + + /* Assume SID == RID until firmware tells us otherwise */ + pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid); + for (i = 0; i < smmu_group->num_sids; ++i) { + /* If we already know about this SID, then we're done */ + if (smmu_group->sids[i] == sid) + return 0; + } + + /* Check the SID is in range of the SMMU and our stream table */ + if (!arm_smmu_sid_in_range(smmu_group->smmu, sid)) { + ret = -ERANGE; + goto out_put_group; + } + + /* Resize the SID array for the group */ + smmu_group->num_sids++; + sids = krealloc(smmu_group->sids, smmu_group->num_sids * sizeof(*sids), + GFP_KERNEL); + if (!sids) { + smmu_group->num_sids--; + ret = -ENOMEM; + goto out_put_group; + } + + /* Add the new SID */ + sids[smmu_group->num_sids - 1] = sid; + smmu_group->sids = sids; + return 0; + +out_put_group: + iommu_group_put(group); + return ret; +} + +static void arm_smmu_remove_device(struct device *dev) +{ + iommu_group_remove_device(dev); +} + +static int arm_smmu_domain_get_attr(struct iommu_domain *domain, + enum iommu_attr attr, void *data) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + + switch (attr) { + case DOMAIN_ATTR_NESTING: + *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED); + return 0; + default: + return -ENODEV; + } +} + +static int arm_smmu_domain_set_attr(struct iommu_domain *domain, + enum iommu_attr attr, void *data) +{ + int ret = 0; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + + mutex_lock(&smmu_domain->init_mutex); + + switch (attr) { + case DOMAIN_ATTR_NESTING: + if (smmu_domain->smmu) { + ret = -EPERM; + goto out_unlock; + } + + if (*(int *)data) + smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED; + else + smmu_domain->stage = ARM_SMMU_DOMAIN_S1; + + break; + default: + ret = -ENODEV; + } + +out_unlock: + mutex_unlock(&smmu_domain->init_mutex); + return ret; +} + +static struct iommu_ops arm_smmu_ops = { + .capable = arm_smmu_capable, + .domain_alloc = arm_smmu_domain_alloc, + .domain_free = arm_smmu_domain_free, + .attach_dev = arm_smmu_attach_dev, + .detach_dev = arm_smmu_detach_dev, + .map = arm_smmu_map, + .unmap = arm_smmu_unmap, + .iova_to_phys = arm_smmu_iova_to_phys, + .add_device = arm_smmu_add_device, + .remove_device = arm_smmu_remove_device, + .domain_get_attr = arm_smmu_domain_get_attr, + .domain_set_attr = arm_smmu_domain_set_attr, + .pgsize_bitmap = -1UL, /* Restricted during device attach */ +}; + +/* Probing and initialisation functions */ +static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, + struct arm_smmu_queue *q, + unsigned long prod_off, + unsigned long cons_off, + size_t dwords) +{ + size_t qsz = ((1 << q->max_n_shift) * dwords) << 3; + + q->base = dma_alloc_coherent(smmu->dev, qsz, &q->base_dma, GFP_KERNEL); + if (!q->base) { + dev_err(smmu->dev, "failed to allocate queue (0x%zx bytes)\n", + qsz); + return -ENOMEM; + } + + q->prod_reg = smmu->base + prod_off; + q->cons_reg = smmu->base + cons_off; + q->ent_dwords = dwords; + + q->q_base = Q_BASE_RWA; + q->q_base |= q->base_dma & Q_BASE_ADDR_MASK << Q_BASE_ADDR_SHIFT; + q->q_base |= (q->max_n_shift & Q_BASE_LOG2SIZE_MASK) + << Q_BASE_LOG2SIZE_SHIFT; + + q->prod = q->cons = 0; + return 0; +} + +static void arm_smmu_free_one_queue(struct arm_smmu_device *smmu, + struct arm_smmu_queue *q) +{ + size_t qsz = ((1 << q->max_n_shift) * q->ent_dwords) << 3; + + dma_free_coherent(smmu->dev, qsz, q->base, q->base_dma); +} + +static void arm_smmu_free_queues(struct arm_smmu_device *smmu) +{ + arm_smmu_free_one_queue(smmu, &smmu->cmdq.q); + arm_smmu_free_one_queue(smmu, &smmu->evtq.q); + + if (smmu->features & ARM_SMMU_FEAT_PRI) + arm_smmu_free_one_queue(smmu, &smmu->priq.q); +} + +static int arm_smmu_init_queues(struct arm_smmu_device *smmu) +{ + int ret; + + /* cmdq */ + spin_lock_init(&smmu->cmdq.lock); + ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, ARM_SMMU_CMDQ_PROD, + ARM_SMMU_CMDQ_CONS, CMDQ_ENT_DWORDS); + if (ret) + goto out; + + /* evtq */ + ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, ARM_SMMU_EVTQ_PROD, + ARM_SMMU_EVTQ_CONS, EVTQ_ENT_DWORDS); + if (ret) + goto out_free_cmdq; + + /* priq */ + if (!(smmu->features & ARM_SMMU_FEAT_PRI)) + return 0; + + ret = arm_smmu_init_one_queue(smmu, &smmu->priq.q, ARM_SMMU_PRIQ_PROD, + ARM_SMMU_PRIQ_CONS, PRIQ_ENT_DWORDS); + if (ret) + goto out_free_evtq; + + return 0; + +out_free_evtq: + arm_smmu_free_one_queue(smmu, &smmu->evtq.q); +out_free_cmdq: + arm_smmu_free_one_queue(smmu, &smmu->cmdq.q); +out: + return ret; +} + +static void arm_smmu_free_l2_strtab(struct arm_smmu_device *smmu) +{ + int i; + size_t size; + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; + + size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3); + for (i = 0; i < cfg->num_l1_descs; ++i) { + struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[i]; + + if (!desc->l2ptr) + continue; + + dma_free_coherent(smmu->dev, size, desc->l2ptr, + desc->l2ptr_dma); + } +} + +static void arm_smmu_init_bypass_stes(u64 *strtab, unsigned int nent) +{ + unsigned int i; + struct arm_smmu_strtab_ent ste = { + .valid = true, + .bypass = true, + }; + + for (i = 0; i < nent; ++i) { + arm_smmu_write_strtab_ent(NULL, -1, strtab, &ste); + strtab += STRTAB_STE_DWORDS; + } +} + +static int arm_smmu_alloc_l2_strtab(struct arm_smmu_device *smmu) +{ + int ret; + unsigned int i; + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; + size_t size = sizeof(*cfg->l1_desc) * cfg->num_l1_descs; + void *strtab = smmu->strtab_cfg.strtab; + + cfg->l1_desc = devm_kzalloc(smmu->dev, size, GFP_KERNEL); + if (!cfg->l1_desc) { + dev_err(smmu->dev, "failed to allocate l1 stream table desc\n"); + return -ENOMEM; + } + + size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3); + for (i = 0; i < cfg->num_l1_descs; ++i) { + struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[i]; + + desc->span = STRTAB_SPLIT + 1; + desc->l2ptr = dma_zalloc_coherent(smmu->dev, size, + &desc->l2ptr_dma, GFP_KERNEL); + if (!desc->l2ptr) { + dev_err(smmu->dev, + "failed to allocate l2 stream table %u\n", i); + ret = -ENOMEM; + goto out_free_l2; + } + + arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); + arm_smmu_write_strtab_l1_desc(strtab, desc); + strtab += STRTAB_STE_DWORDS; + } + + return 0; + +out_free_l2: + arm_smmu_free_l2_strtab(smmu); + return ret; +} + +static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) +{ + void *strtab; + u64 reg; + u32 size; + int ret = 0; + + strtab = dma_zalloc_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, + &smmu->strtab_cfg.strtab_dma, GFP_KERNEL); + if (!strtab) { + dev_err(smmu->dev, "failed to allocate l1 stream table\n"); + return -ENOMEM; + } + smmu->strtab_cfg.strtab = strtab; + + reg = smmu->strtab_cfg.strtab_dma & + STRTAB_BASE_ADDR_MASK << STRTAB_BASE_ADDR_SHIFT; + reg |= STRTAB_BASE_RA; + smmu->strtab_cfg.strtab_base = reg; + + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3); + smmu->strtab_cfg.num_l1_descs = 1 << size; + size += STRTAB_SPLIT; + reg = STRTAB_BASE_CFG_FMT_2LVL; + + ret = arm_smmu_alloc_l2_strtab(smmu); + if (ret) + goto out_free_l1; + } else { + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_STE_DWORDS) + 3); + smmu->strtab_cfg.num_l1_descs = 0; + reg = STRTAB_BASE_CFG_FMT_LINEAR; + arm_smmu_init_bypass_stes(strtab, 1 << size); + } + + if (size < smmu->sid_bits) + dev_warn(smmu->dev, "%s strtab only covers %u/%u bits of SID\n", + smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB ? + "2-level" : "linear", + size, smmu->sid_bits); + + reg |= (size & STRTAB_BASE_CFG_LOG2SIZE_MASK) + << STRTAB_BASE_CFG_LOG2SIZE_SHIFT; + reg |= (STRTAB_SPLIT & STRTAB_BASE_CFG_SPLIT_MASK) + << STRTAB_BASE_CFG_SPLIT_SHIFT; + smmu->strtab_cfg.strtab_base_cfg = reg; + + /* Allocate the first VMID for stage-2 bypass STEs */ + set_bit(0, smmu->vmid_map); + return 0; + +out_free_l1: + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, strtab, + smmu->strtab_cfg.strtab_dma); + return ret; +} + +static void arm_smmu_free_strtab(struct arm_smmu_device *smmu) +{ + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; + + arm_smmu_free_l2_strtab(smmu); + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, cfg->strtab, + cfg->strtab_dma); +} + +static int arm_smmu_init_structures(struct arm_smmu_device *smmu) +{ + int ret; + + ret = arm_smmu_init_queues(smmu); + if (ret) + return ret; + + ret = arm_smmu_init_strtab(smmu); + if (ret) + goto out_free_queues; + + return 0; + +out_free_queues: + arm_smmu_free_queues(smmu); + return ret; +} + +static void arm_smmu_free_structures(struct arm_smmu_device *smmu) +{ + arm_smmu_free_strtab(smmu); + arm_smmu_free_queues(smmu); +} + +static int arm_smmu_write_reg_sync(struct arm_smmu_device *smmu, u32 val, + unsigned int reg_off, unsigned int ack_off) +{ + u32 reg; + + writel_relaxed(val, smmu->base + reg_off); + return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val, + 1, ARM_SMMU_POLL_TIMEOUT_US); +} + +static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) +{ + int ret, irq; + + /* Disable IRQs first */ + ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL, + ARM_SMMU_IRQ_CTRLACK); + if (ret) { + dev_err(smmu->dev, "failed to disable irqs\n"); + return ret; + } + + /* Clear the MSI address regs */ + writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0); + writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); + + /* Request wired interrupt lines */ + irq = smmu->evtq.q.irq; + if (irq) { + ret = devm_request_threaded_irq(smmu->dev, irq, + arm_smmu_evtq_handler, + arm_smmu_evtq_thread, + 0, "arm-smmu-v3-evtq", smmu); + if (IS_ERR_VALUE(ret)) + dev_warn(smmu->dev, "failed to enable evtq irq\n"); + } + + irq = smmu->cmdq.q.irq; + if (irq) { + ret = devm_request_irq(smmu->dev, irq, + arm_smmu_cmdq_sync_handler, 0, + "arm-smmu-v3-cmdq-sync", smmu); + if (IS_ERR_VALUE(ret)) + dev_warn(smmu->dev, "failed to enable cmdq-sync irq\n"); + } + + irq = smmu->gerr_irq; + if (irq) { + ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler, + 0, "arm-smmu-v3-gerror", smmu); + if (IS_ERR_VALUE(ret)) + dev_warn(smmu->dev, "failed to enable gerror irq\n"); + } + + if (smmu->features & ARM_SMMU_FEAT_PRI) { + writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0); + + irq = smmu->priq.q.irq; + if (irq) { + ret = devm_request_threaded_irq(smmu->dev, irq, + arm_smmu_priq_handler, + arm_smmu_priq_thread, + 0, "arm-smmu-v3-priq", + smmu); + if (IS_ERR_VALUE(ret)) + dev_warn(smmu->dev, + "failed to enable priq irq\n"); + } + } + + /* Enable interrupt generation on the SMMU */ + ret = arm_smmu_write_reg_sync(smmu, + IRQ_CTRL_EVTQ_IRQEN | + IRQ_CTRL_GERROR_IRQEN, + ARM_SMMU_IRQ_CTRL, ARM_SMMU_IRQ_CTRLACK); + if (ret) + dev_warn(smmu->dev, "failed to enable irqs\n"); + + return 0; +} + +static int arm_smmu_device_disable(struct arm_smmu_device *smmu) +{ + int ret; + + ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_CR0, ARM_SMMU_CR0ACK); + if (ret) + dev_err(smmu->dev, "failed to clear cr0\n"); + + return ret; +} + +static int arm_smmu_device_reset(struct arm_smmu_device *smmu) +{ + int ret; + u32 reg, enables; + struct arm_smmu_cmdq_ent cmd; + + /* Clear CR0 and sync (disables SMMU and queue processing) */ + reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); + if (reg & CR0_SMMUEN) + dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); + + ret = arm_smmu_device_disable(smmu); + if (ret) + return ret; + + /* CR1 (table and queue memory attributes) */ + reg = (CR1_SH_ISH << CR1_TABLE_SH_SHIFT) | + (CR1_CACHE_WB << CR1_TABLE_OC_SHIFT) | + (CR1_CACHE_WB << CR1_TABLE_IC_SHIFT) | + (CR1_SH_ISH << CR1_QUEUE_SH_SHIFT) | + (CR1_CACHE_WB << CR1_QUEUE_OC_SHIFT) | + (CR1_CACHE_WB << CR1_QUEUE_IC_SHIFT); + writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); + + /* CR2 (random crap) */ + reg = CR2_PTM | CR2_RECINVMID | CR2_E2H; + writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); + + /* Stream table */ + writeq_relaxed(smmu->strtab_cfg.strtab_base, + smmu->base + ARM_SMMU_STRTAB_BASE); + writel_relaxed(smmu->strtab_cfg.strtab_base_cfg, + smmu->base + ARM_SMMU_STRTAB_BASE_CFG); + + /* Command queue */ + writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); + writel_relaxed(smmu->cmdq.q.prod, smmu->base + ARM_SMMU_CMDQ_PROD); + writel_relaxed(smmu->cmdq.q.cons, smmu->base + ARM_SMMU_CMDQ_CONS); + + enables = CR0_CMDQEN; + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to enable command queue\n"); + return ret; + } + + /* Invalidate any cached configuration */ + cmd.opcode = CMDQ_OP_CFGI_ALL; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + cmd.opcode = CMDQ_OP_CMD_SYNC; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + + /* Invalidate any stale TLB entries */ + cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + cmd.opcode = CMDQ_OP_TLBI_NSNH_ALL; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + cmd.opcode = CMDQ_OP_CMD_SYNC; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + + /* Event queue */ + writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); + writel_relaxed(smmu->evtq.q.prod, smmu->base + ARM_SMMU_EVTQ_PROD); + writel_relaxed(smmu->evtq.q.cons, smmu->base + ARM_SMMU_EVTQ_CONS); + + enables |= CR0_EVTQEN; + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to enable event queue\n"); + return ret; + } + + /* PRI queue */ + if (smmu->features & ARM_SMMU_FEAT_PRI) { + writeq_relaxed(smmu->priq.q.q_base, + smmu->base + ARM_SMMU_PRIQ_BASE); + writel_relaxed(smmu->priq.q.prod, + smmu->base + ARM_SMMU_PRIQ_PROD); + writel_relaxed(smmu->priq.q.cons, + smmu->base + ARM_SMMU_PRIQ_CONS); + + enables |= CR0_PRIQEN; + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to enable PRI queue\n"); + return ret; + } + } + + ret = arm_smmu_setup_irqs(smmu); + if (ret) { + dev_err(smmu->dev, "failed to setup irqs\n"); + return ret; + } + + /* Enable the SMMU interface */ + enables |= CR0_SMMUEN; + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to enable SMMU interface\n"); + return ret; + } + + return 0; +} + +static int arm_smmu_device_probe(struct arm_smmu_device *smmu) +{ + u32 reg; + bool coherent; + unsigned long pgsize_bitmap = 0; + + /* IDR0 */ + reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0); + + /* 2-level structures */ + if ((reg & IDR0_ST_LVL_MASK << IDR0_ST_LVL_SHIFT) == IDR0_ST_LVL_2LVL); + smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB; + + if (reg & IDR0_CD2L) + smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB; + + /* + * Translation table endianness. + * We currently require the same endianness as the CPU, but this + * could be changed later by adding a new IO_PGTABLE_QUIRK. + */ + switch (reg & IDR0_TTENDIAN_MASK << IDR0_TTENDIAN_SHIFT) { + case IDR0_TTENDIAN_MIXED: + smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE; + break; +#ifdef __BIG_ENDIAN + case IDR0_TTENDIAN_BE: + smmu->features |= ARM_SMMU_FEAT_TT_BE; + break; +#else + case IDR0_TTENDIAN_LE: + smmu->features |= ARM_SMMU_FEAT_TT_LE; + break; +#endif + default: + dev_err(smmu->dev, "unknown/unsupported TT endianness!\n"); + return -ENXIO; + } + + /* Boolean feature flags */ + if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI) + smmu->features |= ARM_SMMU_FEAT_PRI; + + if (IS_ENABLED(CONFIG_PCI_ATS) && reg & IDR0_ATS) + smmu->features |= ARM_SMMU_FEAT_ATS; + + if (reg & IDR0_SEV) + smmu->features |= ARM_SMMU_FEAT_SEV; + + if (reg & IDR0_MSI) + smmu->features |= ARM_SMMU_FEAT_MSI; + + /* + * The dma-coherent property is used in preference to the ID + * register, but warn on mismatch. + */ + coherent = of_dma_is_coherent(smmu->dev->of_node); + if (coherent) + smmu->features |= ARM_SMMU_FEAT_COHERENCY; + + if (!!(reg & IDR0_COHACC) != coherent) + dev_warn(smmu->dev, "IDR0.COHACC overridden by dma-coherent property (%s)\n", + coherent ? "true" : "false"); + + if (reg & IDR0_STALL_MODEL) + smmu->features |= ARM_SMMU_FEAT_STALLS; + + if (reg & IDR0_S1P) + smmu->features |= ARM_SMMU_FEAT_TRANS_S1; + + if (reg & IDR0_S2P) + smmu->features |= ARM_SMMU_FEAT_TRANS_S2; + + if (!(reg & (IDR0_S1P | IDR0_S2P))) { + dev_err(smmu->dev, "no translation support!\n"); + return -ENXIO; + } + + /* We only support the AArch64 table format at present */ + if ((reg & IDR0_TTF_MASK << IDR0_TTF_SHIFT) < IDR0_TTF_AARCH64) { + dev_err(smmu->dev, "AArch64 table format not supported!\n"); + return -ENXIO; + } + + /* ASID/VMID sizes */ + smmu->asid_bits = reg & IDR0_ASID16 ? 16 : 8; + smmu->vmid_bits = reg & IDR0_VMID16 ? 16 : 8; + + /* IDR1 */ + reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1); + if (reg & (IDR1_TABLES_PRESET | IDR1_QUEUES_PRESET | IDR1_REL)) { + dev_err(smmu->dev, "embedded implementation not supported\n"); + return -ENXIO; + } + + /* Queue sizes, capped at 4k */ + smmu->cmdq.q.max_n_shift = min((u32)CMDQ_MAX_SZ_SHIFT, + reg >> IDR1_CMDQ_SHIFT & IDR1_CMDQ_MASK); + if (!smmu->cmdq.q.max_n_shift) { + /* Odd alignment restrictions on the base, so ignore for now */ + dev_err(smmu->dev, "unit-length command queue not supported\n"); + return -ENXIO; + } + + smmu->evtq.q.max_n_shift = min((u32)EVTQ_MAX_SZ_SHIFT, + reg >> IDR1_EVTQ_SHIFT & IDR1_EVTQ_MASK); + smmu->priq.q.max_n_shift = min((u32)PRIQ_MAX_SZ_SHIFT, + reg >> IDR1_PRIQ_SHIFT & IDR1_PRIQ_MASK); + + /* SID/SSID sizes */ + smmu->ssid_bits = reg >> IDR1_SSID_SHIFT & IDR1_SSID_MASK; + smmu->sid_bits = reg >> IDR1_SID_SHIFT & IDR1_SID_MASK; + + /* IDR5 */ + reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); + + /* Maximum number of outstanding stalls */ + smmu->evtq.max_stalls = reg >> IDR5_STALL_MAX_SHIFT + & IDR5_STALL_MAX_MASK; + + /* Page sizes */ + if (reg & IDR5_GRAN64K) + pgsize_bitmap |= SZ_64K | SZ_512M; + if (reg & IDR5_GRAN16K) + pgsize_bitmap |= SZ_16K | SZ_32M; + if (reg & IDR5_GRAN4K) + pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; + + arm_smmu_ops.pgsize_bitmap &= pgsize_bitmap; + + /* Output address size */ + switch (reg & IDR5_OAS_MASK << IDR5_OAS_SHIFT) { + case IDR5_OAS_32_BIT: + smmu->oas = 32; + break; + case IDR5_OAS_36_BIT: + smmu->oas = 36; + break; + case IDR5_OAS_40_BIT: + smmu->oas = 40; + break; + case IDR5_OAS_42_BIT: + smmu->oas = 42; + break; + case IDR5_OAS_44_BIT: + smmu->oas = 44; + break; + case IDR5_OAS_48_BIT: + smmu->oas = 48; + break; + default: + dev_err(smmu->dev, "unknown output address size!\n"); + return -ENXIO; + } + + /* Set the DMA mask for our table walker */ + if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(smmu->oas))) + dev_warn(smmu->dev, + "failed to set DMA mask for table walker\n"); + + if (!smmu->ias) + smmu->ias = smmu->oas; + + dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n", + smmu->ias, smmu->oas, smmu->features); + return 0; +} + +static int arm_smmu_device_dt_probe(struct platform_device *pdev) +{ + int irq, ret; + struct resource *res; + struct arm_smmu_device *smmu; + struct device *dev = &pdev->dev; + + smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); + if (!smmu) { + dev_err(dev, "failed to allocate arm_smmu_device\n"); + return -ENOMEM; + } + smmu->dev = dev; + + /* Base address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (resource_size(res) + 1 < SZ_128K) { + dev_err(dev, "MMIO region too small (%pr)\n", res); + return -EINVAL; + } + + smmu->base = devm_ioremap_resource(dev, res); + if (IS_ERR(smmu->base)) + return PTR_ERR(smmu->base); + + /* Interrupt lines */ + irq = platform_get_irq_byname(pdev, "eventq"); + if (irq > 0) + smmu->evtq.q.irq = irq; + + irq = platform_get_irq_byname(pdev, "priq"); + if (irq > 0) + smmu->priq.q.irq = irq; + + irq = platform_get_irq_byname(pdev, "cmdq-sync"); + if (irq > 0) + smmu->cmdq.q.irq = irq; + + irq = platform_get_irq_byname(pdev, "gerror"); + if (irq > 0) + smmu->gerr_irq = irq; + + /* Probe the h/w */ + ret = arm_smmu_device_probe(smmu); + if (ret) + return ret; + + /* Initialise in-memory data structures */ + ret = arm_smmu_init_structures(smmu); + if (ret) + return ret; + + /* Reset the device */ + ret = arm_smmu_device_reset(smmu); + if (ret) + goto out_free_structures; + + /* Record our private device structure */ + INIT_LIST_HEAD(&smmu->list); + spin_lock(&arm_smmu_devices_lock); + list_add(&smmu->list, &arm_smmu_devices); + spin_unlock(&arm_smmu_devices_lock); + return 0; + +out_free_structures: + arm_smmu_free_structures(smmu); + return ret; +} + +static int arm_smmu_device_remove(struct platform_device *pdev) +{ + struct arm_smmu_device *curr, *smmu = NULL; + struct device *dev = &pdev->dev; + + spin_lock(&arm_smmu_devices_lock); + list_for_each_entry(curr, &arm_smmu_devices, list) { + if (curr->dev == dev) { + smmu = curr; + list_del(&smmu->list); + break; + } + } + spin_unlock(&arm_smmu_devices_lock); + + if (!smmu) + return -ENODEV; + + arm_smmu_device_disable(smmu); + arm_smmu_free_structures(smmu); + return 0; +} + +static struct of_device_id arm_smmu_of_match[] = { + { .compatible = "arm,smmu-v3", }, + { }, +}; +MODULE_DEVICE_TABLE(of, arm_smmu_of_match); + +static struct platform_driver arm_smmu_driver = { + .driver = { + .name = "arm-smmu-v3", + .of_match_table = of_match_ptr(arm_smmu_of_match), + }, + .probe = arm_smmu_device_dt_probe, + .remove = arm_smmu_device_remove, +}; + +static int __init arm_smmu_init(void) +{ + struct device_node *np; + int ret; + + np = of_find_matching_node(NULL, arm_smmu_of_match); + if (!np) + return 0; + + of_node_put(np); + + ret = platform_driver_register(&arm_smmu_driver); + if (ret) + return ret; + + return bus_set_iommu(&pci_bus_type, &arm_smmu_ops); +} + +static void __exit arm_smmu_exit(void) +{ + return platform_driver_unregister(&arm_smmu_driver); +} + +subsys_initcall(arm_smmu_init); +module_exit(arm_smmu_exit); + +MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations"); +MODULE_AUTHOR("Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>"); +MODULE_LICENSE("GPL v2"); -- 2.1.4 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-05-08 18:00 ` Will Deacon 0 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-08 18:00 UTC (permalink / raw) To: linux-arm-kernel Version three of the ARM SMMU architecture introduces significant changes and improvements over previous versions of the specification, necessitating a new driver in the Linux kernel. The main change to the programming interface is that the majority of the configuration data has been moved from MMIO registers to in-memory data structures, with communication between the CPU and the SMMU being mediated via in-memory circular queues. This patch adds an initial driver for SMMUv3 to Linux. We currently support pinned stage-1 (DMA) and stage-2 (KVM VFIO) mappings using the generic IO-pgtable code. Cc: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> --- MAINTAINERS | 3 +- drivers/iommu/Kconfig | 13 + drivers/iommu/Makefile | 1 + drivers/iommu/arm-smmu-v3.c | 2599 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 2615 insertions(+), 1 deletion(-) create mode 100644 drivers/iommu/arm-smmu-v3.c diff --git a/MAINTAINERS b/MAINTAINERS index 2e5bbc0d68b2..ad1acacba393 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1619,11 +1619,12 @@ F: drivers/i2c/busses/i2c-cadence.c F: drivers/mmc/host/sdhci-of-arasan.c F: drivers/edac/synopsys_edac.c -ARM SMMU DRIVER +ARM SMMU DRIVERS M: Will Deacon <will.deacon@arm.com> L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/iommu/arm-smmu.c +F: drivers/iommu/arm-smmu-v3.c F: drivers/iommu/io-pgtable-arm.c ARM64 PORT (AARCH64 ARCHITECTURE) diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 1ae4e547b419..40f37a2b4a8a 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -339,6 +339,7 @@ config SPAPR_TCE_IOMMU Enables bits of IOMMU API required by VFIO. The iommu_ops is not implemented as it is not necessary for VFIO. +# ARM IOMMU support config ARM_SMMU bool "ARM Ltd. System MMU (SMMU) Support" depends on (ARM64 || ARM) && MMU @@ -352,4 +353,16 @@ config ARM_SMMU Say Y here if your SoC includes an IOMMU device implementing the ARM SMMU architecture. +config ARM_SMMU_V3 + bool "ARM Ltd. System MMU Version 3 (SMMUv3) Support" + depends on ARM64 && PCI + select IOMMU_API + select IOMMU_IO_PGTABLE_LPAE + help + Support for implementations of the ARM System MMU architecture + version 3 providing translation support to a PCIe root complex. + + Say Y here if your system includes an IOMMU device implementing + the ARM SMMUv3 architecture. + endif # IOMMU_SUPPORT diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 080ffab4ed1c..c6dcc513d711 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o msm_iommu_dev.o obj-$(CONFIG_AMD_IOMMU) += amd_iommu.o amd_iommu_init.o obj-$(CONFIG_AMD_IOMMU_V2) += amd_iommu_v2.o obj-$(CONFIG_ARM_SMMU) += arm-smmu.o +obj-$(CONFIG_ARM_SMMU_V3) += arm-smmu-v3.o obj-$(CONFIG_DMAR_TABLE) += dmar.o obj-$(CONFIG_INTEL_IOMMU) += intel-iommu.o obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c new file mode 100644 index 000000000000..c471000e5d3c --- /dev/null +++ b/drivers/iommu/arm-smmu-v3.c @@ -0,0 +1,2599 @@ +/* + * IOMMU API for ARM architected SMMUv3 implementations. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * Copyright (C) 2015 ARM Limited + * + * Author: Will Deacon <will.deacon@arm.com> + * + * This driver is powered by bad coffee and bombay mix. + */ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/iommu.h> +#include <linux/iopoll.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/pci.h> +#include <linux/platform_device.h> + +#include "io-pgtable.h" + +/* MMIO registers */ +#define ARM_SMMU_IDR0 0x0 +#define IDR0_ST_LVL_SHIFT 27 +#define IDR0_ST_LVL_MASK 0x3 +#define IDR0_ST_LVL_2LVL (1 << IDR0_ST_LVL_SHIFT) +#define IDR0_STALL_MODEL (3 << 24) +#define IDR0_TTENDIAN_SHIFT 21 +#define IDR0_TTENDIAN_MASK 0x3 +#define IDR0_TTENDIAN_LE (2 << IDR0_TTENDIAN_SHIFT) +#define IDR0_TTENDIAN_BE (3 << IDR0_TTENDIAN_SHIFT) +#define IDR0_TTENDIAN_MIXED (0 << IDR0_TTENDIAN_SHIFT) +#define IDR0_CD2L (1 << 19) +#define IDR0_VMID16 (1 << 18) +#define IDR0_PRI (1 << 16) +#define IDR0_SEV (1 << 14) +#define IDR0_MSI (1 << 13) +#define IDR0_ASID16 (1 << 12) +#define IDR0_ATS (1 << 10) +#define IDR0_COHACC (1 << 4) +#define IDR0_TTF_SHIFT 2 +#define IDR0_TTF_MASK 0x3 +#define IDR0_TTF_AARCH64 (2 << IDR0_TTF_SHIFT) +#define IDR0_S1P (1 << 1) +#define IDR0_S2P (1 << 0) + +#define ARM_SMMU_IDR1 0x4 +#define IDR1_TABLES_PRESET (1 << 30) +#define IDR1_QUEUES_PRESET (1 << 29) +#define IDR1_REL (1 << 28) +#define IDR1_CMDQ_SHIFT 21 +#define IDR1_CMDQ_MASK 0x1f +#define IDR1_EVTQ_SHIFT 16 +#define IDR1_EVTQ_MASK 0x1f +#define IDR1_PRIQ_SHIFT 11 +#define IDR1_PRIQ_MASK 0x1f +#define IDR1_SSID_SHIFT 6 +#define IDR1_SSID_MASK 0x1f +#define IDR1_SID_SHIFT 0 +#define IDR1_SID_MASK 0x3f + +#define ARM_SMMU_IDR5 0x14 +#define IDR5_STALL_MAX_SHIFT 16 +#define IDR5_STALL_MAX_MASK 0xffff +#define IDR5_GRAN64K (1 << 6) +#define IDR5_GRAN16K (1 << 5) +#define IDR5_GRAN4K (1 << 4) +#define IDR5_OAS_SHIFT 0 +#define IDR5_OAS_MASK 0x7 +#define IDR5_OAS_32_BIT (0 << IDR5_OAS_SHIFT) +#define IDR5_OAS_36_BIT (1 << IDR5_OAS_SHIFT) +#define IDR5_OAS_40_BIT (2 << IDR5_OAS_SHIFT) +#define IDR5_OAS_42_BIT (3 << IDR5_OAS_SHIFT) +#define IDR5_OAS_44_BIT (4 << IDR5_OAS_SHIFT) +#define IDR5_OAS_48_BIT (5 << IDR5_OAS_SHIFT) + +#define ARM_SMMU_CR0 0x20 +#define CR0_CMDQEN (1 << 3) +#define CR0_EVTQEN (1 << 2) +#define CR0_PRIQEN (1 << 1) +#define CR0_SMMUEN (1 << 0) + +#define ARM_SMMU_CR0ACK 0x24 + +#define ARM_SMMU_CR1 0x28 +#define CR1_SH_NSH 0 +#define CR1_SH_OSH 2 +#define CR1_SH_ISH 3 +#define CR1_CACHE_NC 0 +#define CR1_CACHE_WB 1 +#define CR1_CACHE_WT 2 +#define CR1_TABLE_SH_SHIFT 10 +#define CR1_TABLE_OC_SHIFT 8 +#define CR1_TABLE_IC_SHIFT 6 +#define CR1_QUEUE_SH_SHIFT 4 +#define CR1_QUEUE_OC_SHIFT 2 +#define CR1_QUEUE_IC_SHIFT 0 + +#define ARM_SMMU_CR2 0x2c +#define CR2_PTM (1 << 2) +#define CR2_RECINVMID (1 << 1) +#define CR2_E2H (1 << 0) + +#define ARM_SMMU_IRQ_CTRL 0x50 +#define IRQ_CTRL_EVTQ_IRQEN (1 << 2) +#define IRQ_CTRL_GERROR_IRQEN (1 << 0) + +#define ARM_SMMU_IRQ_CTRLACK 0x54 + +#define ARM_SMMU_GERROR 0x60 +#define GERROR_SFM_ERR (1 << 8) +#define GERROR_MSI_GERROR_ABT_ERR (1 << 7) +#define GERROR_MSI_PRIQ_ABT_ERR (1 << 6) +#define GERROR_MSI_EVTQ_ABT_ERR (1 << 5) +#define GERROR_MSI_CMDQ_ABT_ERR (1 << 4) +#define GERROR_PRIQ_ABT_ERR (1 << 3) +#define GERROR_EVTQ_ABT_ERR (1 << 2) +#define GERROR_CMDQ_ERR (1 << 0) +#define GERROR_ERR_MASK 0xfd + +#define ARM_SMMU_GERRORN 0x64 + +#define ARM_SMMU_GERROR_IRQ_CFG0 0x68 +#define ARM_SMMU_GERROR_IRQ_CFG1 0x70 +#define ARM_SMMU_GERROR_IRQ_CFG2 0x74 + +#define ARM_SMMU_STRTAB_BASE 0x80 +#define STRTAB_BASE_RA (1UL << 62) +#define STRTAB_BASE_ADDR_SHIFT 6 +#define STRTAB_BASE_ADDR_MASK 0x3ffffffffffUL + +#define ARM_SMMU_STRTAB_BASE_CFG 0x88 +#define STRTAB_BASE_CFG_LOG2SIZE_SHIFT 0 +#define STRTAB_BASE_CFG_LOG2SIZE_MASK 0x3f +#define STRTAB_BASE_CFG_SPLIT_SHIFT 6 +#define STRTAB_BASE_CFG_SPLIT_MASK 0x1f +#define STRTAB_BASE_CFG_FMT_SHIFT 16 +#define STRTAB_BASE_CFG_FMT_MASK 0x3 +#define STRTAB_BASE_CFG_FMT_LINEAR (0 << STRTAB_BASE_CFG_FMT_SHIFT) +#define STRTAB_BASE_CFG_FMT_2LVL (1 << STRTAB_BASE_CFG_FMT_SHIFT) + +#define ARM_SMMU_CMDQ_BASE 0x90 +#define ARM_SMMU_CMDQ_PROD 0x98 +#define ARM_SMMU_CMDQ_CONS 0x9c + +#define ARM_SMMU_EVTQ_BASE 0xa0 +#define ARM_SMMU_EVTQ_PROD 0x100a8 +#define ARM_SMMU_EVTQ_CONS 0x100ac +#define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0 +#define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8 +#define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc + +#define ARM_SMMU_PRIQ_BASE 0xc0 +#define ARM_SMMU_PRIQ_PROD 0x100c8 +#define ARM_SMMU_PRIQ_CONS 0x100cc +#define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0 +#define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 +#define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc + +/* Common MSI config fields */ +#define MSI_CFG0_SH_SHIFT 60 +#define MSI_CFG0_SH_NSH (0UL << MSI_CFG0_SH_SHIFT) +#define MSI_CFG0_SH_OSH (2UL << MSI_CFG0_SH_SHIFT) +#define MSI_CFG0_SH_ISH (3UL << MSI_CFG0_SH_SHIFT) +#define MSI_CFG0_MEMATTR_SHIFT 56 +#define MSI_CFG0_MEMATTR_DEVICE_nGnRE (0x1 << MSI_CFG0_MEMATTR_SHIFT) +#define MSI_CFG0_ADDR_SHIFT 2 +#define MSI_CFG0_ADDR_MASK 0x3fffffffffffUL + +#define Q_IDX(q, p) ((p) & ((1 << (q)->max_n_shift) - 1)) +#define Q_WRP(q, p) ((p) & (1 << (q)->max_n_shift)) +#define Q_OVERFLOW_FLAG (1 << 31) +#define Q_OVF(q, p) ((p) & Q_OVERFLOW_FLAG) +#define Q_ENT(q, p) ((q)->base + \ + Q_IDX(q, p) * (q)->ent_dwords) + +#define Q_BASE_RWA (1UL << 62) +#define Q_BASE_ADDR_SHIFT 5 +#define Q_BASE_ADDR_MASK 0xfffffffffffUL +#define Q_BASE_LOG2SIZE_SHIFT 0 +#define Q_BASE_LOG2SIZE_MASK 0x1fUL + +/* + * Stream table. + * + * Linear: 128 STEs + * 2lvl: 1024 L1 entries, 64 entries per table (covers a PCI host controller) + */ +#define STRTAB_L1_SZ_SHIFT 13 +#define STRTAB_SPLIT 6 + +#define STRTAB_L1_DESC_DWORDS 1 +#define STRTAB_L1_DESC_SPAN_SHIFT 0 +#define STRTAB_L1_DESC_SPAN_MASK 0x1fUL +#define STRTAB_L1_DESC_L2PTR_SHIFT 6 +#define STRTAB_L1_DESC_L2PTR_MASK 0x3ffffffffffUL + +#define STRTAB_STE_DWORDS 8 +#define STRTAB_STE_0_V (1UL << 0) +#define STRTAB_STE_0_CFG_SHIFT 1 +#define STRTAB_STE_0_CFG_MASK 0x7UL +#define STRTAB_STE_0_CFG_FAULT (0UL << STRTAB_STE_0_CFG_SHIFT) +#define STRTAB_STE_0_CFG_BYPASS (4UL << STRTAB_STE_0_CFG_SHIFT) +#define STRTAB_STE_0_CFG_S1_TRANS (5UL << STRTAB_STE_0_CFG_SHIFT) +#define STRTAB_STE_0_CFG_S2_TRANS (6UL << STRTAB_STE_0_CFG_SHIFT) + +#define STRTAB_STE_0_S1FMT_SHIFT 4 +#define STRTAB_STE_0_S1FMT_LINEAR (0UL << STRTAB_STE_0_S1FMT_SHIFT) +#define STRTAB_STE_0_S1CTXPTR_SHIFT 6 +#define STRTAB_STE_0_S1CTXPTR_MASK 0x3ffffffffffUL +#define STRTAB_STE_0_S1CDMAX_SHIFT 59 +#define STRTAB_STE_0_S1CDMAX_MASK 0x1fUL + +#define STRTAB_STE_1_S1C_CACHE_NC 0UL +#define STRTAB_STE_1_S1C_CACHE_WBRA 1UL +#define STRTAB_STE_1_S1C_CACHE_WT 2UL +#define STRTAB_STE_1_S1C_CACHE_WB 3UL +#define STRTAB_STE_1_S1C_SH_NSH 0UL +#define STRTAB_STE_1_S1C_SH_OSH 2UL +#define STRTAB_STE_1_S1C_SH_ISH 3UL +#define STRTAB_STE_1_S1CIR_SHIFT 2 +#define STRTAB_STE_1_S1COR_SHIFT 4 +#define STRTAB_STE_1_S1CSH_SHIFT 6 + +#define STRTAB_STE_1_S1STALLD (1UL << 27) + +#define STRTAB_STE_1_EATS_ABT 0UL +#define STRTAB_STE_1_EATS_TRANS 1UL +#define STRTAB_STE_1_EATS_S1CHK 2UL +#define STRTAB_STE_1_EATS_SHIFT 28 + +#define STRTAB_STE_1_STRW_NSEL1 0UL +#define STRTAB_STE_1_STRW_EL2 2UL +#define STRTAB_STE_1_STRW_SHIFT 30 + +#define STRTAB_STE_2_S2VMID_SHIFT 0 +#define STRTAB_STE_2_S2VMID_MASK 0xffffUL +#define STRTAB_STE_2_VTCR_SHIFT 32 +#define STRTAB_STE_2_VTCR_MASK 0x7ffffUL +#define STRTAB_STE_2_S2AA64 (1UL << 51) +#define STRTAB_STE_2_S2ENDI (1UL << 52) +#define STRTAB_STE_2_S2PTW (1UL << 54) +#define STRTAB_STE_2_S2R (1UL << 58) + +#define STRTAB_STE_3_S2TTB_SHIFT 4 +#define STRTAB_STE_3_S2TTB_MASK 0xfffffffffffUL + +/* Context descriptor (stage-1 only) */ +#define CTXDESC_CD_DWORDS 8 +#define CTXDESC_CD_0_TCR_T0SZ_SHIFT 0 +#define ARM64_TCR_T0SZ_SHIFT 0 +#define ARM64_TCR_T0SZ_MASK 0x1fUL +#define CTXDESC_CD_0_TCR_TG0_SHIFT 6 +#define ARM64_TCR_TG0_SHIFT 14 +#define ARM64_TCR_TG0_MASK 0x3UL +#define CTXDESC_CD_0_TCR_IRGN0_SHIFT 8 +#define ARM64_TCR_IRGN0_SHIFT 24 +#define ARM64_TCR_IRGN0_MASK 0x3UL +#define CTXDESC_CD_0_TCR_ORGN0_SHIFT 10 +#define ARM64_TCR_ORGN0_SHIFT 26 +#define ARM64_TCR_ORGN0_MASK 0x3UL +#define CTXDESC_CD_0_TCR_SH0_SHIFT 12 +#define ARM64_TCR_SH0_SHIFT 12 +#define ARM64_TCR_SH0_MASK 0x3UL +#define CTXDESC_CD_0_TCR_EPD0_SHIFT 14 +#define ARM64_TCR_EPD0_SHIFT 7 +#define ARM64_TCR_EPD0_MASK 0x1UL +#define CTXDESC_CD_0_TCR_EPD1_SHIFT 30 +#define ARM64_TCR_EPD1_SHIFT 23 +#define ARM64_TCR_EPD1_MASK 0x1UL + +#define CTXDESC_CD_0_ENDI (1UL << 15) +#define CTXDESC_CD_0_V (1UL << 31) + +#define CTXDESC_CD_0_TCR_IPS_SHIFT 32 +#define ARM64_TCR_IPS_SHIFT 32 +#define ARM64_TCR_IPS_MASK 0x7UL +#define CTXDESC_CD_0_TCR_TBI0_SHIFT 38 +#define ARM64_TCR_TBI0_SHIFT 37 +#define ARM64_TCR_TBI0_MASK 0x1UL + +#define CTXDESC_CD_0_AA64 (1UL << 41) +#define CTXDESC_CD_0_R (1UL << 45) +#define CTXDESC_CD_0_A (1UL << 46) +#define CTXDESC_CD_0_ASET_SHIFT 47 +#define CTXDESC_CD_0_ASET_SHARED (0UL << CTXDESC_CD_0_ASET_SHIFT) +#define CTXDESC_CD_0_ASET_PRIVATE (1UL << CTXDESC_CD_0_ASET_SHIFT) +#define CTXDESC_CD_0_ASID_SHIFT 48 +#define CTXDESC_CD_0_ASID_MASK 0xffffUL + +#define CTXDESC_CD_1_TTB0_SHIFT 4 +#define CTXDESC_CD_1_TTB0_MASK 0xfffffffffffUL + +#define CTXDESC_CD_3_MAIR_SHIFT 0 + +/* Convert between AArch64 (CPU) TCR format and SMMU CD format */ +#define ARM_SMMU_TCR2CD(tcr, fld) \ + (((tcr) >> ARM64_TCR_##fld##_SHIFT & ARM64_TCR_##fld##_MASK) \ + << CTXDESC_CD_0_TCR_##fld##_SHIFT) + +/* Command queue */ +#define CMDQ_ENT_DWORDS 2 +#define CMDQ_MAX_SZ_SHIFT 8 + +#define CMDQ_ERR_SHIFT 24 +#define CMDQ_ERR_MASK 0x7f +#define CMDQ_ERR_CERROR_NONE_IDX 0 +#define CMDQ_ERR_CERROR_ILL_IDX 1 +#define CMDQ_ERR_CERROR_ABT_IDX 2 + +#define CMDQ_0_OP_SHIFT 0 +#define CMDQ_0_OP_MASK 0xffUL +#define CMDQ_0_SSV (1UL << 11) + +#define CMDQ_PREFETCH_0_SID_SHIFT 32 +#define CMDQ_PREFETCH_1_SIZE_SHIFT 0 +#define CMDQ_PREFETCH_1_ADDR_MASK ~0xfffUL + +#define CMDQ_CFGI_0_SID_SHIFT 32 +#define CMDQ_CFGI_0_SID_MASK 0xffffffffUL +#define CMDQ_CFGI_1_LEAF (1UL << 0) +#define CMDQ_CFGI_1_RANGE_SHIFT 0 +#define CMDQ_CFGI_1_RANGE_MASK 0x1fUL + +#define CMDQ_TLBI_0_VMID_SHIFT 32 +#define CMDQ_TLBI_0_ASID_SHIFT 48 +#define CMDQ_TLBI_1_LEAF (1UL << 0) +#define CMDQ_TLBI_1_ADDR_MASK ~0xfffUL + +#define CMDQ_PRI_0_SSID_SHIFT 12 +#define CMDQ_PRI_0_SSID_MASK 0xfffffUL +#define CMDQ_PRI_0_SID_SHIFT 32 +#define CMDQ_PRI_0_SID_MASK 0xffffffffUL +#define CMDQ_PRI_1_GRPID_SHIFT 0 +#define CMDQ_PRI_1_GRPID_MASK 0x1ffUL +#define CMDQ_PRI_1_RESP_SHIFT 12 +#define CMDQ_PRI_1_RESP_DENY (0UL << CMDQ_PRI_1_RESP_SHIFT) +#define CMDQ_PRI_1_RESP_FAIL (1UL << CMDQ_PRI_1_RESP_SHIFT) +#define CMDQ_PRI_1_RESP_SUCC (2UL << CMDQ_PRI_1_RESP_SHIFT) + +#define CMDQ_SYNC_0_CS_SHIFT 12 +#define CMDQ_SYNC_0_CS_NONE (0UL << CMDQ_SYNC_0_CS_SHIFT) +#define CMDQ_SYNC_0_CS_SEV (2UL << CMDQ_SYNC_0_CS_SHIFT) + +/* Event queue */ +#define EVTQ_ENT_DWORDS 4 +#define EVTQ_MAX_SZ_SHIFT 7 + +#define EVTQ_0_ID_SHIFT 0 +#define EVTQ_0_ID_MASK 0xffUL + +/* PRI queue */ +#define PRIQ_ENT_DWORDS 2 +#define PRIQ_MAX_SZ_SHIFT 8 + +#define PRIQ_0_SID_SHIFT 0 +#define PRIQ_0_SID_MASK 0xffffffffUL +#define PRIQ_0_SSID_SHIFT 32 +#define PRIQ_0_SSID_MASK 0xfffffUL +#define PRIQ_0_OF (1UL << 57) +#define PRIQ_0_PERM_PRIV (1UL << 58) +#define PRIQ_0_PERM_EXEC (1UL << 59) +#define PRIQ_0_PERM_READ (1UL << 60) +#define PRIQ_0_PERM_WRITE (1UL << 61) +#define PRIQ_0_PRG_LAST (1UL << 62) +#define PRIQ_0_SSID_V (1UL << 63) + +#define PRIQ_1_PRG_IDX_SHIFT 0 +#define PRIQ_1_PRG_IDX_MASK 0x1ffUL +#define PRIQ_1_ADDR_SHIFT 12 +#define PRIQ_1_ADDR_MASK 0xfffffffffffffUL + +/* High-level queue structures */ +#define ARM_SMMU_POLL_TIMEOUT_US 100 + +enum pri_resp { + PRI_RESP_DENY, + PRI_RESP_FAIL, + PRI_RESP_SUCC, +}; + +struct arm_smmu_cmdq_ent { + /* Common fields */ + u8 opcode; + bool substream_valid; + + /* Command-specific fields */ + union { + #define CMDQ_OP_PREFETCH_CFG 0x1 + struct { + u32 sid; + u8 size; + u64 addr; + } prefetch; + + #define CMDQ_OP_CFGI_STE 0x3 + #define CMDQ_OP_CFGI_ALL 0x4 + struct { + u32 sid; + union { + bool leaf; + u8 span; + }; + } cfgi; + + #define CMDQ_OP_TLBI_NH_ASID 0x11 + #define CMDQ_OP_TLBI_NH_VA 0x12 + #define CMDQ_OP_TLBI_EL2_ALL 0x20 + #define CMDQ_OP_TLBI_S12_VMALL 0x28 + #define CMDQ_OP_TLBI_S2_IPA 0x2a + #define CMDQ_OP_TLBI_NSNH_ALL 0x30 + struct { + u16 asid; + u16 vmid; + bool leaf; + u64 addr; + } tlbi; + + #define CMDQ_OP_PRI_RESP 0x41 + struct { + u32 sid; + u32 ssid; + u16 grpid; + enum pri_resp resp; + } pri; + + #define CMDQ_OP_CMD_SYNC 0x46 + }; +}; + +struct arm_smmu_queue { + int irq; /* Wired interrupt */ + + __le64 *base; + dma_addr_t base_dma; + u64 q_base; + + size_t ent_dwords; + u32 max_n_shift; + u32 prod; + u32 cons; + + u32 __iomem *prod_reg; + u32 __iomem *cons_reg; +}; + +struct arm_smmu_cmdq { + struct arm_smmu_queue q; + spinlock_t lock; +}; + +struct arm_smmu_evtq { + struct arm_smmu_queue q; + u32 max_stalls; +}; + +struct arm_smmu_priq { + struct arm_smmu_queue q; +}; + +/* High-level stream table and context descriptor structures */ +struct arm_smmu_strtab_l1_desc { + u8 span; + + __le64 *l2ptr; + dma_addr_t l2ptr_dma; +}; + +struct arm_smmu_s1_cfg { + __le64 *cdptr; + dma_addr_t cdptr_dma; + + struct arm_smmu_ctx_desc { + u16 asid; + u64 ttbr; + u64 tcr; + u64 mair; + } cd; +}; + +struct arm_smmu_s2_cfg { + u16 vmid; + u64 vttbr; + u64 vtcr; +}; + +struct arm_smmu_strtab_ent { + bool valid; + + bool bypass; /* Overrides s1/s2 config */ + struct arm_smmu_s1_cfg *s1_cfg; + struct arm_smmu_s2_cfg *s2_cfg; +}; + +struct arm_smmu_strtab_cfg { + __le64 *strtab; + dma_addr_t strtab_dma; + struct arm_smmu_strtab_l1_desc *l1_desc; + unsigned int num_l1_descs; + + u64 strtab_base; + u32 strtab_base_cfg; +}; + +/* An SMMUv3 instance */ +struct arm_smmu_device { + struct device *dev; + void __iomem *base; + +#define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0) +#define ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1) +#define ARM_SMMU_FEAT_TT_LE (1 << 2) +#define ARM_SMMU_FEAT_TT_BE (1 << 3) +#define ARM_SMMU_FEAT_PRI (1 << 4) +#define ARM_SMMU_FEAT_ATS (1 << 5) +#define ARM_SMMU_FEAT_SEV (1 << 6) +#define ARM_SMMU_FEAT_MSI (1 << 7) +#define ARM_SMMU_FEAT_COHERENCY (1 << 8) +#define ARM_SMMU_FEAT_TRANS_S1 (1 << 9) +#define ARM_SMMU_FEAT_TRANS_S2 (1 << 10) +#define ARM_SMMU_FEAT_STALLS (1 << 11) + u32 features; + + struct arm_smmu_cmdq cmdq; + struct arm_smmu_evtq evtq; + struct arm_smmu_priq priq; + + int gerr_irq; + + unsigned long ias; /* IPA */ + unsigned long oas; /* PA */ + +#define ARM_SMMU_MAX_ASIDS (1 << 16) + unsigned int asid_bits; + DECLARE_BITMAP(asid_map, ARM_SMMU_MAX_ASIDS); + +#define ARM_SMMU_MAX_VMIDS (1 << 16) + unsigned int vmid_bits; + DECLARE_BITMAP(vmid_map, ARM_SMMU_MAX_VMIDS); + + unsigned int ssid_bits; + unsigned int sid_bits; + + struct arm_smmu_strtab_cfg strtab_cfg; + struct list_head list; +}; + +/* SMMU private data for an IOMMU group */ +struct arm_smmu_group { + struct arm_smmu_device *smmu; + struct arm_smmu_domain *domain; + int num_sids; + u32 *sids; + struct arm_smmu_strtab_ent ste; +}; + +/* SMMU private data for an IOMMU domain */ +enum arm_smmu_domain_stage { + ARM_SMMU_DOMAIN_S1 = 0, + ARM_SMMU_DOMAIN_S2, + ARM_SMMU_DOMAIN_NESTED, +}; + +struct arm_smmu_domain { + struct arm_smmu_device *smmu; + struct mutex init_mutex; /* Protects smmu pointer */ + + struct io_pgtable_ops *pgtbl_ops; + spinlock_t pgtbl_lock; + + enum arm_smmu_domain_stage stage; + union { + struct arm_smmu_s1_cfg s1_cfg; + struct arm_smmu_s2_cfg s2_cfg; + }; + + struct iommu_domain domain; +}; + +/* Our list of SMMU instances */ +static DEFINE_SPINLOCK(arm_smmu_devices_lock); +static LIST_HEAD(arm_smmu_devices); + +static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) +{ + return container_of(dom, struct arm_smmu_domain, domain); +} + +/* Low-level queue manipulation functions */ +static bool queue_full(struct arm_smmu_queue *q) +{ + return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) && + Q_WRP(q, q->prod) != Q_WRP(q, q->cons); +} + +static bool queue_empty(struct arm_smmu_queue *q) +{ + return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) && + Q_WRP(q, q->prod) == Q_WRP(q, q->cons); +} + +static void queue_sync_cons(struct arm_smmu_queue *q) +{ + q->cons = readl_relaxed(q->cons_reg); +} + +static void queue_inc_cons(struct arm_smmu_queue *q) +{ + u32 cons = (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1; + + q->cons = Q_OVF(q, q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons); + writel(q->cons, q->cons_reg); +} + +static int queue_sync_prod(struct arm_smmu_queue *q) +{ + int ret = 0; + u32 prod = readl_relaxed(q->prod_reg); + + if (Q_OVF(q, prod) != Q_OVF(q, q->prod)) + ret = -EOVERFLOW; + + q->prod = prod; + return ret; +} + +static void queue_inc_prod(struct arm_smmu_queue *q) +{ + u32 prod = (Q_WRP(q, q->prod) | Q_IDX(q, q->prod)) + 1; + + q->prod = Q_OVF(q, q->prod) | Q_WRP(q, prod) | Q_IDX(q, prod); + writel(q->prod, q->prod_reg); +} + +static bool __queue_cons_before(struct arm_smmu_queue *q, u32 until) +{ + if (Q_WRP(q, q->cons) == Q_WRP(q, until)) + return Q_IDX(q, q->cons) < Q_IDX(q, until); + + return Q_IDX(q, q->cons) >= Q_IDX(q, until); +} + +static int queue_poll_cons(struct arm_smmu_queue *q, u32 until, bool wfe) +{ + ktime_t timeout = ktime_add_us(ktime_get(), ARM_SMMU_POLL_TIMEOUT_US); + + while (queue_sync_cons(q), __queue_cons_before(q, until)) { + if (ktime_compare(ktime_get(), timeout) > 0) + return -ETIMEDOUT; + + if (wfe) { + wfe(); + } else { + cpu_relax(); + udelay(1); + } + } + + return 0; +} + +static void queue_write(__le64 *dst, u64 *src, size_t n_dwords) +{ + int i; + + for (i = 0; i < n_dwords; ++i) + *dst++ = cpu_to_le64(*src++); +} + +static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent) +{ + if (queue_full(q)) + return -ENOSPC; + + queue_write(Q_ENT(q, q->prod), ent, q->ent_dwords); + queue_inc_prod(q); + return 0; +} + +static void queue_read(__le64 *dst, u64 *src, size_t n_dwords) +{ + int i; + + for (i = 0; i < n_dwords; ++i) + *dst++ = le64_to_cpu(*src++); +} + +static int queue_remove_raw(struct arm_smmu_queue *q, u64 *ent) +{ + if (queue_empty(q)) + return -EAGAIN; + + queue_read(ent, Q_ENT(q, q->cons), q->ent_dwords); + queue_inc_cons(q); + return 0; +} + +/* High-level queue accessors */ +static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) +{ + memset(cmd, 0, CMDQ_ENT_DWORDS << 3); + cmd[0] |= (ent->opcode & CMDQ_0_OP_MASK) << CMDQ_0_OP_SHIFT; + + switch (ent->opcode) { + case CMDQ_OP_TLBI_EL2_ALL: + case CMDQ_OP_TLBI_NSNH_ALL: + break; + case CMDQ_OP_PREFETCH_CFG: + cmd[0] |= (u64)ent->prefetch.sid << CMDQ_PREFETCH_0_SID_SHIFT; + cmd[1] |= ent->prefetch.size << CMDQ_PREFETCH_1_SIZE_SHIFT; + cmd[1] |= ent->prefetch.addr & CMDQ_PREFETCH_1_ADDR_MASK; + break; + case CMDQ_OP_CFGI_STE: + cmd[0] |= (u64)ent->cfgi.sid << CMDQ_CFGI_0_SID_SHIFT; + cmd[1] |= ent->cfgi.leaf ? CMDQ_CFGI_1_LEAF : 0; + break; + case CMDQ_OP_CFGI_ALL: + /* Cover the entire SID range */ + cmd[1] |= CMDQ_CFGI_1_RANGE_MASK << CMDQ_CFGI_1_RANGE_SHIFT; + break; + case CMDQ_OP_TLBI_NH_VA: + cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT; + /* Fallthrough */ + case CMDQ_OP_TLBI_S2_IPA: + cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT; + cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0; + cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_ADDR_MASK; + break; + case CMDQ_OP_TLBI_NH_ASID: + cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT; + /* Fallthrough */ + case CMDQ_OP_TLBI_S12_VMALL: + cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT; + break; + case CMDQ_OP_PRI_RESP: + cmd[0] |= ent->substream_valid ? CMDQ_0_SSV : 0; + cmd[0] |= ent->pri.ssid << CMDQ_PRI_0_SSID_SHIFT; + cmd[0] |= (u64)ent->pri.sid << CMDQ_PRI_0_SID_SHIFT; + cmd[1] |= ent->pri.grpid << CMDQ_PRI_1_GRPID_SHIFT; + switch (ent->pri.resp) { + case PRI_RESP_DENY: + cmd[1] |= CMDQ_PRI_1_RESP_DENY; + break; + case PRI_RESP_FAIL: + cmd[1] |= CMDQ_PRI_1_RESP_FAIL; + break; + case PRI_RESP_SUCC: + cmd[1] |= CMDQ_PRI_1_RESP_SUCC; + break; + default: + return -EINVAL; + } + break; + case CMDQ_OP_CMD_SYNC: + cmd[0] |= CMDQ_SYNC_0_CS_SEV; + break; + default: + return -ENOENT; + } + + return 0; +} + +static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) +{ + static const char *cerror_str[] = { + [CMDQ_ERR_CERROR_NONE_IDX] = "No error", + [CMDQ_ERR_CERROR_ILL_IDX] = "Illegal command", + [CMDQ_ERR_CERROR_ABT_IDX] = "Abort on command fetch", + }; + + int i; + u64 cmd[CMDQ_ENT_DWORDS]; + struct arm_smmu_queue *q = &smmu->cmdq.q; + u32 cons = readl_relaxed(q->cons_reg); + u32 idx = cons >> CMDQ_ERR_SHIFT & CMDQ_ERR_MASK; + struct arm_smmu_cmdq_ent cmd_sync = { + .opcode = CMDQ_OP_CMD_SYNC, + }; + + dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, + cerror_str[idx]); + + switch (idx) { + case CMDQ_ERR_CERROR_ILL_IDX: + break; + case CMDQ_ERR_CERROR_ABT_IDX: + dev_err(smmu->dev, "retrying command fetch\n"); + case CMDQ_ERR_CERROR_NONE_IDX: + return; + } + + /* + * We may have concurrent producers, so we need to be careful + * not to touch any of the shadow cmdq state. + */ + queue_read(cmd, Q_ENT(q, idx), q->ent_dwords); + dev_err(smmu->dev, "skipping command in error state:\n"); + for (i = 0; i < ARRAY_SIZE(cmd); ++i) + dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); + + /* Convert the erroneous command into a CMD_SYNC */ + if (arm_smmu_cmdq_build_cmd(cmd, &cmd_sync)) { + dev_err(smmu->dev, "failed to convert to CMD_SYNC\n"); + return; + } + + queue_write(cmd, Q_ENT(q, idx), q->ent_dwords); +} + +static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_ent *ent) +{ + u32 until; + u64 cmd[CMDQ_ENT_DWORDS]; + bool wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV); + struct arm_smmu_queue *q = &smmu->cmdq.q; + + if (arm_smmu_cmdq_build_cmd(cmd, ent)) { + dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n", + ent->opcode); + return; + } + + spin_lock(&smmu->cmdq.lock); + while (until = q->prod + 1, queue_insert_raw(q, cmd) == -ENOSPC) { + /* + * Keep the queue locked, otherwise the producer could wrap + * twice and we could see a future consumer pointer that looks + * like it's behind us. + */ + if (queue_poll_cons(q, until, wfe)) + dev_err_ratelimited(smmu->dev, "CMDQ timeout\n"); + } + + if (ent->opcode == CMDQ_OP_CMD_SYNC && queue_poll_cons(q, until, wfe)) + dev_err_ratelimited(smmu->dev, "CMD_SYNC timeout\n"); + spin_unlock(&smmu->cmdq.lock); +} + +/* Context descriptor manipulation functions */ +static u64 arm_smmu_cpu_tcr_to_cd(u64 tcr) +{ + u64 val = 0; + + /* Repack the TCR. Just care about TTBR0 for now */ + val |= ARM_SMMU_TCR2CD(tcr, T0SZ); + val |= ARM_SMMU_TCR2CD(tcr, TG0); + val |= ARM_SMMU_TCR2CD(tcr, IRGN0); + val |= ARM_SMMU_TCR2CD(tcr, ORGN0); + val |= ARM_SMMU_TCR2CD(tcr, SH0); + val |= ARM_SMMU_TCR2CD(tcr, EPD0); + val |= ARM_SMMU_TCR2CD(tcr, EPD1); + val |= ARM_SMMU_TCR2CD(tcr, IPS); + val |= ARM_SMMU_TCR2CD(tcr, TBI0); + + return val; +} + +static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu, + struct arm_smmu_s1_cfg *cfg) +{ + u64 val; + + /* + * We don't need to issue any invalidation here, as we'll invalidate + * the STE when installing the new entry anyway. + */ + val = arm_smmu_cpu_tcr_to_cd(cfg->cd.tcr) | +#ifdef __BIG_ENDIAN + CTXDESC_CD_0_ENDI | +#endif + CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET_PRIVATE | + CTXDESC_CD_0_AA64 | (u64)cfg->cd.asid << CTXDESC_CD_0_ASID_SHIFT | + CTXDESC_CD_0_V; + cfg->cdptr[0] = cpu_to_le64(val); + + val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK << CTXDESC_CD_1_TTB0_SHIFT; + cfg->cdptr[1] = cpu_to_le64(val); + + cfg->cdptr[3] = cpu_to_le64(cfg->cd.mair << CTXDESC_CD_3_MAIR_SHIFT); +} + +/* Stream table manipulation functions */ +static void +arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc) +{ + u64 val = 0; + + val |= (desc->span & STRTAB_L1_DESC_SPAN_MASK) + << STRTAB_L1_DESC_SPAN_SHIFT; + val |= desc->l2ptr_dma & + STRTAB_L1_DESC_L2PTR_MASK << STRTAB_L1_DESC_L2PTR_SHIFT; + + *dst = cpu_to_le64(val); +} + +static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) +{ + struct arm_smmu_cmdq_ent cmd = { + .opcode = CMDQ_OP_CFGI_STE, + .cfgi = { + .sid = sid, + .leaf = true, + }, + }; + + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + cmd.opcode = CMDQ_OP_CMD_SYNC; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); +} + +static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid, + __le64 *dst, struct arm_smmu_strtab_ent *ste) +{ + /* + * This is hideously complicated, but we only really care about + * three cases@the moment: + * + * 1. Invalid (all zero) -> bypass (init) + * 2. Bypass -> translation (attach) + * 3. Translation -> bypass (detach) + * + * Given that we can't update the STE atomically and the SMMU + * doesn't read the thing in a defined order, that leaves us + * with the following maintenance requirements: + * + * 1. Update Config, return (init time STEs aren't live) + * 2. Write everything apart from dword 0, sync, write dword 0, sync + * 3. Update Config, sync + */ + u64 val = le64_to_cpu(dst[0]); + bool ste_live = false; + struct arm_smmu_cmdq_ent prefetch_cmd = { + .opcode = CMDQ_OP_PREFETCH_CFG, + .prefetch = { + .sid = sid, + }, + }; + + if (val & STRTAB_STE_0_V) { + u64 cfg; + + cfg = val & STRTAB_STE_0_CFG_MASK << STRTAB_STE_0_CFG_SHIFT; + switch (cfg) { + case STRTAB_STE_0_CFG_BYPASS: + break; + case STRTAB_STE_0_CFG_S1_TRANS: + case STRTAB_STE_0_CFG_S2_TRANS: + ste_live = true; + break; + default: + BUG(); /* STE corruption */ + } + } + + /* Nuke the existing Config, as we're going to rewrite it */ + val &= ~(STRTAB_STE_0_CFG_MASK << STRTAB_STE_0_CFG_SHIFT); + + if (ste->valid) + val |= STRTAB_STE_0_V; + else + val &= ~STRTAB_STE_0_V; + + if (ste->bypass) { + val |= STRTAB_STE_0_CFG_BYPASS; + dst[0] = cpu_to_le64(val); + dst[2] = 0; /* Nuke the VMID */ + if (ste_live) + arm_smmu_sync_ste_for_sid(smmu, sid); + return; + } + + if (ste->s1_cfg) { + BUG_ON(ste_live); + dst[1] = cpu_to_le64( + STRTAB_STE_1_S1C_CACHE_WBRA + << STRTAB_STE_1_S1CIR_SHIFT | + STRTAB_STE_1_S1C_CACHE_WBRA + << STRTAB_STE_1_S1COR_SHIFT | + STRTAB_STE_1_S1C_SH_ISH << STRTAB_STE_1_S1CSH_SHIFT | + STRTAB_STE_1_S1STALLD | +#ifdef CONFIG_PCI_ATS + STRTAB_STE_1_EATS_TRANS << STRTAB_STE_1_EATS_SHIFT | +#endif + STRTAB_STE_1_STRW_NSEL1 << STRTAB_STE_1_STRW_SHIFT); + + val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK + << STRTAB_STE_0_S1CTXPTR_SHIFT) | + STRTAB_STE_0_CFG_S1_TRANS; + + } + + if (ste->s2_cfg) { + BUG_ON(ste_live); + dst[2] = cpu_to_le64( + ste->s2_cfg->vmid << STRTAB_STE_2_S2VMID_SHIFT | + (ste->s2_cfg->vtcr & STRTAB_STE_2_VTCR_MASK) + << STRTAB_STE_2_VTCR_SHIFT | +#ifdef __BIG_ENDIAN + STRTAB_STE_2_S2ENDI | +#endif + STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 | + STRTAB_STE_2_S2R); + + dst[3] = cpu_to_le64(ste->s2_cfg->vttbr & + STRTAB_STE_3_S2TTB_MASK << STRTAB_STE_3_S2TTB_SHIFT); + + val |= STRTAB_STE_0_CFG_S2_TRANS; + } + + arm_smmu_sync_ste_for_sid(smmu, sid); + dst[0] = cpu_to_le64(val); + arm_smmu_sync_ste_for_sid(smmu, sid); + + /* It's likely that we'll want to use the new STE soon */ + arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd); +} + +/* IRQ and event handlers */ +static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev) +{ + int i; + struct arm_smmu_device *smmu = dev; + struct arm_smmu_queue *q = &smmu->evtq.q; + u64 evt[EVTQ_ENT_DWORDS]; + + while (!queue_remove_raw(q, evt)) { + u8 id = evt[0] >> EVTQ_0_ID_SHIFT & EVTQ_0_ID_MASK; + + dev_info(smmu->dev, "event 0x%02x received:\n", id); + for (i = 0; i < ARRAY_SIZE(evt); ++i) + dev_info(smmu->dev, "\t0x%016llx\n", + (unsigned long long)evt[i]); + } + + /* Sync our overflow flag, as we believe we're up to speed */ + q->cons = Q_OVF(q, q->prod) | Q_WRP(q, q->cons) | Q_IDX(q, q->cons); + return IRQ_HANDLED; +} + +static irqreturn_t arm_smmu_evtq_handler(int irq, void *dev) +{ + irqreturn_t ret = IRQ_WAKE_THREAD; + struct arm_smmu_device *smmu = dev; + struct arm_smmu_queue *q = &smmu->evtq.q; + + /* + * Not much we can do on overflow, so scream and pretend we're + * trying harder. + */ + if (queue_sync_prod(q) == -EOVERFLOW) + dev_err(smmu->dev, "EVTQ overflow detected -- events lost\n"); + else if (queue_empty(q)) + ret = IRQ_NONE; + + return ret; +} + +static irqreturn_t arm_smmu_priq_thread(int irq, void *dev) +{ + struct arm_smmu_device *smmu = dev; + struct arm_smmu_queue *q = &smmu->priq.q; + u64 evt[PRIQ_ENT_DWORDS]; + + while (!queue_remove_raw(q, evt)) { + u32 sid, ssid; + u16 grpid; + bool ssv, last; + + sid = evt[0] >> PRIQ_0_SID_SHIFT & PRIQ_0_SID_MASK; + ssv = evt[0] & PRIQ_0_SSID_V; + ssid = ssv ? evt[0] >> PRIQ_0_SSID_SHIFT & PRIQ_0_SSID_MASK : 0; + last = evt[0] & PRIQ_0_PRG_LAST; + grpid = evt[1] >> PRIQ_1_PRG_IDX_SHIFT & PRIQ_1_PRG_IDX_MASK; + + dev_info(smmu->dev, "unexpected PRI request received:\n"); + dev_info(smmu->dev, + "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016llx\n", + sid, ssid, grpid, last ? "L" : "", + evt[0] & PRIQ_0_PERM_PRIV ? "" : "un", + evt[0] & PRIQ_0_PERM_READ ? "R" : "", + evt[0] & PRIQ_0_PERM_WRITE ? "W" : "", + evt[0] & PRIQ_0_PERM_EXEC ? "X" : "", + evt[1] & PRIQ_1_ADDR_MASK << PRIQ_1_ADDR_SHIFT); + + if (last) { + struct arm_smmu_cmdq_ent cmd = { + .opcode = CMDQ_OP_PRI_RESP, + .substream_valid = ssv, + .pri = { + .sid = sid, + .ssid = ssid, + .grpid = grpid, + .resp = PRI_RESP_DENY, + }, + }; + + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + } + } + + /* Sync our overflow flag, as we believe we're up to speed */ + q->cons = Q_OVF(q, q->prod) | Q_WRP(q, q->cons) | Q_IDX(q, q->cons); + return IRQ_HANDLED; +} + +static irqreturn_t arm_smmu_priq_handler(int irq, void *dev) +{ + irqreturn_t ret = IRQ_WAKE_THREAD; + struct arm_smmu_device *smmu = dev; + struct arm_smmu_queue *q = &smmu->priq.q; + + /* PRIQ overflow indicates a programming error */ + if (queue_sync_prod(q) == -EOVERFLOW) + dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n"); + else if (queue_empty(q)) + ret = IRQ_NONE; + + return ret; +} + +static irqreturn_t arm_smmu_cmdq_sync_handler(int irq, void *dev) +{ + /* We don't actually use CMD_SYNC interrupts for anything */ + return IRQ_HANDLED; +} + +static int arm_smmu_device_disable(struct arm_smmu_device *smmu); + +static irqreturn_t arm_smmu_gerror_handler(int irq, void *dev) +{ + u32 gerror, gerrorn; + struct arm_smmu_device *smmu = dev; + + gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR); + gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); + + gerror ^= gerrorn; + if (!(gerror & GERROR_ERR_MASK)) + return IRQ_NONE; /* No errors pending */ + + dev_warn(smmu->dev, + "unexpected global error reported (0x%08x), this could be serious\n", + gerror); + + if (gerror & GERROR_SFM_ERR) { + dev_err(smmu->dev, "device has entered Service Failure Mode!\n"); + arm_smmu_device_disable(smmu); + } + + if (gerror & GERROR_MSI_GERROR_ABT_ERR) + dev_warn(smmu->dev, "GERROR MSI write aborted\n"); + + if (gerror & GERROR_MSI_PRIQ_ABT_ERR) { + dev_warn(smmu->dev, "PRIQ MSI write aborted\n"); + arm_smmu_priq_handler(irq, smmu->dev); + } + + if (gerror & GERROR_MSI_EVTQ_ABT_ERR) { + dev_warn(smmu->dev, "EVTQ MSI write aborted\n"); + arm_smmu_evtq_handler(irq, smmu->dev); + } + + if (gerror & GERROR_MSI_CMDQ_ABT_ERR) { + dev_warn(smmu->dev, "CMDQ MSI write aborted\n"); + arm_smmu_cmdq_sync_handler(irq, smmu->dev); + } + + if (gerror & GERROR_PRIQ_ABT_ERR) + dev_err(smmu->dev, "PRIQ write aborted -- events may have been lost\n"); + + if (gerror & GERROR_EVTQ_ABT_ERR) + dev_err(smmu->dev, "EVTQ write aborted -- events may have been lost\n"); + + if (gerror & GERROR_CMDQ_ERR) + arm_smmu_cmdq_skip_err(smmu); + + writel(gerror, smmu->base + ARM_SMMU_GERRORN); + return IRQ_HANDLED; +} + +/* IO_PGTABLE API */ +static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu) +{ + struct arm_smmu_cmdq_ent cmd; + + cmd.opcode = CMDQ_OP_CMD_SYNC; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); +} + +static void arm_smmu_tlb_sync(void *cookie) +{ + struct arm_smmu_domain *smmu_domain = cookie; + __arm_smmu_tlb_sync(smmu_domain->smmu); +} + +static void arm_smmu_tlb_inv_context(void *cookie) +{ + struct arm_smmu_domain *smmu_domain = cookie; + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_cmdq_ent cmd; + + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { + cmd.opcode = CMDQ_OP_TLBI_NH_ASID; + cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; + cmd.tlbi.vmid = 0; + } else { + cmd.opcode = CMDQ_OP_TLBI_S12_VMALL; + cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; + } + + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + __arm_smmu_tlb_sync(smmu); +} + +static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, + bool leaf, void *cookie) +{ + struct arm_smmu_domain *smmu_domain = cookie; + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_cmdq_ent cmd = { + .tlbi = { + .leaf = leaf, + .addr = iova, + }, + }; + + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { + cmd.opcode = CMDQ_OP_TLBI_NH_VA; + cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; + } else { + cmd.opcode = CMDQ_OP_TLBI_S2_IPA; + cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; + } + + arm_smmu_cmdq_issue_cmd(smmu, &cmd); +} + +static void arm_smmu_flush_pgtable(void *addr, size_t size, void *cookie) +{ + struct arm_smmu_domain *smmu_domain = cookie; + struct arm_smmu_device *smmu = smmu_domain->smmu; + unsigned long offset = (unsigned long)addr & ~PAGE_MASK; + + if (smmu->features & ARM_SMMU_FEAT_COHERENCY) { + dsb(ishst); + } else { + dma_addr_t dma_addr; + struct device *dev = smmu->dev; + + dma_addr = dma_map_page(dev, virt_to_page(addr), offset, size, + DMA_TO_DEVICE); + + if (dma_mapping_error(dev, dma_addr)) + dev_err(dev, "failed to flush pgtable at %p\n", addr); + else + dma_unmap_page(dev, dma_addr, size, DMA_TO_DEVICE); + } +} + +static struct iommu_gather_ops arm_smmu_gather_ops = { + .tlb_flush_all = arm_smmu_tlb_inv_context, + .tlb_add_flush = arm_smmu_tlb_inv_range_nosync, + .tlb_sync = arm_smmu_tlb_sync, + .flush_pgtable = arm_smmu_flush_pgtable, +}; + +/* IOMMU API */ +static bool arm_smmu_capable(enum iommu_cap cap) +{ + switch (cap) { + case IOMMU_CAP_CACHE_COHERENCY: + return true; + case IOMMU_CAP_INTR_REMAP: + return true; /* MSIs are just memory writes */ + case IOMMU_CAP_NOEXEC: + return true; + default: + return false; + } +} + +static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) +{ + struct arm_smmu_domain *smmu_domain; + + if (type != IOMMU_DOMAIN_UNMANAGED) + return NULL; + + /* + * Allocate the domain and initialise some of its data structures. + * We can't really do anything meaningful until we've added a + * master. + */ + smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); + if (!smmu_domain) + return NULL; + + mutex_init(&smmu_domain->init_mutex); + spin_lock_init(&smmu_domain->pgtbl_lock); + return &smmu_domain->domain; +} + +static int arm_smmu_bitmap_alloc(unsigned long *map, int span) +{ + int idx, size = 1 << span; + + do { + idx = find_first_zero_bit(map, size); + if (idx == size) + return -ENOSPC; + } while (test_and_set_bit(idx, map)); + + return idx; +} + +static void arm_smmu_bitmap_free(unsigned long *map, int idx) +{ + clear_bit(idx, map); +} + +static void arm_smmu_domain_free(struct iommu_domain *domain) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_device *smmu = smmu_domain->smmu; + + if (smmu_domain->pgtbl_ops) + free_io_pgtable_ops(smmu_domain->pgtbl_ops); + + /* Free the CD and ASID, if we allocated them */ + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { + struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; + + if (cfg->cdptr) { + dma_free_coherent(smmu_domain->smmu->dev, + CTXDESC_CD_DWORDS << 3, + cfg->cdptr, + cfg->cdptr_dma); + + arm_smmu_bitmap_free(smmu->asid_map, cfg->cd.asid); + } + } else { + struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; + if (cfg->vmid) + arm_smmu_bitmap_free(smmu->vmid_map, cfg->vmid); + } + + kfree(smmu_domain); +} + +static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, + struct io_pgtable_cfg *pgtbl_cfg) +{ + int ret; + u16 asid; + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; + + asid = arm_smmu_bitmap_alloc(smmu->asid_map, smmu->asid_bits); + if (IS_ERR_VALUE(asid)) + return asid; + + cfg->cdptr = dma_zalloc_coherent(smmu->dev, CTXDESC_CD_DWORDS << 3, + &cfg->cdptr_dma, GFP_KERNEL); + if (!cfg->cdptr) { + dev_warn(smmu->dev, "failed to allocate context descriptor\n"); + goto out_free_asid; + } + + cfg->cd.asid = asid; + cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; + cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr; + cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; + return 0; + +out_free_asid: + arm_smmu_bitmap_free(smmu->asid_map, asid); + return ret; +} + +static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, + struct io_pgtable_cfg *pgtbl_cfg) +{ + u16 vmid; + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; + + vmid = arm_smmu_bitmap_alloc(smmu->vmid_map, smmu->vmid_bits); + if (IS_ERR_VALUE(vmid)) + return vmid; + + cfg->vmid = vmid; + cfg->vttbr = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; + cfg->vtcr = pgtbl_cfg->arm_lpae_s2_cfg.vtcr; + return 0; +} + +static struct iommu_ops arm_smmu_ops; + +static int arm_smmu_domain_finalise(struct iommu_domain *domain) +{ + int ret; + unsigned long ias, oas; + enum io_pgtable_fmt fmt; + struct io_pgtable_cfg pgtbl_cfg; + struct io_pgtable_ops *pgtbl_ops; + int (*finalise_stage_fn)(struct arm_smmu_domain *, + struct io_pgtable_cfg *); + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_device *smmu = smmu_domain->smmu; + + /* Restrict the stage to what we can actually support */ + if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) + smmu_domain->stage = ARM_SMMU_DOMAIN_S2; + if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) + smmu_domain->stage = ARM_SMMU_DOMAIN_S1; + + switch (smmu_domain->stage) { + case ARM_SMMU_DOMAIN_S1: + ias = VA_BITS; + oas = smmu->ias; + fmt = ARM_64_LPAE_S1; + finalise_stage_fn = arm_smmu_domain_finalise_s1; + break; + case ARM_SMMU_DOMAIN_NESTED: + case ARM_SMMU_DOMAIN_S2: + ias = smmu->ias; + oas = smmu->oas; + fmt = ARM_64_LPAE_S2; + finalise_stage_fn = arm_smmu_domain_finalise_s2; + break; + default: + return -EINVAL; + } + + pgtbl_cfg = (struct io_pgtable_cfg) { + .pgsize_bitmap = arm_smmu_ops.pgsize_bitmap, + .ias = ias, + .oas = oas, + .tlb = &arm_smmu_gather_ops, + }; + + pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain); + if (!pgtbl_ops) + return -ENOMEM; + + arm_smmu_ops.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; + smmu_domain->pgtbl_ops = pgtbl_ops; + + ret = finalise_stage_fn(smmu_domain, &pgtbl_cfg); + if (IS_ERR_VALUE(ret)) + free_io_pgtable_ops(pgtbl_ops); + + return ret; +} + +static struct arm_smmu_group *arm_smmu_group_get(struct device *dev) +{ + struct iommu_group *group; + struct arm_smmu_group *smmu_group; + + group = iommu_group_get(dev); + if (!group) + return NULL; + + smmu_group = iommu_group_get_iommudata(group); + iommu_group_put(group); + return smmu_group; +} + +static __le64 *arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid) +{ + __le64 *step; + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; + + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { + struct arm_smmu_strtab_l1_desc *l1_desc; + int idx; + + /* Two-level walk */ + idx = (sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS; + l1_desc = &cfg->l1_desc[idx]; + idx = (sid & ((1 << STRTAB_SPLIT) - 1)) * STRTAB_STE_DWORDS; + step = &l1_desc->l2ptr[idx]; + } else { + /* Simple linear lookup */ + step = &cfg->strtab[sid * STRTAB_STE_DWORDS]; + } + + return step; +} + +static int arm_smmu_install_ste_for_group(struct arm_smmu_group *smmu_group) +{ + int i; + struct arm_smmu_domain *smmu_domain = smmu_group->domain; + struct arm_smmu_strtab_ent *ste = &smmu_group->ste; + struct arm_smmu_device *smmu = smmu_group->smmu; + + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { + ste->s1_cfg = &smmu_domain->s1_cfg; + ste->s2_cfg = NULL; + arm_smmu_write_ctx_desc(smmu, ste->s1_cfg); + } else { + ste->s1_cfg = NULL; + ste->s2_cfg = &smmu_domain->s2_cfg; + } + + for (i = 0; i < smmu_group->num_sids; ++i) { + u32 sid = smmu_group->sids[i]; + __le64 *step = arm_smmu_get_step_for_sid(smmu, sid); + + arm_smmu_write_strtab_ent(smmu, sid, step, ste); + } + + return 0; +} + +static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) +{ + int ret = 0; + struct arm_smmu_device *smmu; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_group *smmu_group = arm_smmu_group_get(dev); + + if (!smmu_group) + return -ENOENT; + + /* Already attached to a different domain? */ + if (smmu_group->domain && smmu_group->domain != smmu_domain) + return -EEXIST; + + smmu = smmu_group->smmu; + mutex_lock(&smmu_domain->init_mutex); + + if (!smmu_domain->smmu) { + smmu_domain->smmu = smmu; + ret = arm_smmu_domain_finalise(domain); + if (ret) { + smmu_domain->smmu = NULL; + goto out_unlock; + } + } else if (smmu_domain->smmu != smmu) { + dev_err(dev, + "cannot attach to SMMU %s (upstream of %s)\n", + dev_name(smmu_domain->smmu->dev), + dev_name(smmu->dev)); + ret = -ENXIO; + goto out_unlock; + } + + /* Group already attached to this domain? */ + if (smmu_group->domain) + goto out_unlock; + + smmu_group->domain = smmu_domain; + smmu_group->ste.bypass = false; + + ret = arm_smmu_install_ste_for_group(smmu_group); + if (IS_ERR_VALUE(ret)) + smmu_group->domain = NULL; + +out_unlock: + mutex_unlock(&smmu_domain->init_mutex); + return ret; +} + +static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_group *smmu_group = arm_smmu_group_get(dev); + + BUG_ON(!smmu_domain); + BUG_ON(!smmu_group); + + mutex_lock(&smmu_domain->init_mutex); + BUG_ON(smmu_group->domain != smmu_domain); + + smmu_group->ste.bypass = true; + if (IS_ERR_VALUE(arm_smmu_install_ste_for_group(smmu_group))) + dev_warn(dev, "failed to install bypass STE\n"); + + smmu_group->domain = NULL; + mutex_unlock(&smmu_domain->init_mutex); +} + +static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, + phys_addr_t paddr, size_t size, int prot) +{ + int ret; + unsigned long flags; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; + + if (!ops) + return -ENODEV; + + spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); + ret = ops->map(ops, iova, paddr, size, prot); + spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); + return ret; +} + +static size_t +arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size) +{ + size_t ret; + unsigned long flags; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; + + if (!ops) + return 0; + + spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); + ret = ops->unmap(ops, iova, size); + spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); + return ret; +} + +static phys_addr_t +arm_smmu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) +{ + phys_addr_t ret; + unsigned long flags; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; + + if (!ops) + return 0; + + spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); + ret = ops->iova_to_phys(ops, iova); + spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); + + return ret; +} + +static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *sidp) +{ + *(u32 *)sidp = alias; + return 0; /* Continue walking */ +} + +static void __arm_smmu_release_pci_iommudata(void *data) +{ + kfree(data); +} + +static struct arm_smmu_device *arm_smmu_get_for_pci_dev(struct pci_dev *pdev) +{ + struct device_node *of_node; + struct arm_smmu_device *curr, *smmu = NULL; + struct pci_bus *bus = pdev->bus; + + /* Walk up to the root bus */ + while (!pci_is_root_bus(bus)) + bus = bus->parent; + + /* Follow the "iommus" phandle from the host controller */ + of_node = of_parse_phandle(bus->bridge->parent->of_node, "iommus", 0); + if (!of_node) + return NULL; + + /* See if we can find an SMMU corresponding to the phandle */ + spin_lock(&arm_smmu_devices_lock); + list_for_each_entry(curr, &arm_smmu_devices, list) { + if (curr->dev->of_node == of_node) { + smmu = curr; + break; + } + } + spin_unlock(&arm_smmu_devices_lock); + of_node_put(of_node); + return smmu; +} + +static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) +{ + unsigned long limit; + + if (sid < (1UL << smmu->sid_bits)) + return true; + + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { + limit = 1UL << (STRTAB_L1_SZ_SHIFT - + (ilog2(STRTAB_L1_DESC_DWORDS) + 3) + + STRTAB_SPLIT); + } else { + limit = 1UL << (STRTAB_L1_SZ_SHIFT - + (ilog2(STRTAB_STE_DWORDS) + 3)); + } + + return sid < limit; +} + +static int arm_smmu_add_device(struct device *dev) +{ + int i, ret; + u32 sid, *sids; + struct pci_dev *pdev; + struct iommu_group *group; + struct arm_smmu_group *smmu_group; + + /* We only support PCI, for now */ + if (!dev_is_pci(dev)) + return -ENODEV; + + pdev = to_pci_dev(dev); + group = iommu_group_get_for_dev(dev); + if (IS_ERR(group)) + return PTR_ERR(group); + + smmu_group = iommu_group_get_iommudata(group); + if (!smmu_group) { + struct arm_smmu_device *smmu = arm_smmu_get_for_pci_dev(pdev); + if (!smmu) { + ret = -ENOENT; + goto out_put_group; + } + + smmu_group = kzalloc(sizeof(*smmu_group), GFP_KERNEL); + if (!smmu_group) { + ret = -ENOMEM; + goto out_put_group; + } + + smmu_group->ste.valid = true; + smmu_group->smmu = smmu; + iommu_group_set_iommudata(group, smmu_group, + __arm_smmu_release_pci_iommudata); + } + + /* Assume SID == RID until firmware tells us otherwise */ + pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid); + for (i = 0; i < smmu_group->num_sids; ++i) { + /* If we already know about this SID, then we're done */ + if (smmu_group->sids[i] == sid) + return 0; + } + + /* Check the SID is in range of the SMMU and our stream table */ + if (!arm_smmu_sid_in_range(smmu_group->smmu, sid)) { + ret = -ERANGE; + goto out_put_group; + } + + /* Resize the SID array for the group */ + smmu_group->num_sids++; + sids = krealloc(smmu_group->sids, smmu_group->num_sids * sizeof(*sids), + GFP_KERNEL); + if (!sids) { + smmu_group->num_sids--; + ret = -ENOMEM; + goto out_put_group; + } + + /* Add the new SID */ + sids[smmu_group->num_sids - 1] = sid; + smmu_group->sids = sids; + return 0; + +out_put_group: + iommu_group_put(group); + return ret; +} + +static void arm_smmu_remove_device(struct device *dev) +{ + iommu_group_remove_device(dev); +} + +static int arm_smmu_domain_get_attr(struct iommu_domain *domain, + enum iommu_attr attr, void *data) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + + switch (attr) { + case DOMAIN_ATTR_NESTING: + *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED); + return 0; + default: + return -ENODEV; + } +} + +static int arm_smmu_domain_set_attr(struct iommu_domain *domain, + enum iommu_attr attr, void *data) +{ + int ret = 0; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + + mutex_lock(&smmu_domain->init_mutex); + + switch (attr) { + case DOMAIN_ATTR_NESTING: + if (smmu_domain->smmu) { + ret = -EPERM; + goto out_unlock; + } + + if (*(int *)data) + smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED; + else + smmu_domain->stage = ARM_SMMU_DOMAIN_S1; + + break; + default: + ret = -ENODEV; + } + +out_unlock: + mutex_unlock(&smmu_domain->init_mutex); + return ret; +} + +static struct iommu_ops arm_smmu_ops = { + .capable = arm_smmu_capable, + .domain_alloc = arm_smmu_domain_alloc, + .domain_free = arm_smmu_domain_free, + .attach_dev = arm_smmu_attach_dev, + .detach_dev = arm_smmu_detach_dev, + .map = arm_smmu_map, + .unmap = arm_smmu_unmap, + .iova_to_phys = arm_smmu_iova_to_phys, + .add_device = arm_smmu_add_device, + .remove_device = arm_smmu_remove_device, + .domain_get_attr = arm_smmu_domain_get_attr, + .domain_set_attr = arm_smmu_domain_set_attr, + .pgsize_bitmap = -1UL, /* Restricted during device attach */ +}; + +/* Probing and initialisation functions */ +static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, + struct arm_smmu_queue *q, + unsigned long prod_off, + unsigned long cons_off, + size_t dwords) +{ + size_t qsz = ((1 << q->max_n_shift) * dwords) << 3; + + q->base = dma_alloc_coherent(smmu->dev, qsz, &q->base_dma, GFP_KERNEL); + if (!q->base) { + dev_err(smmu->dev, "failed to allocate queue (0x%zx bytes)\n", + qsz); + return -ENOMEM; + } + + q->prod_reg = smmu->base + prod_off; + q->cons_reg = smmu->base + cons_off; + q->ent_dwords = dwords; + + q->q_base = Q_BASE_RWA; + q->q_base |= q->base_dma & Q_BASE_ADDR_MASK << Q_BASE_ADDR_SHIFT; + q->q_base |= (q->max_n_shift & Q_BASE_LOG2SIZE_MASK) + << Q_BASE_LOG2SIZE_SHIFT; + + q->prod = q->cons = 0; + return 0; +} + +static void arm_smmu_free_one_queue(struct arm_smmu_device *smmu, + struct arm_smmu_queue *q) +{ + size_t qsz = ((1 << q->max_n_shift) * q->ent_dwords) << 3; + + dma_free_coherent(smmu->dev, qsz, q->base, q->base_dma); +} + +static void arm_smmu_free_queues(struct arm_smmu_device *smmu) +{ + arm_smmu_free_one_queue(smmu, &smmu->cmdq.q); + arm_smmu_free_one_queue(smmu, &smmu->evtq.q); + + if (smmu->features & ARM_SMMU_FEAT_PRI) + arm_smmu_free_one_queue(smmu, &smmu->priq.q); +} + +static int arm_smmu_init_queues(struct arm_smmu_device *smmu) +{ + int ret; + + /* cmdq */ + spin_lock_init(&smmu->cmdq.lock); + ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, ARM_SMMU_CMDQ_PROD, + ARM_SMMU_CMDQ_CONS, CMDQ_ENT_DWORDS); + if (ret) + goto out; + + /* evtq */ + ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, ARM_SMMU_EVTQ_PROD, + ARM_SMMU_EVTQ_CONS, EVTQ_ENT_DWORDS); + if (ret) + goto out_free_cmdq; + + /* priq */ + if (!(smmu->features & ARM_SMMU_FEAT_PRI)) + return 0; + + ret = arm_smmu_init_one_queue(smmu, &smmu->priq.q, ARM_SMMU_PRIQ_PROD, + ARM_SMMU_PRIQ_CONS, PRIQ_ENT_DWORDS); + if (ret) + goto out_free_evtq; + + return 0; + +out_free_evtq: + arm_smmu_free_one_queue(smmu, &smmu->evtq.q); +out_free_cmdq: + arm_smmu_free_one_queue(smmu, &smmu->cmdq.q); +out: + return ret; +} + +static void arm_smmu_free_l2_strtab(struct arm_smmu_device *smmu) +{ + int i; + size_t size; + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; + + size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3); + for (i = 0; i < cfg->num_l1_descs; ++i) { + struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[i]; + + if (!desc->l2ptr) + continue; + + dma_free_coherent(smmu->dev, size, desc->l2ptr, + desc->l2ptr_dma); + } +} + +static void arm_smmu_init_bypass_stes(u64 *strtab, unsigned int nent) +{ + unsigned int i; + struct arm_smmu_strtab_ent ste = { + .valid = true, + .bypass = true, + }; + + for (i = 0; i < nent; ++i) { + arm_smmu_write_strtab_ent(NULL, -1, strtab, &ste); + strtab += STRTAB_STE_DWORDS; + } +} + +static int arm_smmu_alloc_l2_strtab(struct arm_smmu_device *smmu) +{ + int ret; + unsigned int i; + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; + size_t size = sizeof(*cfg->l1_desc) * cfg->num_l1_descs; + void *strtab = smmu->strtab_cfg.strtab; + + cfg->l1_desc = devm_kzalloc(smmu->dev, size, GFP_KERNEL); + if (!cfg->l1_desc) { + dev_err(smmu->dev, "failed to allocate l1 stream table desc\n"); + return -ENOMEM; + } + + size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3); + for (i = 0; i < cfg->num_l1_descs; ++i) { + struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[i]; + + desc->span = STRTAB_SPLIT + 1; + desc->l2ptr = dma_zalloc_coherent(smmu->dev, size, + &desc->l2ptr_dma, GFP_KERNEL); + if (!desc->l2ptr) { + dev_err(smmu->dev, + "failed to allocate l2 stream table %u\n", i); + ret = -ENOMEM; + goto out_free_l2; + } + + arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); + arm_smmu_write_strtab_l1_desc(strtab, desc); + strtab += STRTAB_STE_DWORDS; + } + + return 0; + +out_free_l2: + arm_smmu_free_l2_strtab(smmu); + return ret; +} + +static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) +{ + void *strtab; + u64 reg; + u32 size; + int ret = 0; + + strtab = dma_zalloc_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, + &smmu->strtab_cfg.strtab_dma, GFP_KERNEL); + if (!strtab) { + dev_err(smmu->dev, "failed to allocate l1 stream table\n"); + return -ENOMEM; + } + smmu->strtab_cfg.strtab = strtab; + + reg = smmu->strtab_cfg.strtab_dma & + STRTAB_BASE_ADDR_MASK << STRTAB_BASE_ADDR_SHIFT; + reg |= STRTAB_BASE_RA; + smmu->strtab_cfg.strtab_base = reg; + + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3); + smmu->strtab_cfg.num_l1_descs = 1 << size; + size += STRTAB_SPLIT; + reg = STRTAB_BASE_CFG_FMT_2LVL; + + ret = arm_smmu_alloc_l2_strtab(smmu); + if (ret) + goto out_free_l1; + } else { + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_STE_DWORDS) + 3); + smmu->strtab_cfg.num_l1_descs = 0; + reg = STRTAB_BASE_CFG_FMT_LINEAR; + arm_smmu_init_bypass_stes(strtab, 1 << size); + } + + if (size < smmu->sid_bits) + dev_warn(smmu->dev, "%s strtab only covers %u/%u bits of SID\n", + smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB ? + "2-level" : "linear", + size, smmu->sid_bits); + + reg |= (size & STRTAB_BASE_CFG_LOG2SIZE_MASK) + << STRTAB_BASE_CFG_LOG2SIZE_SHIFT; + reg |= (STRTAB_SPLIT & STRTAB_BASE_CFG_SPLIT_MASK) + << STRTAB_BASE_CFG_SPLIT_SHIFT; + smmu->strtab_cfg.strtab_base_cfg = reg; + + /* Allocate the first VMID for stage-2 bypass STEs */ + set_bit(0, smmu->vmid_map); + return 0; + +out_free_l1: + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, strtab, + smmu->strtab_cfg.strtab_dma); + return ret; +} + +static void arm_smmu_free_strtab(struct arm_smmu_device *smmu) +{ + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; + + arm_smmu_free_l2_strtab(smmu); + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, cfg->strtab, + cfg->strtab_dma); +} + +static int arm_smmu_init_structures(struct arm_smmu_device *smmu) +{ + int ret; + + ret = arm_smmu_init_queues(smmu); + if (ret) + return ret; + + ret = arm_smmu_init_strtab(smmu); + if (ret) + goto out_free_queues; + + return 0; + +out_free_queues: + arm_smmu_free_queues(smmu); + return ret; +} + +static void arm_smmu_free_structures(struct arm_smmu_device *smmu) +{ + arm_smmu_free_strtab(smmu); + arm_smmu_free_queues(smmu); +} + +static int arm_smmu_write_reg_sync(struct arm_smmu_device *smmu, u32 val, + unsigned int reg_off, unsigned int ack_off) +{ + u32 reg; + + writel_relaxed(val, smmu->base + reg_off); + return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val, + 1, ARM_SMMU_POLL_TIMEOUT_US); +} + +static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) +{ + int ret, irq; + + /* Disable IRQs first */ + ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL, + ARM_SMMU_IRQ_CTRLACK); + if (ret) { + dev_err(smmu->dev, "failed to disable irqs\n"); + return ret; + } + + /* Clear the MSI address regs */ + writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0); + writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); + + /* Request wired interrupt lines */ + irq = smmu->evtq.q.irq; + if (irq) { + ret = devm_request_threaded_irq(smmu->dev, irq, + arm_smmu_evtq_handler, + arm_smmu_evtq_thread, + 0, "arm-smmu-v3-evtq", smmu); + if (IS_ERR_VALUE(ret)) + dev_warn(smmu->dev, "failed to enable evtq irq\n"); + } + + irq = smmu->cmdq.q.irq; + if (irq) { + ret = devm_request_irq(smmu->dev, irq, + arm_smmu_cmdq_sync_handler, 0, + "arm-smmu-v3-cmdq-sync", smmu); + if (IS_ERR_VALUE(ret)) + dev_warn(smmu->dev, "failed to enable cmdq-sync irq\n"); + } + + irq = smmu->gerr_irq; + if (irq) { + ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler, + 0, "arm-smmu-v3-gerror", smmu); + if (IS_ERR_VALUE(ret)) + dev_warn(smmu->dev, "failed to enable gerror irq\n"); + } + + if (smmu->features & ARM_SMMU_FEAT_PRI) { + writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0); + + irq = smmu->priq.q.irq; + if (irq) { + ret = devm_request_threaded_irq(smmu->dev, irq, + arm_smmu_priq_handler, + arm_smmu_priq_thread, + 0, "arm-smmu-v3-priq", + smmu); + if (IS_ERR_VALUE(ret)) + dev_warn(smmu->dev, + "failed to enable priq irq\n"); + } + } + + /* Enable interrupt generation on the SMMU */ + ret = arm_smmu_write_reg_sync(smmu, + IRQ_CTRL_EVTQ_IRQEN | + IRQ_CTRL_GERROR_IRQEN, + ARM_SMMU_IRQ_CTRL, ARM_SMMU_IRQ_CTRLACK); + if (ret) + dev_warn(smmu->dev, "failed to enable irqs\n"); + + return 0; +} + +static int arm_smmu_device_disable(struct arm_smmu_device *smmu) +{ + int ret; + + ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_CR0, ARM_SMMU_CR0ACK); + if (ret) + dev_err(smmu->dev, "failed to clear cr0\n"); + + return ret; +} + +static int arm_smmu_device_reset(struct arm_smmu_device *smmu) +{ + int ret; + u32 reg, enables; + struct arm_smmu_cmdq_ent cmd; + + /* Clear CR0 and sync (disables SMMU and queue processing) */ + reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); + if (reg & CR0_SMMUEN) + dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); + + ret = arm_smmu_device_disable(smmu); + if (ret) + return ret; + + /* CR1 (table and queue memory attributes) */ + reg = (CR1_SH_ISH << CR1_TABLE_SH_SHIFT) | + (CR1_CACHE_WB << CR1_TABLE_OC_SHIFT) | + (CR1_CACHE_WB << CR1_TABLE_IC_SHIFT) | + (CR1_SH_ISH << CR1_QUEUE_SH_SHIFT) | + (CR1_CACHE_WB << CR1_QUEUE_OC_SHIFT) | + (CR1_CACHE_WB << CR1_QUEUE_IC_SHIFT); + writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); + + /* CR2 (random crap) */ + reg = CR2_PTM | CR2_RECINVMID | CR2_E2H; + writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); + + /* Stream table */ + writeq_relaxed(smmu->strtab_cfg.strtab_base, + smmu->base + ARM_SMMU_STRTAB_BASE); + writel_relaxed(smmu->strtab_cfg.strtab_base_cfg, + smmu->base + ARM_SMMU_STRTAB_BASE_CFG); + + /* Command queue */ + writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); + writel_relaxed(smmu->cmdq.q.prod, smmu->base + ARM_SMMU_CMDQ_PROD); + writel_relaxed(smmu->cmdq.q.cons, smmu->base + ARM_SMMU_CMDQ_CONS); + + enables = CR0_CMDQEN; + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to enable command queue\n"); + return ret; + } + + /* Invalidate any cached configuration */ + cmd.opcode = CMDQ_OP_CFGI_ALL; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + cmd.opcode = CMDQ_OP_CMD_SYNC; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + + /* Invalidate any stale TLB entries */ + cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + cmd.opcode = CMDQ_OP_TLBI_NSNH_ALL; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + cmd.opcode = CMDQ_OP_CMD_SYNC; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + + /* Event queue */ + writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); + writel_relaxed(smmu->evtq.q.prod, smmu->base + ARM_SMMU_EVTQ_PROD); + writel_relaxed(smmu->evtq.q.cons, smmu->base + ARM_SMMU_EVTQ_CONS); + + enables |= CR0_EVTQEN; + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to enable event queue\n"); + return ret; + } + + /* PRI queue */ + if (smmu->features & ARM_SMMU_FEAT_PRI) { + writeq_relaxed(smmu->priq.q.q_base, + smmu->base + ARM_SMMU_PRIQ_BASE); + writel_relaxed(smmu->priq.q.prod, + smmu->base + ARM_SMMU_PRIQ_PROD); + writel_relaxed(smmu->priq.q.cons, + smmu->base + ARM_SMMU_PRIQ_CONS); + + enables |= CR0_PRIQEN; + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to enable PRI queue\n"); + return ret; + } + } + + ret = arm_smmu_setup_irqs(smmu); + if (ret) { + dev_err(smmu->dev, "failed to setup irqs\n"); + return ret; + } + + /* Enable the SMMU interface */ + enables |= CR0_SMMUEN; + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to enable SMMU interface\n"); + return ret; + } + + return 0; +} + +static int arm_smmu_device_probe(struct arm_smmu_device *smmu) +{ + u32 reg; + bool coherent; + unsigned long pgsize_bitmap = 0; + + /* IDR0 */ + reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0); + + /* 2-level structures */ + if ((reg & IDR0_ST_LVL_MASK << IDR0_ST_LVL_SHIFT) == IDR0_ST_LVL_2LVL); + smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB; + + if (reg & IDR0_CD2L) + smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB; + + /* + * Translation table endianness. + * We currently require the same endianness as the CPU, but this + * could be changed later by adding a new IO_PGTABLE_QUIRK. + */ + switch (reg & IDR0_TTENDIAN_MASK << IDR0_TTENDIAN_SHIFT) { + case IDR0_TTENDIAN_MIXED: + smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE; + break; +#ifdef __BIG_ENDIAN + case IDR0_TTENDIAN_BE: + smmu->features |= ARM_SMMU_FEAT_TT_BE; + break; +#else + case IDR0_TTENDIAN_LE: + smmu->features |= ARM_SMMU_FEAT_TT_LE; + break; +#endif + default: + dev_err(smmu->dev, "unknown/unsupported TT endianness!\n"); + return -ENXIO; + } + + /* Boolean feature flags */ + if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI) + smmu->features |= ARM_SMMU_FEAT_PRI; + + if (IS_ENABLED(CONFIG_PCI_ATS) && reg & IDR0_ATS) + smmu->features |= ARM_SMMU_FEAT_ATS; + + if (reg & IDR0_SEV) + smmu->features |= ARM_SMMU_FEAT_SEV; + + if (reg & IDR0_MSI) + smmu->features |= ARM_SMMU_FEAT_MSI; + + /* + * The dma-coherent property is used in preference to the ID + * register, but warn on mismatch. + */ + coherent = of_dma_is_coherent(smmu->dev->of_node); + if (coherent) + smmu->features |= ARM_SMMU_FEAT_COHERENCY; + + if (!!(reg & IDR0_COHACC) != coherent) + dev_warn(smmu->dev, "IDR0.COHACC overridden by dma-coherent property (%s)\n", + coherent ? "true" : "false"); + + if (reg & IDR0_STALL_MODEL) + smmu->features |= ARM_SMMU_FEAT_STALLS; + + if (reg & IDR0_S1P) + smmu->features |= ARM_SMMU_FEAT_TRANS_S1; + + if (reg & IDR0_S2P) + smmu->features |= ARM_SMMU_FEAT_TRANS_S2; + + if (!(reg & (IDR0_S1P | IDR0_S2P))) { + dev_err(smmu->dev, "no translation support!\n"); + return -ENXIO; + } + + /* We only support the AArch64 table format at present */ + if ((reg & IDR0_TTF_MASK << IDR0_TTF_SHIFT) < IDR0_TTF_AARCH64) { + dev_err(smmu->dev, "AArch64 table format not supported!\n"); + return -ENXIO; + } + + /* ASID/VMID sizes */ + smmu->asid_bits = reg & IDR0_ASID16 ? 16 : 8; + smmu->vmid_bits = reg & IDR0_VMID16 ? 16 : 8; + + /* IDR1 */ + reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1); + if (reg & (IDR1_TABLES_PRESET | IDR1_QUEUES_PRESET | IDR1_REL)) { + dev_err(smmu->dev, "embedded implementation not supported\n"); + return -ENXIO; + } + + /* Queue sizes, capped at 4k */ + smmu->cmdq.q.max_n_shift = min((u32)CMDQ_MAX_SZ_SHIFT, + reg >> IDR1_CMDQ_SHIFT & IDR1_CMDQ_MASK); + if (!smmu->cmdq.q.max_n_shift) { + /* Odd alignment restrictions on the base, so ignore for now */ + dev_err(smmu->dev, "unit-length command queue not supported\n"); + return -ENXIO; + } + + smmu->evtq.q.max_n_shift = min((u32)EVTQ_MAX_SZ_SHIFT, + reg >> IDR1_EVTQ_SHIFT & IDR1_EVTQ_MASK); + smmu->priq.q.max_n_shift = min((u32)PRIQ_MAX_SZ_SHIFT, + reg >> IDR1_PRIQ_SHIFT & IDR1_PRIQ_MASK); + + /* SID/SSID sizes */ + smmu->ssid_bits = reg >> IDR1_SSID_SHIFT & IDR1_SSID_MASK; + smmu->sid_bits = reg >> IDR1_SID_SHIFT & IDR1_SID_MASK; + + /* IDR5 */ + reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); + + /* Maximum number of outstanding stalls */ + smmu->evtq.max_stalls = reg >> IDR5_STALL_MAX_SHIFT + & IDR5_STALL_MAX_MASK; + + /* Page sizes */ + if (reg & IDR5_GRAN64K) + pgsize_bitmap |= SZ_64K | SZ_512M; + if (reg & IDR5_GRAN16K) + pgsize_bitmap |= SZ_16K | SZ_32M; + if (reg & IDR5_GRAN4K) + pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; + + arm_smmu_ops.pgsize_bitmap &= pgsize_bitmap; + + /* Output address size */ + switch (reg & IDR5_OAS_MASK << IDR5_OAS_SHIFT) { + case IDR5_OAS_32_BIT: + smmu->oas = 32; + break; + case IDR5_OAS_36_BIT: + smmu->oas = 36; + break; + case IDR5_OAS_40_BIT: + smmu->oas = 40; + break; + case IDR5_OAS_42_BIT: + smmu->oas = 42; + break; + case IDR5_OAS_44_BIT: + smmu->oas = 44; + break; + case IDR5_OAS_48_BIT: + smmu->oas = 48; + break; + default: + dev_err(smmu->dev, "unknown output address size!\n"); + return -ENXIO; + } + + /* Set the DMA mask for our table walker */ + if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(smmu->oas))) + dev_warn(smmu->dev, + "failed to set DMA mask for table walker\n"); + + if (!smmu->ias) + smmu->ias = smmu->oas; + + dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n", + smmu->ias, smmu->oas, smmu->features); + return 0; +} + +static int arm_smmu_device_dt_probe(struct platform_device *pdev) +{ + int irq, ret; + struct resource *res; + struct arm_smmu_device *smmu; + struct device *dev = &pdev->dev; + + smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); + if (!smmu) { + dev_err(dev, "failed to allocate arm_smmu_device\n"); + return -ENOMEM; + } + smmu->dev = dev; + + /* Base address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (resource_size(res) + 1 < SZ_128K) { + dev_err(dev, "MMIO region too small (%pr)\n", res); + return -EINVAL; + } + + smmu->base = devm_ioremap_resource(dev, res); + if (IS_ERR(smmu->base)) + return PTR_ERR(smmu->base); + + /* Interrupt lines */ + irq = platform_get_irq_byname(pdev, "eventq"); + if (irq > 0) + smmu->evtq.q.irq = irq; + + irq = platform_get_irq_byname(pdev, "priq"); + if (irq > 0) + smmu->priq.q.irq = irq; + + irq = platform_get_irq_byname(pdev, "cmdq-sync"); + if (irq > 0) + smmu->cmdq.q.irq = irq; + + irq = platform_get_irq_byname(pdev, "gerror"); + if (irq > 0) + smmu->gerr_irq = irq; + + /* Probe the h/w */ + ret = arm_smmu_device_probe(smmu); + if (ret) + return ret; + + /* Initialise in-memory data structures */ + ret = arm_smmu_init_structures(smmu); + if (ret) + return ret; + + /* Reset the device */ + ret = arm_smmu_device_reset(smmu); + if (ret) + goto out_free_structures; + + /* Record our private device structure */ + INIT_LIST_HEAD(&smmu->list); + spin_lock(&arm_smmu_devices_lock); + list_add(&smmu->list, &arm_smmu_devices); + spin_unlock(&arm_smmu_devices_lock); + return 0; + +out_free_structures: + arm_smmu_free_structures(smmu); + return ret; +} + +static int arm_smmu_device_remove(struct platform_device *pdev) +{ + struct arm_smmu_device *curr, *smmu = NULL; + struct device *dev = &pdev->dev; + + spin_lock(&arm_smmu_devices_lock); + list_for_each_entry(curr, &arm_smmu_devices, list) { + if (curr->dev == dev) { + smmu = curr; + list_del(&smmu->list); + break; + } + } + spin_unlock(&arm_smmu_devices_lock); + + if (!smmu) + return -ENODEV; + + arm_smmu_device_disable(smmu); + arm_smmu_free_structures(smmu); + return 0; +} + +static struct of_device_id arm_smmu_of_match[] = { + { .compatible = "arm,smmu-v3", }, + { }, +}; +MODULE_DEVICE_TABLE(of, arm_smmu_of_match); + +static struct platform_driver arm_smmu_driver = { + .driver = { + .name = "arm-smmu-v3", + .of_match_table = of_match_ptr(arm_smmu_of_match), + }, + .probe = arm_smmu_device_dt_probe, + .remove = arm_smmu_device_remove, +}; + +static int __init arm_smmu_init(void) +{ + struct device_node *np; + int ret; + + np = of_find_matching_node(NULL, arm_smmu_of_match); + if (!np) + return 0; + + of_node_put(np); + + ret = platform_driver_register(&arm_smmu_driver); + if (ret) + return ret; + + return bus_set_iommu(&pci_bus_type, &arm_smmu_ops); +} + +static void __exit arm_smmu_exit(void) +{ + return platform_driver_unregister(&arm_smmu_driver); +} + +subsys_initcall(arm_smmu_init); +module_exit(arm_smmu_exit); + +MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations"); +MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); +MODULE_LICENSE("GPL v2"); -- 2.1.4 ^ permalink raw reply related [flat|nested] 40+ messages in thread
[parent not found: <1431108046-9675-3-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-05-08 18:00 ` Will Deacon @ 2015-05-12 7:40 ` leizhen -1 siblings, 0 replies; 40+ messages in thread From: leizhen @ 2015-05-12 7:40 UTC (permalink / raw) To: Will Deacon Cc: Huxinwei, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Sanil kumar, Gaojianbo, Dingtianhong, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r > + > +static int queue_poll_cons(struct arm_smmu_queue *q, u32 until, bool wfe) > +{ > + ktime_t timeout = ktime_add_us(ktime_get(), ARM_SMMU_POLL_TIMEOUT_US); > + > + while (queue_sync_cons(q), __queue_cons_before(q, until)) { > + if (ktime_compare(ktime_get(), timeout) > 0) Is it good to limit hardware behavior? May be wait for ever will be better. If SMMU can not consume queue items under normal condition, the SMMU hardware is broken, will lead software system to be crashed later. > + return -ETIMEDOUT; > + > + if (wfe) { > + wfe(); > + } else { > + cpu_relax(); > + udelay(1); > + } > + } > + > + return 0; > +} > + > +static void queue_write(__le64 *dst, u64 *src, size_t n_dwords) > +{ > + int i; > + > + for (i = 0; i < n_dwords; ++i) > + *dst++ = cpu_to_le64(*src++); > +} > + > +static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent) > +{ > + if (queue_full(q)) > + return -ENOSPC; > + > + queue_write(Q_ENT(q, q->prod), ent, q->ent_dwords); A dmb or dsb maybe needed. We must insure all data written are completed, then notify hardware to consume. > + queue_inc_prod(q); > + return 0; > +} > + > + > +/* High-level queue accessors */ > +static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) > +{ > + memset(cmd, 0, CMDQ_ENT_DWORDS << 3); > + cmd[0] |= (ent->opcode & CMDQ_0_OP_MASK) << CMDQ_0_OP_SHIFT; > + > + switch (ent->opcode) { > + case CMDQ_OP_TLBI_EL2_ALL: > + case CMDQ_OP_CMD_SYNC: > + cmd[0] |= CMDQ_SYNC_0_CS_SEV; We can not always set SIG_SEV, actually it should base upon SMMU_IDR0.SEV(smmu->features & ARM_SMMU_FEAT_SEV) > + break; > + default: > + return -ENOENT; > + } > + > + return 0; > +} > + > +static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, > + struct io_pgtable_cfg *pgtbl_cfg) > +{ > + int ret; > + u16 asid; > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; > + > + asid = arm_smmu_bitmap_alloc(smmu->asid_map, smmu->asid_bits); > + if (IS_ERR_VALUE(asid)) > + return asid; > + > + cfg->cdptr = dma_zalloc_coherent(smmu->dev, CTXDESC_CD_DWORDS << 3, > + &cfg->cdptr_dma, GFP_KERNEL); Why use dma_zalloc_coherent? iova is coverted from PA by calling phys_to_dma. I afraid PA and iova maybe not equal. In fact, the mapping between iova and PA is rely on SMMU driver itself. Why not use virt_to_phys to get PA, SMMU hardware actually require PA. > + if (!cfg->cdptr) { > + dev_warn(smmu->dev, "failed to allocate context descriptor\n"); > + goto out_free_asid; > + } > + > + cfg->cd.asid = asid; > + cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; > + cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr; > + cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; > + return 0; > + > +out_free_asid: > + arm_smmu_bitmap_free(smmu->asid_map, asid); > + return ret; > +} > + > + > +static int arm_smmu_add_device(struct device *dev) > +{ > + int i, ret; > + u32 sid, *sids; > + struct pci_dev *pdev; > + struct iommu_group *group; > + struct arm_smmu_group *smmu_group; > + > + /* We only support PCI, for now */ > + if (!dev_is_pci(dev)) > + return -ENODEV; > + > + pdev = to_pci_dev(dev); > + group = iommu_group_get_for_dev(dev); > + if (IS_ERR(group)) > + return PTR_ERR(group); > + > + smmu_group = iommu_group_get_iommudata(group); > + if (!smmu_group) { > + struct arm_smmu_device *smmu = arm_smmu_get_for_pci_dev(pdev); > + if (!smmu) { > + ret = -ENOENT; > + goto out_put_group; > + } > + > + smmu_group = kzalloc(sizeof(*smmu_group), GFP_KERNEL); > + if (!smmu_group) { > + ret = -ENOMEM; > + goto out_put_group; > + } > + > + smmu_group->ste.valid = true; > + smmu_group->smmu = smmu; > + iommu_group_set_iommudata(group, smmu_group, > + __arm_smmu_release_pci_iommudata); > + } > + > + /* Assume SID == RID until firmware tells us otherwise */ > + pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid); > + for (i = 0; i < smmu_group->num_sids; ++i) { > + /* If we already know about this SID, then we're done */ > + if (smmu_group->sids[i] == sid) > + return 0; > + } > + > + /* Check the SID is in range of the SMMU and our stream table */ > + if (!arm_smmu_sid_in_range(smmu_group->smmu, sid)) { > + ret = -ERANGE; > + goto out_put_group; > + } > + > + /* Resize the SID array for the group */ > + smmu_group->num_sids++; > + sids = krealloc(smmu_group->sids, smmu_group->num_sids * sizeof(*sids), > + GFP_KERNEL); > + if (!sids) { > + smmu_group->num_sids--; > + ret = -ENOMEM; > + goto out_put_group; > + } > + > + /* Add the new SID */ > + sids[smmu_group->num_sids - 1] = sid; > + smmu_group->sids = sids; > + return 0; > + > +out_put_group: > + iommu_group_put(group); > + return ret; > +} > +static int arm_smmu_alloc_l2_strtab(struct arm_smmu_device *smmu) > +{ > + int ret; > + unsigned int i; > + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; > + size_t size = sizeof(*cfg->l1_desc) * cfg->num_l1_descs; > + void *strtab = smmu->strtab_cfg.strtab; > + > + cfg->l1_desc = devm_kzalloc(smmu->dev, size, GFP_KERNEL); > + if (!cfg->l1_desc) { > + dev_err(smmu->dev, "failed to allocate l1 stream table desc\n"); > + return -ENOMEM; > + } > + > + size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3); > + for (i = 0; i < cfg->num_l1_descs; ++i) { > + struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[i]; > + > + desc->span = STRTAB_SPLIT + 1; > + desc->l2ptr = dma_zalloc_coherent(smmu->dev, size, > + &desc->l2ptr_dma, GFP_KERNEL); No, no, please don't allocate all Lv2 table memory, we should dynamic allocation when needed. Otherwise we can not save memory relative to one level table. And cfg->l1_desc seems not necessary. Before create mapping for a specified StreamID, we read corresponding Lv1 table entry, if L2Ptr is NULL, then we build Lv2 table. Otherwise, means this Lv2 table have already been built, because a Lv2 table is shared by a group of StreamIDs. > + if (!desc->l2ptr) { > + dev_err(smmu->dev, > + "failed to allocate l2 stream table %u\n", i); > + ret = -ENOMEM; > + goto out_free_l2; > + } > + > + arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); > + arm_smmu_write_strtab_l1_desc(strtab, desc); > + strtab += STRTAB_STE_DWORDS; > + } > + > + return 0; > + > +out_free_l2: > + arm_smmu_free_l2_strtab(smmu); > + return ret; > +} > + > +static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) > +{ > + void *strtab; > + u64 reg; > + u32 size; > + int ret = 0; > + > + strtab = dma_zalloc_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, > + &smmu->strtab_cfg.strtab_dma, GFP_KERNEL); As above, when Lv2 tables are dynamic allocation, we can create Lv1 table base on SMMU_IDR1.SIDSIZE and support non-pic devices. Oh, if SIDSIZE is too large, like 32. Maybe we should use 64K size Lv2 table. But we can only use PAGE_SIZE first, for lazy. > + if (!strtab) { > + dev_err(smmu->dev, "failed to allocate l1 stream table\n"); > + return -ENOMEM; > + } > + smmu->strtab_cfg.strtab = strtab; > + > + reg = smmu->strtab_cfg.strtab_dma & > + STRTAB_BASE_ADDR_MASK << STRTAB_BASE_ADDR_SHIFT; > + reg |= STRTAB_BASE_RA; > + smmu->strtab_cfg.strtab_base = reg; > + > + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { > + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3); > + smmu->strtab_cfg.num_l1_descs = 1 << size; > + size += STRTAB_SPLIT; > + reg = STRTAB_BASE_CFG_FMT_2LVL; > + > + ret = arm_smmu_alloc_l2_strtab(smmu); > + if (ret) > + goto out_free_l1; > + } else { > + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_STE_DWORDS) + 3); > + smmu->strtab_cfg.num_l1_descs = 0; > + reg = STRTAB_BASE_CFG_FMT_LINEAR; > + arm_smmu_init_bypass_stes(strtab, 1 << size); > + } > + > + if (size < smmu->sid_bits) > + dev_warn(smmu->dev, "%s strtab only covers %u/%u bits of SID\n", > + smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB ? > + "2-level" : "linear", > + size, smmu->sid_bits); > + > + reg |= (size & STRTAB_BASE_CFG_LOG2SIZE_MASK) > + << STRTAB_BASE_CFG_LOG2SIZE_SHIFT; > + reg |= (STRTAB_SPLIT & STRTAB_BASE_CFG_SPLIT_MASK) > + << STRTAB_BASE_CFG_SPLIT_SHIFT; > + smmu->strtab_cfg.strtab_base_cfg = reg; > + > + /* Allocate the first VMID for stage-2 bypass STEs */ > + set_bit(0, smmu->vmid_map); > + return 0; > + > +out_free_l1: > + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, strtab, > + smmu->strtab_cfg.strtab_dma); > + return ret; > +} > + > +static void arm_smmu_free_strtab(struct arm_smmu_device *smmu) > +{ > + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; > + > + arm_smmu_free_l2_strtab(smmu); > + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, cfg->strtab, > + cfg->strtab_dma); > +} > + > + > +static int arm_smmu_device_reset(struct arm_smmu_device *smmu) > +{ > + int ret; > + u32 reg, enables; > + struct arm_smmu_cmdq_ent cmd; > + > + /* Clear CR0 and sync (disables SMMU and queue processing) */ > + reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); > + if (reg & CR0_SMMUEN) > + dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); > + > + ret = arm_smmu_device_disable(smmu); > + if (ret) > + return ret; > + > + /* CR1 (table and queue memory attributes) */ > + reg = (CR1_SH_ISH << CR1_TABLE_SH_SHIFT) | > + (CR1_CACHE_WB << CR1_TABLE_OC_SHIFT) | > + (CR1_CACHE_WB << CR1_TABLE_IC_SHIFT) | > + (CR1_SH_ISH << CR1_QUEUE_SH_SHIFT) | > + (CR1_CACHE_WB << CR1_QUEUE_OC_SHIFT) | > + (CR1_CACHE_WB << CR1_QUEUE_IC_SHIFT); > + writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); > + > + /* CR2 (random crap) */ > + reg = CR2_PTM | CR2_RECINVMID | CR2_E2H; Do we need to explicitly set CR2_E2H? Linux only run at EL1. > + writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); > + > + /* Stream table */ > + writeq_relaxed(smmu->strtab_cfg.strtab_base, > + smmu->base + ARM_SMMU_STRTAB_BASE); > + writel_relaxed(smmu->strtab_cfg.strtab_base_cfg, > + smmu->base + ARM_SMMU_STRTAB_BASE_CFG); > + > + /* Command queue */ > + writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); > + writel_relaxed(smmu->cmdq.q.prod, smmu->base + ARM_SMMU_CMDQ_PROD); > + writel_relaxed(smmu->cmdq.q.cons, smmu->base + ARM_SMMU_CMDQ_CONS); > + > + enables = CR0_CMDQEN; > + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > + ARM_SMMU_CR0ACK); > + if (ret) { > + dev_err(smmu->dev, "failed to enable command queue\n"); > + return ret; > + } > + > + /* Invalidate any cached configuration */ > + cmd.opcode = CMDQ_OP_CFGI_ALL; > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > + cmd.opcode = CMDQ_OP_CMD_SYNC; > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > + > + /* Invalidate any stale TLB entries */ > + cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; Do we need to execute CMDQ_OP_TLBI_EL2_ALL? Linux only run at EL1. It at least rely on SMMU_IDR0.Hyp > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > + cmd.opcode = CMDQ_OP_TLBI_NSNH_ALL; > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > + cmd.opcode = CMDQ_OP_CMD_SYNC; > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > + > + /* Event queue */ > + writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); > + writel_relaxed(smmu->evtq.q.prod, smmu->base + ARM_SMMU_EVTQ_PROD); > + writel_relaxed(smmu->evtq.q.cons, smmu->base + ARM_SMMU_EVTQ_CONS); > + > + enables |= CR0_EVTQEN; > + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > + ARM_SMMU_CR0ACK); > + if (ret) { > + dev_err(smmu->dev, "failed to enable event queue\n"); > + return ret; > + } > + > + /* PRI queue */ > + if (smmu->features & ARM_SMMU_FEAT_PRI) { > + writeq_relaxed(smmu->priq.q.q_base, > + smmu->base + ARM_SMMU_PRIQ_BASE); > + writel_relaxed(smmu->priq.q.prod, > + smmu->base + ARM_SMMU_PRIQ_PROD); > + writel_relaxed(smmu->priq.q.cons, > + smmu->base + ARM_SMMU_PRIQ_CONS); > + > + enables |= CR0_PRIQEN; > + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > + ARM_SMMU_CR0ACK); > + if (ret) { > + dev_err(smmu->dev, "failed to enable PRI queue\n"); > + return ret; > + } > + } > + > + ret = arm_smmu_setup_irqs(smmu); > + if (ret) { > + dev_err(smmu->dev, "failed to setup irqs\n"); > + return ret; > + } > + > + /* Enable the SMMU interface */ > + enables |= CR0_SMMUEN; > + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > + ARM_SMMU_CR0ACK); > + if (ret) { > + dev_err(smmu->dev, "failed to enable SMMU interface\n"); > + return ret; > + } > + > + return 0; > +} > + ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-05-12 7:40 ` leizhen 0 siblings, 0 replies; 40+ messages in thread From: leizhen @ 2015-05-12 7:40 UTC (permalink / raw) To: linux-arm-kernel > + > +static int queue_poll_cons(struct arm_smmu_queue *q, u32 until, bool wfe) > +{ > + ktime_t timeout = ktime_add_us(ktime_get(), ARM_SMMU_POLL_TIMEOUT_US); > + > + while (queue_sync_cons(q), __queue_cons_before(q, until)) { > + if (ktime_compare(ktime_get(), timeout) > 0) Is it good to limit hardware behavior? May be wait for ever will be better. If SMMU can not consume queue items under normal condition, the SMMU hardware is broken, will lead software system to be crashed later. > + return -ETIMEDOUT; > + > + if (wfe) { > + wfe(); > + } else { > + cpu_relax(); > + udelay(1); > + } > + } > + > + return 0; > +} > + > +static void queue_write(__le64 *dst, u64 *src, size_t n_dwords) > +{ > + int i; > + > + for (i = 0; i < n_dwords; ++i) > + *dst++ = cpu_to_le64(*src++); > +} > + > +static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent) > +{ > + if (queue_full(q)) > + return -ENOSPC; > + > + queue_write(Q_ENT(q, q->prod), ent, q->ent_dwords); A dmb or dsb maybe needed. We must insure all data written are completed, then notify hardware to consume. > + queue_inc_prod(q); > + return 0; > +} > + > + > +/* High-level queue accessors */ > +static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) > +{ > + memset(cmd, 0, CMDQ_ENT_DWORDS << 3); > + cmd[0] |= (ent->opcode & CMDQ_0_OP_MASK) << CMDQ_0_OP_SHIFT; > + > + switch (ent->opcode) { > + case CMDQ_OP_TLBI_EL2_ALL: > + case CMDQ_OP_CMD_SYNC: > + cmd[0] |= CMDQ_SYNC_0_CS_SEV; We can not always set SIG_SEV, actually it should base upon SMMU_IDR0.SEV(smmu->features & ARM_SMMU_FEAT_SEV) > + break; > + default: > + return -ENOENT; > + } > + > + return 0; > +} > + > +static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, > + struct io_pgtable_cfg *pgtbl_cfg) > +{ > + int ret; > + u16 asid; > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; > + > + asid = arm_smmu_bitmap_alloc(smmu->asid_map, smmu->asid_bits); > + if (IS_ERR_VALUE(asid)) > + return asid; > + > + cfg->cdptr = dma_zalloc_coherent(smmu->dev, CTXDESC_CD_DWORDS << 3, > + &cfg->cdptr_dma, GFP_KERNEL); Why use dma_zalloc_coherent? iova is coverted from PA by calling phys_to_dma. I afraid PA and iova maybe not equal. In fact, the mapping between iova and PA is rely on SMMU driver itself. Why not use virt_to_phys to get PA, SMMU hardware actually require PA. > + if (!cfg->cdptr) { > + dev_warn(smmu->dev, "failed to allocate context descriptor\n"); > + goto out_free_asid; > + } > + > + cfg->cd.asid = asid; > + cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; > + cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr; > + cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; > + return 0; > + > +out_free_asid: > + arm_smmu_bitmap_free(smmu->asid_map, asid); > + return ret; > +} > + > + > +static int arm_smmu_add_device(struct device *dev) > +{ > + int i, ret; > + u32 sid, *sids; > + struct pci_dev *pdev; > + struct iommu_group *group; > + struct arm_smmu_group *smmu_group; > + > + /* We only support PCI, for now */ > + if (!dev_is_pci(dev)) > + return -ENODEV; > + > + pdev = to_pci_dev(dev); > + group = iommu_group_get_for_dev(dev); > + if (IS_ERR(group)) > + return PTR_ERR(group); > + > + smmu_group = iommu_group_get_iommudata(group); > + if (!smmu_group) { > + struct arm_smmu_device *smmu = arm_smmu_get_for_pci_dev(pdev); > + if (!smmu) { > + ret = -ENOENT; > + goto out_put_group; > + } > + > + smmu_group = kzalloc(sizeof(*smmu_group), GFP_KERNEL); > + if (!smmu_group) { > + ret = -ENOMEM; > + goto out_put_group; > + } > + > + smmu_group->ste.valid = true; > + smmu_group->smmu = smmu; > + iommu_group_set_iommudata(group, smmu_group, > + __arm_smmu_release_pci_iommudata); > + } > + > + /* Assume SID == RID until firmware tells us otherwise */ > + pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid); > + for (i = 0; i < smmu_group->num_sids; ++i) { > + /* If we already know about this SID, then we're done */ > + if (smmu_group->sids[i] == sid) > + return 0; > + } > + > + /* Check the SID is in range of the SMMU and our stream table */ > + if (!arm_smmu_sid_in_range(smmu_group->smmu, sid)) { > + ret = -ERANGE; > + goto out_put_group; > + } > + > + /* Resize the SID array for the group */ > + smmu_group->num_sids++; > + sids = krealloc(smmu_group->sids, smmu_group->num_sids * sizeof(*sids), > + GFP_KERNEL); > + if (!sids) { > + smmu_group->num_sids--; > + ret = -ENOMEM; > + goto out_put_group; > + } > + > + /* Add the new SID */ > + sids[smmu_group->num_sids - 1] = sid; > + smmu_group->sids = sids; > + return 0; > + > +out_put_group: > + iommu_group_put(group); > + return ret; > +} > +static int arm_smmu_alloc_l2_strtab(struct arm_smmu_device *smmu) > +{ > + int ret; > + unsigned int i; > + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; > + size_t size = sizeof(*cfg->l1_desc) * cfg->num_l1_descs; > + void *strtab = smmu->strtab_cfg.strtab; > + > + cfg->l1_desc = devm_kzalloc(smmu->dev, size, GFP_KERNEL); > + if (!cfg->l1_desc) { > + dev_err(smmu->dev, "failed to allocate l1 stream table desc\n"); > + return -ENOMEM; > + } > + > + size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3); > + for (i = 0; i < cfg->num_l1_descs; ++i) { > + struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[i]; > + > + desc->span = STRTAB_SPLIT + 1; > + desc->l2ptr = dma_zalloc_coherent(smmu->dev, size, > + &desc->l2ptr_dma, GFP_KERNEL); No, no, please don't allocate all Lv2 table memory, we should dynamic allocation when needed. Otherwise we can not save memory relative to one level table. And cfg->l1_desc seems not necessary. Before create mapping for a specified StreamID, we read corresponding Lv1 table entry, if L2Ptr is NULL, then we build Lv2 table. Otherwise, means this Lv2 table have already been built, because a Lv2 table is shared by a group of StreamIDs. > + if (!desc->l2ptr) { > + dev_err(smmu->dev, > + "failed to allocate l2 stream table %u\n", i); > + ret = -ENOMEM; > + goto out_free_l2; > + } > + > + arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); > + arm_smmu_write_strtab_l1_desc(strtab, desc); > + strtab += STRTAB_STE_DWORDS; > + } > + > + return 0; > + > +out_free_l2: > + arm_smmu_free_l2_strtab(smmu); > + return ret; > +} > + > +static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) > +{ > + void *strtab; > + u64 reg; > + u32 size; > + int ret = 0; > + > + strtab = dma_zalloc_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, > + &smmu->strtab_cfg.strtab_dma, GFP_KERNEL); As above, when Lv2 tables are dynamic allocation, we can create Lv1 table base on SMMU_IDR1.SIDSIZE and support non-pic devices. Oh, if SIDSIZE is too large, like 32. Maybe we should use 64K size Lv2 table. But we can only use PAGE_SIZE first, for lazy. > + if (!strtab) { > + dev_err(smmu->dev, "failed to allocate l1 stream table\n"); > + return -ENOMEM; > + } > + smmu->strtab_cfg.strtab = strtab; > + > + reg = smmu->strtab_cfg.strtab_dma & > + STRTAB_BASE_ADDR_MASK << STRTAB_BASE_ADDR_SHIFT; > + reg |= STRTAB_BASE_RA; > + smmu->strtab_cfg.strtab_base = reg; > + > + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { > + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3); > + smmu->strtab_cfg.num_l1_descs = 1 << size; > + size += STRTAB_SPLIT; > + reg = STRTAB_BASE_CFG_FMT_2LVL; > + > + ret = arm_smmu_alloc_l2_strtab(smmu); > + if (ret) > + goto out_free_l1; > + } else { > + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_STE_DWORDS) + 3); > + smmu->strtab_cfg.num_l1_descs = 0; > + reg = STRTAB_BASE_CFG_FMT_LINEAR; > + arm_smmu_init_bypass_stes(strtab, 1 << size); > + } > + > + if (size < smmu->sid_bits) > + dev_warn(smmu->dev, "%s strtab only covers %u/%u bits of SID\n", > + smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB ? > + "2-level" : "linear", > + size, smmu->sid_bits); > + > + reg |= (size & STRTAB_BASE_CFG_LOG2SIZE_MASK) > + << STRTAB_BASE_CFG_LOG2SIZE_SHIFT; > + reg |= (STRTAB_SPLIT & STRTAB_BASE_CFG_SPLIT_MASK) > + << STRTAB_BASE_CFG_SPLIT_SHIFT; > + smmu->strtab_cfg.strtab_base_cfg = reg; > + > + /* Allocate the first VMID for stage-2 bypass STEs */ > + set_bit(0, smmu->vmid_map); > + return 0; > + > +out_free_l1: > + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, strtab, > + smmu->strtab_cfg.strtab_dma); > + return ret; > +} > + > +static void arm_smmu_free_strtab(struct arm_smmu_device *smmu) > +{ > + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; > + > + arm_smmu_free_l2_strtab(smmu); > + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, cfg->strtab, > + cfg->strtab_dma); > +} > + > + > +static int arm_smmu_device_reset(struct arm_smmu_device *smmu) > +{ > + int ret; > + u32 reg, enables; > + struct arm_smmu_cmdq_ent cmd; > + > + /* Clear CR0 and sync (disables SMMU and queue processing) */ > + reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); > + if (reg & CR0_SMMUEN) > + dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); > + > + ret = arm_smmu_device_disable(smmu); > + if (ret) > + return ret; > + > + /* CR1 (table and queue memory attributes) */ > + reg = (CR1_SH_ISH << CR1_TABLE_SH_SHIFT) | > + (CR1_CACHE_WB << CR1_TABLE_OC_SHIFT) | > + (CR1_CACHE_WB << CR1_TABLE_IC_SHIFT) | > + (CR1_SH_ISH << CR1_QUEUE_SH_SHIFT) | > + (CR1_CACHE_WB << CR1_QUEUE_OC_SHIFT) | > + (CR1_CACHE_WB << CR1_QUEUE_IC_SHIFT); > + writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); > + > + /* CR2 (random crap) */ > + reg = CR2_PTM | CR2_RECINVMID | CR2_E2H; Do we need to explicitly set CR2_E2H? Linux only run at EL1. > + writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); > + > + /* Stream table */ > + writeq_relaxed(smmu->strtab_cfg.strtab_base, > + smmu->base + ARM_SMMU_STRTAB_BASE); > + writel_relaxed(smmu->strtab_cfg.strtab_base_cfg, > + smmu->base + ARM_SMMU_STRTAB_BASE_CFG); > + > + /* Command queue */ > + writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); > + writel_relaxed(smmu->cmdq.q.prod, smmu->base + ARM_SMMU_CMDQ_PROD); > + writel_relaxed(smmu->cmdq.q.cons, smmu->base + ARM_SMMU_CMDQ_CONS); > + > + enables = CR0_CMDQEN; > + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > + ARM_SMMU_CR0ACK); > + if (ret) { > + dev_err(smmu->dev, "failed to enable command queue\n"); > + return ret; > + } > + > + /* Invalidate any cached configuration */ > + cmd.opcode = CMDQ_OP_CFGI_ALL; > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > + cmd.opcode = CMDQ_OP_CMD_SYNC; > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > + > + /* Invalidate any stale TLB entries */ > + cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; Do we need to execute CMDQ_OP_TLBI_EL2_ALL? Linux only run at EL1. It at least rely on SMMU_IDR0.Hyp > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > + cmd.opcode = CMDQ_OP_TLBI_NSNH_ALL; > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > + cmd.opcode = CMDQ_OP_CMD_SYNC; > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > + > + /* Event queue */ > + writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); > + writel_relaxed(smmu->evtq.q.prod, smmu->base + ARM_SMMU_EVTQ_PROD); > + writel_relaxed(smmu->evtq.q.cons, smmu->base + ARM_SMMU_EVTQ_CONS); > + > + enables |= CR0_EVTQEN; > + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > + ARM_SMMU_CR0ACK); > + if (ret) { > + dev_err(smmu->dev, "failed to enable event queue\n"); > + return ret; > + } > + > + /* PRI queue */ > + if (smmu->features & ARM_SMMU_FEAT_PRI) { > + writeq_relaxed(smmu->priq.q.q_base, > + smmu->base + ARM_SMMU_PRIQ_BASE); > + writel_relaxed(smmu->priq.q.prod, > + smmu->base + ARM_SMMU_PRIQ_PROD); > + writel_relaxed(smmu->priq.q.cons, > + smmu->base + ARM_SMMU_PRIQ_CONS); > + > + enables |= CR0_PRIQEN; > + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > + ARM_SMMU_CR0ACK); > + if (ret) { > + dev_err(smmu->dev, "failed to enable PRI queue\n"); > + return ret; > + } > + } > + > + ret = arm_smmu_setup_irqs(smmu); > + if (ret) { > + dev_err(smmu->dev, "failed to setup irqs\n"); > + return ret; > + } > + > + /* Enable the SMMU interface */ > + enables |= CR0_SMMUEN; > + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > + ARM_SMMU_CR0ACK); > + if (ret) { > + dev_err(smmu->dev, "failed to enable SMMU interface\n"); > + return ret; > + } > + > + return 0; > +} > + ^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <5551AE56.6050906-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-05-12 7:40 ` leizhen @ 2015-05-12 16:55 ` Will Deacon -1 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-12 16:55 UTC (permalink / raw) To: leizhen Cc: huxinwei-hv44wF8Li93QT0dZR+AlfA, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Sanil kumar, Gaojianbo, Dingtianhong, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hi Leizhen, Thanks for the review! On Tue, May 12, 2015 at 08:40:06AM +0100, leizhen wrote: > > > + > > +static int queue_poll_cons(struct arm_smmu_queue *q, u32 until, bool wfe) > > +{ > > + ktime_t timeout = ktime_add_us(ktime_get(), ARM_SMMU_POLL_TIMEOUT_US); > > + > > + while (queue_sync_cons(q), __queue_cons_before(q, until)) { > > + if (ktime_compare(ktime_get(), timeout) > 0) > > Is it good to limit hardware behavior? May be wait for ever will be > better. If SMMU can not consume queue items under normal condition, the > SMMU hardware is broken, will lead software system to be crashed later. I disagree. Having a broken SMMU lock-up the entire kernel is considerably worse than having e.g. a DMA master get stuck. If this timeout expires, then we'll print a message and continue without waiting any longer for a CMD_SYNC completion (see arm_smmu_cmdq_issue_cmd). > > + return -ETIMEDOUT; > > + > > + if (wfe) { > > + wfe(); > > + } else { > > + cpu_relax(); > > + udelay(1); > > + } > > + } > > + > > + return 0; > > +} > > + > > +static void queue_write(__le64 *dst, u64 *src, size_t n_dwords) > > +{ > > + int i; > > + > > + for (i = 0; i < n_dwords; ++i) > > + *dst++ = cpu_to_le64(*src++); > > +} > > + > > +static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent) > > +{ > > + if (queue_full(q)) > > + return -ENOSPC; > > + > > + queue_write(Q_ENT(q, q->prod), ent, q->ent_dwords); > > A dmb or dsb maybe needed. We must insure all data written are completed, > then notify hardware to consume. The dsb is performed when we update the producer pointer in queue_inc_prod (since we use writel as opposed to writel_relaxed). > > + queue_inc_prod(q); > > + return 0; > > +} > > + > > + > > +/* High-level queue accessors */ > > +static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) > > +{ > > + memset(cmd, 0, CMDQ_ENT_DWORDS << 3); > > + cmd[0] |= (ent->opcode & CMDQ_0_OP_MASK) << CMDQ_0_OP_SHIFT; > > + > > + switch (ent->opcode) { > > + case CMDQ_OP_TLBI_EL2_ALL: > > > + case CMDQ_OP_CMD_SYNC: > > + cmd[0] |= CMDQ_SYNC_0_CS_SEV; > > We can not always set SIG_SEV, actually it should base upon > SMMU_IDR0.SEV(smmu->features & ARM_SMMU_FEAT_SEV) It doesn't matter for the CMD_SYNC command (which treats SIG_SEV as SIG_NONE in this case). What actually matters is that we don't perform wfe() when the SMMU can't issue the event, but that's already taken care of in arm_smmu_cmdq_issue_cmd. > > + break; > > + default: > > + return -ENOENT; > > + } > > + > > + return 0; > > +} > > > + > > +static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, > > + struct io_pgtable_cfg *pgtbl_cfg) > > +{ > > + int ret; > > + u16 asid; > > + struct arm_smmu_device *smmu = smmu_domain->smmu; > > + struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; > > + > > + asid = arm_smmu_bitmap_alloc(smmu->asid_map, smmu->asid_bits); > > + if (IS_ERR_VALUE(asid)) > > + return asid; > > + > > + cfg->cdptr = dma_zalloc_coherent(smmu->dev, CTXDESC_CD_DWORDS << 3, > > + &cfg->cdptr_dma, GFP_KERNEL); > > Why use dma_zalloc_coherent? iova is coverted from PA by calling > phys_to_dma. I afraid PA and iova maybe not equal. In fact, the mapping > between iova and PA is rely on SMMU driver itself. Why not use > virt_to_phys to get PA, SMMU hardware actually require PA. The SMMU structure walker is not allowed to be chained into another SMMU, so the physical and DMA addresses are equal here. That said, the walker does not need to be cache coherent, so I need to use the coherent DMA allocator to get memory of the correct attributes. I also need the table to be naturally aligned. An alternative would be something like __get_free_pages with homebrew cache maintenance for non-coherent SMMUs, but I don't want to re-invent the DMA mapping code in the driver (we already have a similar mess with the page tables, which I'd like to sort out). > > +static int arm_smmu_alloc_l2_strtab(struct arm_smmu_device *smmu) > > +{ > > + int ret; > > + unsigned int i; > > + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; > > + size_t size = sizeof(*cfg->l1_desc) * cfg->num_l1_descs; > > + void *strtab = smmu->strtab_cfg.strtab; > > + > > + cfg->l1_desc = devm_kzalloc(smmu->dev, size, GFP_KERNEL); > > + if (!cfg->l1_desc) { > > + dev_err(smmu->dev, "failed to allocate l1 stream table desc\n"); > > + return -ENOMEM; > > + } > > + > > + size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3); > > + for (i = 0; i < cfg->num_l1_descs; ++i) { > > + struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[i]; > > + > > + desc->span = STRTAB_SPLIT + 1; > > + desc->l2ptr = dma_zalloc_coherent(smmu->dev, size, > > + &desc->l2ptr_dma, GFP_KERNEL); > > No, no, please don't allocate all Lv2 table memory, we should dynamic > allocation when needed. Otherwise we can not save memory relative to one > level table. And cfg->l1_desc seems not necessary. Before create mapping > for a specified StreamID, we read corresponding Lv1 table entry, if L2Ptr > is NULL, then we build Lv2 table. Otherwise, means this Lv2 table have > already been built, because a Lv2 table is shared by a group of StreamIDs. The purpose of the two level approach isn't to save memory; it's to remove the need for a single (large) contiguous block. Furthermore, we need all master devices in the system to come up in a state where their transactions bypass the SMMU (i.e. we don't require them to use the SMMU for translation). Achieving this necessitates a fully-populated stream-table before any DMA occurs. I suppose we could look into populating it based on the ->add_device callback, which currently does have some range checks (arm_smmu_sid_in_range). Is that what you had in mind? > > + if (!desc->l2ptr) { > > + dev_err(smmu->dev, > > + "failed to allocate l2 stream table %u\n", i); > > + ret = -ENOMEM; > > + goto out_free_l2; > > + } > > + > > + arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); > > + arm_smmu_write_strtab_l1_desc(strtab, desc); > > + strtab += STRTAB_STE_DWORDS; > > + } > > + > > + return 0; > > + > > +out_free_l2: > > + arm_smmu_free_l2_strtab(smmu); > > + return ret; > > +} > > + > > +static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) > > +{ > > + void *strtab; > > + u64 reg; > > + u32 size; > > + int ret = 0; > > + > > + strtab = dma_zalloc_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, > > + &smmu->strtab_cfg.strtab_dma, GFP_KERNEL); > > As above, when Lv2 tables are dynamic allocation, we can create Lv1 table > base on SMMU_IDR1.SIDSIZE and support non-pic devices. Oh, if SIDSIZE is > too large, like 32. Maybe we should use 64K size Lv2 table. But we can > only use PAGE_SIZE first, for lazy. Right now, the l2 tables are 4k and l1 table is 8k. That's (a) nice for allocation on a system with 4k pages and (b) enough to cover a PCI host controller. The problem with supporting 32-bit SIDs is that the l1 will become a sizeable contiguous chunk which we'll have to allocate regardless. So, if we keep the l2 size at 4k for the moment, how big would you like the l1? For a 32-bit numberspace, it would be 4MB, which I don't think is practical. > > + if (!strtab) { > > + dev_err(smmu->dev, "failed to allocate l1 stream table\n"); > > + return -ENOMEM; > > + } > > + smmu->strtab_cfg.strtab = strtab; > > + > > + reg = smmu->strtab_cfg.strtab_dma & > > + STRTAB_BASE_ADDR_MASK << STRTAB_BASE_ADDR_SHIFT; > > + reg |= STRTAB_BASE_RA; > > + smmu->strtab_cfg.strtab_base = reg; > > + > > + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { > > + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3); > > + smmu->strtab_cfg.num_l1_descs = 1 << size; > > + size += STRTAB_SPLIT; > > + reg = STRTAB_BASE_CFG_FMT_2LVL; > > + > > + ret = arm_smmu_alloc_l2_strtab(smmu); > > + if (ret) > > + goto out_free_l1; > > + } else { > > + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_STE_DWORDS) + 3); > > + smmu->strtab_cfg.num_l1_descs = 0; > > + reg = STRTAB_BASE_CFG_FMT_LINEAR; > > + arm_smmu_init_bypass_stes(strtab, 1 << size); > > + } > > + > > + if (size < smmu->sid_bits) > > + dev_warn(smmu->dev, "%s strtab only covers %u/%u bits of SID\n", > > + smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB ? > > + "2-level" : "linear", > > + size, smmu->sid_bits); > > + > > + reg |= (size & STRTAB_BASE_CFG_LOG2SIZE_MASK) > > + << STRTAB_BASE_CFG_LOG2SIZE_SHIFT; > > + reg |= (STRTAB_SPLIT & STRTAB_BASE_CFG_SPLIT_MASK) > > + << STRTAB_BASE_CFG_SPLIT_SHIFT; > > + smmu->strtab_cfg.strtab_base_cfg = reg; > > + > > + /* Allocate the first VMID for stage-2 bypass STEs */ > > + set_bit(0, smmu->vmid_map); > > + return 0; > > + > > +out_free_l1: > > + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, strtab, > > + smmu->strtab_cfg.strtab_dma); > > + return ret; > > +} > > + > > +static void arm_smmu_free_strtab(struct arm_smmu_device *smmu) > > +{ > > + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; > > + > > + arm_smmu_free_l2_strtab(smmu); > > + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, cfg->strtab, > > + cfg->strtab_dma); > > +} > > + > > > + > > +static int arm_smmu_device_reset(struct arm_smmu_device *smmu) > > +{ > > + int ret; > > + u32 reg, enables; > > + struct arm_smmu_cmdq_ent cmd; > > + > > + /* Clear CR0 and sync (disables SMMU and queue processing) */ > > + reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); > > + if (reg & CR0_SMMUEN) > > + dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); > > + > > + ret = arm_smmu_device_disable(smmu); > > + if (ret) > > + return ret; > > + > > + /* CR1 (table and queue memory attributes) */ > > + reg = (CR1_SH_ISH << CR1_TABLE_SH_SHIFT) | > > + (CR1_CACHE_WB << CR1_TABLE_OC_SHIFT) | > > + (CR1_CACHE_WB << CR1_TABLE_IC_SHIFT) | > > + (CR1_SH_ISH << CR1_QUEUE_SH_SHIFT) | > > + (CR1_CACHE_WB << CR1_QUEUE_OC_SHIFT) | > > + (CR1_CACHE_WB << CR1_QUEUE_IC_SHIFT); > > + writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); > > + > > + /* CR2 (random crap) */ > > + reg = CR2_PTM | CR2_RECINVMID | CR2_E2H; > > Do we need to explicitly set CR2_E2H? Linux only run at EL1. Setting E2H won't cause any harm and I'd expect Linux to run there in the future. If we ever decide to share CPU page tables with the SMMU, then we'll need this set to participate in DVM. > > + writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); > > + > > + /* Stream table */ > > + writeq_relaxed(smmu->strtab_cfg.strtab_base, > > + smmu->base + ARM_SMMU_STRTAB_BASE); > > + writel_relaxed(smmu->strtab_cfg.strtab_base_cfg, > > + smmu->base + ARM_SMMU_STRTAB_BASE_CFG); > > + > > + /* Command queue */ > > + writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); > > + writel_relaxed(smmu->cmdq.q.prod, smmu->base + ARM_SMMU_CMDQ_PROD); > > + writel_relaxed(smmu->cmdq.q.cons, smmu->base + ARM_SMMU_CMDQ_CONS); > > + > > + enables = CR0_CMDQEN; > > + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > > + ARM_SMMU_CR0ACK); > > + if (ret) { > > + dev_err(smmu->dev, "failed to enable command queue\n"); > > + return ret; > > + } > > + > > + /* Invalidate any cached configuration */ > > + cmd.opcode = CMDQ_OP_CFGI_ALL; > > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > > + cmd.opcode = CMDQ_OP_CMD_SYNC; > > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > > + > > + /* Invalidate any stale TLB entries */ > > + cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; > > Do we need to execute CMDQ_OP_TLBI_EL2_ALL? Linux only run at EL1. It at > least rely on SMMU_IDR0.Hyp The SMMU isn't guaranteed to come up clean out of reset, so it's a good idea to perform this invalidation in case of junk in the TLB. Given that Linux owns the stage-2 translation, then this is the right place to do it. Will ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-05-12 16:55 ` Will Deacon 0 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-12 16:55 UTC (permalink / raw) To: linux-arm-kernel Hi Leizhen, Thanks for the review! On Tue, May 12, 2015 at 08:40:06AM +0100, leizhen wrote: > > > + > > +static int queue_poll_cons(struct arm_smmu_queue *q, u32 until, bool wfe) > > +{ > > + ktime_t timeout = ktime_add_us(ktime_get(), ARM_SMMU_POLL_TIMEOUT_US); > > + > > + while (queue_sync_cons(q), __queue_cons_before(q, until)) { > > + if (ktime_compare(ktime_get(), timeout) > 0) > > Is it good to limit hardware behavior? May be wait for ever will be > better. If SMMU can not consume queue items under normal condition, the > SMMU hardware is broken, will lead software system to be crashed later. I disagree. Having a broken SMMU lock-up the entire kernel is considerably worse than having e.g. a DMA master get stuck. If this timeout expires, then we'll print a message and continue without waiting any longer for a CMD_SYNC completion (see arm_smmu_cmdq_issue_cmd). > > + return -ETIMEDOUT; > > + > > + if (wfe) { > > + wfe(); > > + } else { > > + cpu_relax(); > > + udelay(1); > > + } > > + } > > + > > + return 0; > > +} > > + > > +static void queue_write(__le64 *dst, u64 *src, size_t n_dwords) > > +{ > > + int i; > > + > > + for (i = 0; i < n_dwords; ++i) > > + *dst++ = cpu_to_le64(*src++); > > +} > > + > > +static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent) > > +{ > > + if (queue_full(q)) > > + return -ENOSPC; > > + > > + queue_write(Q_ENT(q, q->prod), ent, q->ent_dwords); > > A dmb or dsb maybe needed. We must insure all data written are completed, > then notify hardware to consume. The dsb is performed when we update the producer pointer in queue_inc_prod (since we use writel as opposed to writel_relaxed). > > + queue_inc_prod(q); > > + return 0; > > +} > > + > > + > > +/* High-level queue accessors */ > > +static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) > > +{ > > + memset(cmd, 0, CMDQ_ENT_DWORDS << 3); > > + cmd[0] |= (ent->opcode & CMDQ_0_OP_MASK) << CMDQ_0_OP_SHIFT; > > + > > + switch (ent->opcode) { > > + case CMDQ_OP_TLBI_EL2_ALL: > > > + case CMDQ_OP_CMD_SYNC: > > + cmd[0] |= CMDQ_SYNC_0_CS_SEV; > > We can not always set SIG_SEV, actually it should base upon > SMMU_IDR0.SEV(smmu->features & ARM_SMMU_FEAT_SEV) It doesn't matter for the CMD_SYNC command (which treats SIG_SEV as SIG_NONE in this case). What actually matters is that we don't perform wfe() when the SMMU can't issue the event, but that's already taken care of in arm_smmu_cmdq_issue_cmd. > > + break; > > + default: > > + return -ENOENT; > > + } > > + > > + return 0; > > +} > > > + > > +static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, > > + struct io_pgtable_cfg *pgtbl_cfg) > > +{ > > + int ret; > > + u16 asid; > > + struct arm_smmu_device *smmu = smmu_domain->smmu; > > + struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; > > + > > + asid = arm_smmu_bitmap_alloc(smmu->asid_map, smmu->asid_bits); > > + if (IS_ERR_VALUE(asid)) > > + return asid; > > + > > + cfg->cdptr = dma_zalloc_coherent(smmu->dev, CTXDESC_CD_DWORDS << 3, > > + &cfg->cdptr_dma, GFP_KERNEL); > > Why use dma_zalloc_coherent? iova is coverted from PA by calling > phys_to_dma. I afraid PA and iova maybe not equal. In fact, the mapping > between iova and PA is rely on SMMU driver itself. Why not use > virt_to_phys to get PA, SMMU hardware actually require PA. The SMMU structure walker is not allowed to be chained into another SMMU, so the physical and DMA addresses are equal here. That said, the walker does not need to be cache coherent, so I need to use the coherent DMA allocator to get memory of the correct attributes. I also need the table to be naturally aligned. An alternative would be something like __get_free_pages with homebrew cache maintenance for non-coherent SMMUs, but I don't want to re-invent the DMA mapping code in the driver (we already have a similar mess with the page tables, which I'd like to sort out). > > +static int arm_smmu_alloc_l2_strtab(struct arm_smmu_device *smmu) > > +{ > > + int ret; > > + unsigned int i; > > + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; > > + size_t size = sizeof(*cfg->l1_desc) * cfg->num_l1_descs; > > + void *strtab = smmu->strtab_cfg.strtab; > > + > > + cfg->l1_desc = devm_kzalloc(smmu->dev, size, GFP_KERNEL); > > + if (!cfg->l1_desc) { > > + dev_err(smmu->dev, "failed to allocate l1 stream table desc\n"); > > + return -ENOMEM; > > + } > > + > > + size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3); > > + for (i = 0; i < cfg->num_l1_descs; ++i) { > > + struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[i]; > > + > > + desc->span = STRTAB_SPLIT + 1; > > + desc->l2ptr = dma_zalloc_coherent(smmu->dev, size, > > + &desc->l2ptr_dma, GFP_KERNEL); > > No, no, please don't allocate all Lv2 table memory, we should dynamic > allocation when needed. Otherwise we can not save memory relative to one > level table. And cfg->l1_desc seems not necessary. Before create mapping > for a specified StreamID, we read corresponding Lv1 table entry, if L2Ptr > is NULL, then we build Lv2 table. Otherwise, means this Lv2 table have > already been built, because a Lv2 table is shared by a group of StreamIDs. The purpose of the two level approach isn't to save memory; it's to remove the need for a single (large) contiguous block. Furthermore, we need all master devices in the system to come up in a state where their transactions bypass the SMMU (i.e. we don't require them to use the SMMU for translation). Achieving this necessitates a fully-populated stream-table before any DMA occurs. I suppose we could look into populating it based on the ->add_device callback, which currently does have some range checks (arm_smmu_sid_in_range). Is that what you had in mind? > > + if (!desc->l2ptr) { > > + dev_err(smmu->dev, > > + "failed to allocate l2 stream table %u\n", i); > > + ret = -ENOMEM; > > + goto out_free_l2; > > + } > > + > > + arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); > > + arm_smmu_write_strtab_l1_desc(strtab, desc); > > + strtab += STRTAB_STE_DWORDS; > > + } > > + > > + return 0; > > + > > +out_free_l2: > > + arm_smmu_free_l2_strtab(smmu); > > + return ret; > > +} > > + > > +static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) > > +{ > > + void *strtab; > > + u64 reg; > > + u32 size; > > + int ret = 0; > > + > > + strtab = dma_zalloc_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, > > + &smmu->strtab_cfg.strtab_dma, GFP_KERNEL); > > As above, when Lv2 tables are dynamic allocation, we can create Lv1 table > base on SMMU_IDR1.SIDSIZE and support non-pic devices. Oh, if SIDSIZE is > too large, like 32. Maybe we should use 64K size Lv2 table. But we can > only use PAGE_SIZE first, for lazy. Right now, the l2 tables are 4k and l1 table is 8k. That's (a) nice for allocation on a system with 4k pages and (b) enough to cover a PCI host controller. The problem with supporting 32-bit SIDs is that the l1 will become a sizeable contiguous chunk which we'll have to allocate regardless. So, if we keep the l2 size at 4k for the moment, how big would you like the l1? For a 32-bit numberspace, it would be 4MB, which I don't think is practical. > > + if (!strtab) { > > + dev_err(smmu->dev, "failed to allocate l1 stream table\n"); > > + return -ENOMEM; > > + } > > + smmu->strtab_cfg.strtab = strtab; > > + > > + reg = smmu->strtab_cfg.strtab_dma & > > + STRTAB_BASE_ADDR_MASK << STRTAB_BASE_ADDR_SHIFT; > > + reg |= STRTAB_BASE_RA; > > + smmu->strtab_cfg.strtab_base = reg; > > + > > + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { > > + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3); > > + smmu->strtab_cfg.num_l1_descs = 1 << size; > > + size += STRTAB_SPLIT; > > + reg = STRTAB_BASE_CFG_FMT_2LVL; > > + > > + ret = arm_smmu_alloc_l2_strtab(smmu); > > + if (ret) > > + goto out_free_l1; > > + } else { > > + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_STE_DWORDS) + 3); > > + smmu->strtab_cfg.num_l1_descs = 0; > > + reg = STRTAB_BASE_CFG_FMT_LINEAR; > > + arm_smmu_init_bypass_stes(strtab, 1 << size); > > + } > > + > > + if (size < smmu->sid_bits) > > + dev_warn(smmu->dev, "%s strtab only covers %u/%u bits of SID\n", > > + smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB ? > > + "2-level" : "linear", > > + size, smmu->sid_bits); > > + > > + reg |= (size & STRTAB_BASE_CFG_LOG2SIZE_MASK) > > + << STRTAB_BASE_CFG_LOG2SIZE_SHIFT; > > + reg |= (STRTAB_SPLIT & STRTAB_BASE_CFG_SPLIT_MASK) > > + << STRTAB_BASE_CFG_SPLIT_SHIFT; > > + smmu->strtab_cfg.strtab_base_cfg = reg; > > + > > + /* Allocate the first VMID for stage-2 bypass STEs */ > > + set_bit(0, smmu->vmid_map); > > + return 0; > > + > > +out_free_l1: > > + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, strtab, > > + smmu->strtab_cfg.strtab_dma); > > + return ret; > > +} > > + > > +static void arm_smmu_free_strtab(struct arm_smmu_device *smmu) > > +{ > > + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; > > + > > + arm_smmu_free_l2_strtab(smmu); > > + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, cfg->strtab, > > + cfg->strtab_dma); > > +} > > + > > > + > > +static int arm_smmu_device_reset(struct arm_smmu_device *smmu) > > +{ > > + int ret; > > + u32 reg, enables; > > + struct arm_smmu_cmdq_ent cmd; > > + > > + /* Clear CR0 and sync (disables SMMU and queue processing) */ > > + reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); > > + if (reg & CR0_SMMUEN) > > + dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); > > + > > + ret = arm_smmu_device_disable(smmu); > > + if (ret) > > + return ret; > > + > > + /* CR1 (table and queue memory attributes) */ > > + reg = (CR1_SH_ISH << CR1_TABLE_SH_SHIFT) | > > + (CR1_CACHE_WB << CR1_TABLE_OC_SHIFT) | > > + (CR1_CACHE_WB << CR1_TABLE_IC_SHIFT) | > > + (CR1_SH_ISH << CR1_QUEUE_SH_SHIFT) | > > + (CR1_CACHE_WB << CR1_QUEUE_OC_SHIFT) | > > + (CR1_CACHE_WB << CR1_QUEUE_IC_SHIFT); > > + writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); > > + > > + /* CR2 (random crap) */ > > + reg = CR2_PTM | CR2_RECINVMID | CR2_E2H; > > Do we need to explicitly set CR2_E2H? Linux only run at EL1. Setting E2H won't cause any harm and I'd expect Linux to run there in the future. If we ever decide to share CPU page tables with the SMMU, then we'll need this set to participate in DVM. > > + writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); > > + > > + /* Stream table */ > > + writeq_relaxed(smmu->strtab_cfg.strtab_base, > > + smmu->base + ARM_SMMU_STRTAB_BASE); > > + writel_relaxed(smmu->strtab_cfg.strtab_base_cfg, > > + smmu->base + ARM_SMMU_STRTAB_BASE_CFG); > > + > > + /* Command queue */ > > + writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); > > + writel_relaxed(smmu->cmdq.q.prod, smmu->base + ARM_SMMU_CMDQ_PROD); > > + writel_relaxed(smmu->cmdq.q.cons, smmu->base + ARM_SMMU_CMDQ_CONS); > > + > > + enables = CR0_CMDQEN; > > + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > > + ARM_SMMU_CR0ACK); > > + if (ret) { > > + dev_err(smmu->dev, "failed to enable command queue\n"); > > + return ret; > > + } > > + > > + /* Invalidate any cached configuration */ > > + cmd.opcode = CMDQ_OP_CFGI_ALL; > > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > > + cmd.opcode = CMDQ_OP_CMD_SYNC; > > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > > + > > + /* Invalidate any stale TLB entries */ > > + cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; > > Do we need to execute CMDQ_OP_TLBI_EL2_ALL? Linux only run at EL1. It at > least rely on SMMU_IDR0.Hyp The SMMU isn't guaranteed to come up clean out of reset, so it's a good idea to perform this invalidation in case of junk in the TLB. Given that Linux owns the stage-2 translation, then this is the right place to do it. Will ^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <20150512165500.GE2062-5wv7dgnIgG8@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-05-12 16:55 ` Will Deacon @ 2015-05-13 8:33 ` leizhen -1 siblings, 0 replies; 40+ messages in thread From: leizhen @ 2015-05-13 8:33 UTC (permalink / raw) To: Will Deacon Cc: huxinwei-hv44wF8Li93QT0dZR+AlfA, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Sanil kumar, Gaojianbo, Dingtianhong, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On 2015/5/13 0:55, Will Deacon wrote: > Hi Leizhen, > > Thanks for the review! > > On Tue, May 12, 2015 at 08:40:06AM +0100, leizhen wrote: >> >>> + >>> +static int queue_poll_cons(struct arm_smmu_queue *q, u32 until, bool wfe) >>> +{ >>> + ktime_t timeout = ktime_add_us(ktime_get(), ARM_SMMU_POLL_TIMEOUT_US); >>> + >>> + while (queue_sync_cons(q), __queue_cons_before(q, until)) { >>> + if (ktime_compare(ktime_get(), timeout) > 0) >> >> Is it good to limit hardware behavior? May be wait for ever will be >> better. If SMMU can not consume queue items under normal condition, the >> SMMU hardware is broken, will lead software system to be crashed later. > > I disagree. Having a broken SMMU lock-up the entire kernel is considerably > worse than having e.g. a DMA master get stuck. If this timeout expires, > then we'll print a message and continue without waiting any longer for > a CMD_SYNC completion (see arm_smmu_cmdq_issue_cmd). OK > >>> + return -ETIMEDOUT; >>> + >>> + if (wfe) { >>> + wfe(); >>> + } else { >>> + cpu_relax(); >>> + udelay(1); >>> + } >>> + } >>> + >>> + return 0; >>> +} >>> + >>> +static void queue_write(__le64 *dst, u64 *src, size_t n_dwords) >>> +{ >>> + int i; >>> + >>> + for (i = 0; i < n_dwords; ++i) >>> + *dst++ = cpu_to_le64(*src++); >>> +} >>> + >>> +static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent) >>> +{ >>> + if (queue_full(q)) >>> + return -ENOSPC; >>> + >>> + queue_write(Q_ENT(q, q->prod), ent, q->ent_dwords); >> >> A dmb or dsb maybe needed. We must insure all data written are completed, >> then notify hardware to consume. > > The dsb is performed when we update the producer pointer in queue_inc_prod > (since we use writel as opposed to writel_relaxed). OK, I saw. > >>> + queue_inc_prod(q); >>> + return 0; >>> +} >>> + >>> + >>> +/* High-level queue accessors */ >>> +static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) >>> +{ >>> + memset(cmd, 0, CMDQ_ENT_DWORDS << 3); >>> + cmd[0] |= (ent->opcode & CMDQ_0_OP_MASK) << CMDQ_0_OP_SHIFT; >>> + >>> + switch (ent->opcode) { >>> + case CMDQ_OP_TLBI_EL2_ALL: >> >>> + case CMDQ_OP_CMD_SYNC: >>> + cmd[0] |= CMDQ_SYNC_0_CS_SEV; >> >> We can not always set SIG_SEV, actually it should base upon >> SMMU_IDR0.SEV(smmu->features & ARM_SMMU_FEAT_SEV) > > It doesn't matter for the CMD_SYNC command (which treats SIG_SEV as > SIG_NONE in this case). What actually matters is that we don't perform > wfe() when the SMMU can't issue the event, but that's already taken care > of in arm_smmu_cmdq_issue_cmd. OK > >>> + break; >>> + default: >>> + return -ENOENT; >>> + } >>> + >>> + return 0; >>> +} >> >>> + >>> +static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, >>> + struct io_pgtable_cfg *pgtbl_cfg) >>> +{ >>> + int ret; >>> + u16 asid; >>> + struct arm_smmu_device *smmu = smmu_domain->smmu; >>> + struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; >>> + >>> + asid = arm_smmu_bitmap_alloc(smmu->asid_map, smmu->asid_bits); >>> + if (IS_ERR_VALUE(asid)) >>> + return asid; >>> + >>> + cfg->cdptr = dma_zalloc_coherent(smmu->dev, CTXDESC_CD_DWORDS << 3, >>> + &cfg->cdptr_dma, GFP_KERNEL); >> >> Why use dma_zalloc_coherent? iova is coverted from PA by calling >> phys_to_dma. I afraid PA and iova maybe not equal. In fact, the mapping >> between iova and PA is rely on SMMU driver itself. Why not use >> virt_to_phys to get PA, SMMU hardware actually require PA. > > The SMMU structure walker is not allowed to be chained into another SMMU, > so the physical and DMA addresses are equal here. That said, the walker > does not need to be cache coherent, so I need to use the coherent DMA > allocator to get memory of the correct attributes. I also need the table > to be naturally aligned. > > An alternative would be something like __get_free_pages with homebrew > cache maintenance for non-coherent SMMUs, but I don't want to re-invent > the DMA mapping code in the driver (we already have a similar mess with > the page tables, which I'd like to sort out). OK, I have not considered non-coherent SMMU before. But non-coherent SMMU maybe rare. > >>> +static int arm_smmu_alloc_l2_strtab(struct arm_smmu_device *smmu) >>> +{ >>> + int ret; >>> + unsigned int i; >>> + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; >>> + size_t size = sizeof(*cfg->l1_desc) * cfg->num_l1_descs; >>> + void *strtab = smmu->strtab_cfg.strtab; >>> + >>> + cfg->l1_desc = devm_kzalloc(smmu->dev, size, GFP_KERNEL); >>> + if (!cfg->l1_desc) { >>> + dev_err(smmu->dev, "failed to allocate l1 stream table desc\n"); >>> + return -ENOMEM; >>> + } >>> + >>> + size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3); >>> + for (i = 0; i < cfg->num_l1_descs; ++i) { >>> + struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[i]; >>> + >>> + desc->span = STRTAB_SPLIT + 1; >>> + desc->l2ptr = dma_zalloc_coherent(smmu->dev, size, >>> + &desc->l2ptr_dma, GFP_KERNEL); >> >> No, no, please don't allocate all Lv2 table memory, we should dynamic >> allocation when needed. Otherwise we can not save memory relative to one >> level table. And cfg->l1_desc seems not necessary. Before create mapping >> for a specified StreamID, we read corresponding Lv1 table entry, if L2Ptr >> is NULL, then we build Lv2 table. Otherwise, means this Lv2 table have >> already been built, because a Lv2 table is shared by a group of StreamIDs. > > The purpose of the two level approach isn't to save memory; it's to remove > the need for a single (large) contiguous block. Furthermore, we need all > master devices in the system to come up in a state where their transactions > bypass the SMMU (i.e. we don't require them to use the SMMU for > translation). Achieving this necessitates a fully-populated stream-table > before any DMA occurs. OK, but for non-pci devices(maybe pci devices also), initialize all devices(StreamIDs) to bypass mode maybe incorrect. Some devices maybe capable bring attributes by itself, and access different memory with different attributes(device attribute or cacheable attribute); some devices maybe not capable bring attributes by itself, but need access memory with cacheable attribute only, so we should set STE.MTCFG = 1. Provide dts configuration will be better. Oh, I can do it after your patches upstreamed, because this problem maybe only I met. Furthermore, I don't agree initialize all devices to bypass by default. Suppose a non-pci device's StreamID can be dynamic configured. We require StreamID-A, but the device actually issue StreamID-B because of software configuration fault. We really hope SMMU can report Bad StreamID fault. > > I suppose we could look into populating it based on the ->add_device > callback, which currently does have some range checks > (arm_smmu_sid_in_range). Is that what you had in mind? Yes, maybe attach_dev. But we should allocated the whole Lv1 table base on SMMU_IDR1.SIDSIZE > >>> + if (!desc->l2ptr) { >>> + dev_err(smmu->dev, >>> + "failed to allocate l2 stream table %u\n", i); >>> + ret = -ENOMEM; >>> + goto out_free_l2; >>> + } >>> + >>> + arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); >>> + arm_smmu_write_strtab_l1_desc(strtab, desc); >>> + strtab += STRTAB_STE_DWORDS; >>> + } >>> + >>> + return 0; >>> + >>> +out_free_l2: >>> + arm_smmu_free_l2_strtab(smmu); >>> + return ret; >>> +} >>> + >>> +static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) >>> +{ >>> + void *strtab; >>> + u64 reg; >>> + u32 size; >>> + int ret = 0; >>> + >>> + strtab = dma_zalloc_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, >>> + &smmu->strtab_cfg.strtab_dma, GFP_KERNEL); >> >> As above, when Lv2 tables are dynamic allocation, we can create Lv1 table >> base on SMMU_IDR1.SIDSIZE and support non-pic devices. Oh, if SIDSIZE is >> too large, like 32. Maybe we should use 64K size Lv2 table. But we can >> only use PAGE_SIZE first, for lazy. > > Right now, the l2 tables are 4k and l1 table is 8k. That's (a) nice for > allocation on a system with 4k pages and (b) enough to cover a PCI host > controller. The problem with supporting 32-bit SIDs is that the l1 will > become a sizeable contiguous chunk which we'll have to allocate > regardless. > > So, if we keep the l2 size at 4k for the moment, how big would you like > the l1? For a 32-bit numberspace, it would be 4MB, which I don't think is > practical. Yes, because I don't think SMMU_IDR1.SIDSIZE = 32 really exist, so I said use PAGE_SIZE first. But now, this patch only support SMMU_IDR1.SIDSIZE <= 16. Suppose SMMU_IDR1.SIDSIZE = 25，Lv2 table size at 4K, then Lv1 table need 2^(25 - 6 + 3) = 2^22 = 4M. If we pre-allocated all Lv2 table, we need 2^25 * 64 = 2^31 = 2G, that's too big. So we must only allocate Lv2 table when we needed. If SMMU_IDR1.SIDSIZE = 32 really exist(or too big), we need dynamic choose Lv2 table size(4K,16K,64K). Because Lv1 table maybe too big, and can not be allocated by current API, a dts configuration should be added, like lv1-table-base = <0x0 0x0>, and we use ioremap_cache get VA(maybe ioremap, for non-coherent SMMU). Oh, I can do it after your patches upstreamed, because this problem maybe only I met. > >>> + if (!strtab) { >>> + dev_err(smmu->dev, "failed to allocate l1 stream table\n"); >>> + return -ENOMEM; >>> + } >>> + smmu->strtab_cfg.strtab = strtab; >>> + >>> + reg = smmu->strtab_cfg.strtab_dma & >>> + STRTAB_BASE_ADDR_MASK << STRTAB_BASE_ADDR_SHIFT; >>> + reg |= STRTAB_BASE_RA; >>> + smmu->strtab_cfg.strtab_base = reg; >>> + >>> + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { >>> + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3); >>> + smmu->strtab_cfg.num_l1_descs = 1 << size; >>> + size += STRTAB_SPLIT; >>> + reg = STRTAB_BASE_CFG_FMT_2LVL; >>> + >>> + ret = arm_smmu_alloc_l2_strtab(smmu); >>> + if (ret) >>> + goto out_free_l1; >>> + } else { >>> + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_STE_DWORDS) + 3); >>> + smmu->strtab_cfg.num_l1_descs = 0; >>> + reg = STRTAB_BASE_CFG_FMT_LINEAR; >>> + arm_smmu_init_bypass_stes(strtab, 1 << size); >>> + } >>> + >>> + if (size < smmu->sid_bits) >>> + dev_warn(smmu->dev, "%s strtab only covers %u/%u bits of SID\n", >>> + smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB ? >>> + "2-level" : "linear", >>> + size, smmu->sid_bits); >>> + >>> + reg |= (size & STRTAB_BASE_CFG_LOG2SIZE_MASK) >>> + << STRTAB_BASE_CFG_LOG2SIZE_SHIFT; >>> + reg |= (STRTAB_SPLIT & STRTAB_BASE_CFG_SPLIT_MASK) >>> + << STRTAB_BASE_CFG_SPLIT_SHIFT; >>> + smmu->strtab_cfg.strtab_base_cfg = reg; >>> + >>> + /* Allocate the first VMID for stage-2 bypass STEs */ >>> + set_bit(0, smmu->vmid_map); >>> + return 0; >>> + >>> +out_free_l1: >>> + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, strtab, >>> + smmu->strtab_cfg.strtab_dma); >>> + return ret; >>> +} >>> + >>> +static void arm_smmu_free_strtab(struct arm_smmu_device *smmu) >>> +{ >>> + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; >>> + >>> + arm_smmu_free_l2_strtab(smmu); >>> + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, cfg->strtab, >>> + cfg->strtab_dma); >>> +} >>> + >> >>> + >>> +static int arm_smmu_device_reset(struct arm_smmu_device *smmu) >>> +{ >>> + int ret; >>> + u32 reg, enables; >>> + struct arm_smmu_cmdq_ent cmd; >>> + >>> + /* Clear CR0 and sync (disables SMMU and queue processing) */ >>> + reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); >>> + if (reg & CR0_SMMUEN) >>> + dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); >>> + >>> + ret = arm_smmu_device_disable(smmu); >>> + if (ret) >>> + return ret; >>> + >>> + /* CR1 (table and queue memory attributes) */ >>> + reg = (CR1_SH_ISH << CR1_TABLE_SH_SHIFT) | >>> + (CR1_CACHE_WB << CR1_TABLE_OC_SHIFT) | >>> + (CR1_CACHE_WB << CR1_TABLE_IC_SHIFT) | >>> + (CR1_SH_ISH << CR1_QUEUE_SH_SHIFT) | >>> + (CR1_CACHE_WB << CR1_QUEUE_OC_SHIFT) | >>> + (CR1_CACHE_WB << CR1_QUEUE_IC_SHIFT); >>> + writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); >>> + >>> + /* CR2 (random crap) */ >>> + reg = CR2_PTM | CR2_RECINVMID | CR2_E2H; >> >> Do we need to explicitly set CR2_E2H? Linux only run at EL1. > > Setting E2H won't cause any harm and I'd expect Linux to run there in the > future. If we ever decide to share CPU page tables with the SMMU, then we'll > need this set to participate in DVM. OK > >>> + writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); >>> + >>> + /* Stream table */ >>> + writeq_relaxed(smmu->strtab_cfg.strtab_base, >>> + smmu->base + ARM_SMMU_STRTAB_BASE); >>> + writel_relaxed(smmu->strtab_cfg.strtab_base_cfg, >>> + smmu->base + ARM_SMMU_STRTAB_BASE_CFG); >>> + >>> + /* Command queue */ >>> + writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); >>> + writel_relaxed(smmu->cmdq.q.prod, smmu->base + ARM_SMMU_CMDQ_PROD); >>> + writel_relaxed(smmu->cmdq.q.cons, smmu->base + ARM_SMMU_CMDQ_CONS); >>> + >>> + enables = CR0_CMDQEN; >>> + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, >>> + ARM_SMMU_CR0ACK); >>> + if (ret) { >>> + dev_err(smmu->dev, "failed to enable command queue\n"); >>> + return ret; >>> + } >>> + >>> + /* Invalidate any cached configuration */ >>> + cmd.opcode = CMDQ_OP_CFGI_ALL; >>> + arm_smmu_cmdq_issue_cmd(smmu, &cmd); >>> + cmd.opcode = CMDQ_OP_CMD_SYNC; >>> + arm_smmu_cmdq_issue_cmd(smmu, &cmd); >>> + >>> + /* Invalidate any stale TLB entries */ >>> + cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; >> >> Do we need to execute CMDQ_OP_TLBI_EL2_ALL? Linux only run at EL1. It at >> least rely on SMMU_IDR0.Hyp > > The SMMU isn't guaranteed to come up clean out of reset, so it's a good > idea to perform this invalidation in case of junk in the TLB. Given that > Linux owns the stage-2 translation, then this is the right place to do it. OK. But it should be controled by SMMU_IDR0.Hyp. I means: if (SMMU_IDR0.Hyp) execute command CMDQ_OP_TLBI_EL2_ALL When SMMU_IDR0.Hyp=’0’, this command causes CERROR_ILL > > Will > > . > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-05-13 8:33 ` leizhen 0 siblings, 0 replies; 40+ messages in thread From: leizhen @ 2015-05-13 8:33 UTC (permalink / raw) To: linux-arm-kernel On 2015/5/13 0:55, Will Deacon wrote: > Hi Leizhen, > > Thanks for the review! > > On Tue, May 12, 2015 at 08:40:06AM +0100, leizhen wrote: >> >>> + >>> +static int queue_poll_cons(struct arm_smmu_queue *q, u32 until, bool wfe) >>> +{ >>> + ktime_t timeout = ktime_add_us(ktime_get(), ARM_SMMU_POLL_TIMEOUT_US); >>> + >>> + while (queue_sync_cons(q), __queue_cons_before(q, until)) { >>> + if (ktime_compare(ktime_get(), timeout) > 0) >> >> Is it good to limit hardware behavior? May be wait for ever will be >> better. If SMMU can not consume queue items under normal condition, the >> SMMU hardware is broken, will lead software system to be crashed later. > > I disagree. Having a broken SMMU lock-up the entire kernel is considerably > worse than having e.g. a DMA master get stuck. If this timeout expires, > then we'll print a message and continue without waiting any longer for > a CMD_SYNC completion (see arm_smmu_cmdq_issue_cmd). OK > >>> + return -ETIMEDOUT; >>> + >>> + if (wfe) { >>> + wfe(); >>> + } else { >>> + cpu_relax(); >>> + udelay(1); >>> + } >>> + } >>> + >>> + return 0; >>> +} >>> + >>> +static void queue_write(__le64 *dst, u64 *src, size_t n_dwords) >>> +{ >>> + int i; >>> + >>> + for (i = 0; i < n_dwords; ++i) >>> + *dst++ = cpu_to_le64(*src++); >>> +} >>> + >>> +static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent) >>> +{ >>> + if (queue_full(q)) >>> + return -ENOSPC; >>> + >>> + queue_write(Q_ENT(q, q->prod), ent, q->ent_dwords); >> >> A dmb or dsb maybe needed. We must insure all data written are completed, >> then notify hardware to consume. > > The dsb is performed when we update the producer pointer in queue_inc_prod > (since we use writel as opposed to writel_relaxed). OK, I saw. > >>> + queue_inc_prod(q); >>> + return 0; >>> +} >>> + >>> + >>> +/* High-level queue accessors */ >>> +static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) >>> +{ >>> + memset(cmd, 0, CMDQ_ENT_DWORDS << 3); >>> + cmd[0] |= (ent->opcode & CMDQ_0_OP_MASK) << CMDQ_0_OP_SHIFT; >>> + >>> + switch (ent->opcode) { >>> + case CMDQ_OP_TLBI_EL2_ALL: >> >>> + case CMDQ_OP_CMD_SYNC: >>> + cmd[0] |= CMDQ_SYNC_0_CS_SEV; >> >> We can not always set SIG_SEV, actually it should base upon >> SMMU_IDR0.SEV(smmu->features & ARM_SMMU_FEAT_SEV) > > It doesn't matter for the CMD_SYNC command (which treats SIG_SEV as > SIG_NONE in this case). What actually matters is that we don't perform > wfe() when the SMMU can't issue the event, but that's already taken care > of in arm_smmu_cmdq_issue_cmd. OK > >>> + break; >>> + default: >>> + return -ENOENT; >>> + } >>> + >>> + return 0; >>> +} >> >>> + >>> +static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, >>> + struct io_pgtable_cfg *pgtbl_cfg) >>> +{ >>> + int ret; >>> + u16 asid; >>> + struct arm_smmu_device *smmu = smmu_domain->smmu; >>> + struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; >>> + >>> + asid = arm_smmu_bitmap_alloc(smmu->asid_map, smmu->asid_bits); >>> + if (IS_ERR_VALUE(asid)) >>> + return asid; >>> + >>> + cfg->cdptr = dma_zalloc_coherent(smmu->dev, CTXDESC_CD_DWORDS << 3, >>> + &cfg->cdptr_dma, GFP_KERNEL); >> >> Why use dma_zalloc_coherent? iova is coverted from PA by calling >> phys_to_dma. I afraid PA and iova maybe not equal. In fact, the mapping >> between iova and PA is rely on SMMU driver itself. Why not use >> virt_to_phys to get PA, SMMU hardware actually require PA. > > The SMMU structure walker is not allowed to be chained into another SMMU, > so the physical and DMA addresses are equal here. That said, the walker > does not need to be cache coherent, so I need to use the coherent DMA > allocator to get memory of the correct attributes. I also need the table > to be naturally aligned. > > An alternative would be something like __get_free_pages with homebrew > cache maintenance for non-coherent SMMUs, but I don't want to re-invent > the DMA mapping code in the driver (we already have a similar mess with > the page tables, which I'd like to sort out). OK, I have not considered non-coherent SMMU before. But non-coherent SMMU maybe rare. > >>> +static int arm_smmu_alloc_l2_strtab(struct arm_smmu_device *smmu) >>> +{ >>> + int ret; >>> + unsigned int i; >>> + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; >>> + size_t size = sizeof(*cfg->l1_desc) * cfg->num_l1_descs; >>> + void *strtab = smmu->strtab_cfg.strtab; >>> + >>> + cfg->l1_desc = devm_kzalloc(smmu->dev, size, GFP_KERNEL); >>> + if (!cfg->l1_desc) { >>> + dev_err(smmu->dev, "failed to allocate l1 stream table desc\n"); >>> + return -ENOMEM; >>> + } >>> + >>> + size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3); >>> + for (i = 0; i < cfg->num_l1_descs; ++i) { >>> + struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[i]; >>> + >>> + desc->span = STRTAB_SPLIT + 1; >>> + desc->l2ptr = dma_zalloc_coherent(smmu->dev, size, >>> + &desc->l2ptr_dma, GFP_KERNEL); >> >> No, no, please don't allocate all Lv2 table memory, we should dynamic >> allocation when needed. Otherwise we can not save memory relative to one >> level table. And cfg->l1_desc seems not necessary. Before create mapping >> for a specified StreamID, we read corresponding Lv1 table entry, if L2Ptr >> is NULL, then we build Lv2 table. Otherwise, means this Lv2 table have >> already been built, because a Lv2 table is shared by a group of StreamIDs. > > The purpose of the two level approach isn't to save memory; it's to remove > the need for a single (large) contiguous block. Furthermore, we need all > master devices in the system to come up in a state where their transactions > bypass the SMMU (i.e. we don't require them to use the SMMU for > translation). Achieving this necessitates a fully-populated stream-table > before any DMA occurs. OK, but for non-pci devices(maybe pci devices also), initialize all devices(StreamIDs) to bypass mode maybe incorrect. Some devices maybe capable bring attributes by itself, and access different memory with different attributes(device attribute or cacheable attribute); some devices maybe not capable bring attributes by itself, but need access memory with cacheable attribute only, so we should set STE.MTCFG = 1. Provide dts configuration will be better. Oh, I can do it after your patches upstreamed, because this problem maybe only I met. Furthermore, I don't agree initialize all devices to bypass by default. Suppose a non-pci device's StreamID can be dynamic configured. We require StreamID-A, but the device actually issue StreamID-B because of software configuration fault. We really hope SMMU can report Bad StreamID fault. > > I suppose we could look into populating it based on the ->add_device > callback, which currently does have some range checks > (arm_smmu_sid_in_range). Is that what you had in mind? Yes, maybe attach_dev. But we should allocated the whole Lv1 table base on SMMU_IDR1.SIDSIZE > >>> + if (!desc->l2ptr) { >>> + dev_err(smmu->dev, >>> + "failed to allocate l2 stream table %u\n", i); >>> + ret = -ENOMEM; >>> + goto out_free_l2; >>> + } >>> + >>> + arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); >>> + arm_smmu_write_strtab_l1_desc(strtab, desc); >>> + strtab += STRTAB_STE_DWORDS; >>> + } >>> + >>> + return 0; >>> + >>> +out_free_l2: >>> + arm_smmu_free_l2_strtab(smmu); >>> + return ret; >>> +} >>> + >>> +static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) >>> +{ >>> + void *strtab; >>> + u64 reg; >>> + u32 size; >>> + int ret = 0; >>> + >>> + strtab = dma_zalloc_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, >>> + &smmu->strtab_cfg.strtab_dma, GFP_KERNEL); >> >> As above, when Lv2 tables are dynamic allocation, we can create Lv1 table >> base on SMMU_IDR1.SIDSIZE and support non-pic devices. Oh, if SIDSIZE is >> too large, like 32. Maybe we should use 64K size Lv2 table. But we can >> only use PAGE_SIZE first, for lazy. > > Right now, the l2 tables are 4k and l1 table is 8k. That's (a) nice for > allocation on a system with 4k pages and (b) enough to cover a PCI host > controller. The problem with supporting 32-bit SIDs is that the l1 will > become a sizeable contiguous chunk which we'll have to allocate > regardless. > > So, if we keep the l2 size at 4k for the moment, how big would you like > the l1? For a 32-bit numberspace, it would be 4MB, which I don't think is > practical. Yes, because I don't think SMMU_IDR1.SIDSIZE = 32 really exist, so I said use PAGE_SIZE first. But now, this patch only support SMMU_IDR1.SIDSIZE <= 16. Suppose SMMU_IDR1.SIDSIZE = 25?Lv2 table size@4K, then Lv1 table need 2^(25 - 6 + 3) = 2^22 = 4M. If we pre-allocated all Lv2 table, we need 2^25 * 64 = 2^31 = 2G, that's too big. So we must only allocate Lv2 table when we needed. If SMMU_IDR1.SIDSIZE = 32 really exist(or too big), we need dynamic choose Lv2 table size(4K,16K,64K). Because Lv1 table maybe too big, and can not be allocated by current API, a dts configuration should be added, like lv1-table-base = <0x0 0x0>, and we use ioremap_cache get VA(maybe ioremap, for non-coherent SMMU). Oh, I can do it after your patches upstreamed, because this problem maybe only I met. > >>> + if (!strtab) { >>> + dev_err(smmu->dev, "failed to allocate l1 stream table\n"); >>> + return -ENOMEM; >>> + } >>> + smmu->strtab_cfg.strtab = strtab; >>> + >>> + reg = smmu->strtab_cfg.strtab_dma & >>> + STRTAB_BASE_ADDR_MASK << STRTAB_BASE_ADDR_SHIFT; >>> + reg |= STRTAB_BASE_RA; >>> + smmu->strtab_cfg.strtab_base = reg; >>> + >>> + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { >>> + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3); >>> + smmu->strtab_cfg.num_l1_descs = 1 << size; >>> + size += STRTAB_SPLIT; >>> + reg = STRTAB_BASE_CFG_FMT_2LVL; >>> + >>> + ret = arm_smmu_alloc_l2_strtab(smmu); >>> + if (ret) >>> + goto out_free_l1; >>> + } else { >>> + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_STE_DWORDS) + 3); >>> + smmu->strtab_cfg.num_l1_descs = 0; >>> + reg = STRTAB_BASE_CFG_FMT_LINEAR; >>> + arm_smmu_init_bypass_stes(strtab, 1 << size); >>> + } >>> + >>> + if (size < smmu->sid_bits) >>> + dev_warn(smmu->dev, "%s strtab only covers %u/%u bits of SID\n", >>> + smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB ? >>> + "2-level" : "linear", >>> + size, smmu->sid_bits); >>> + >>> + reg |= (size & STRTAB_BASE_CFG_LOG2SIZE_MASK) >>> + << STRTAB_BASE_CFG_LOG2SIZE_SHIFT; >>> + reg |= (STRTAB_SPLIT & STRTAB_BASE_CFG_SPLIT_MASK) >>> + << STRTAB_BASE_CFG_SPLIT_SHIFT; >>> + smmu->strtab_cfg.strtab_base_cfg = reg; >>> + >>> + /* Allocate the first VMID for stage-2 bypass STEs */ >>> + set_bit(0, smmu->vmid_map); >>> + return 0; >>> + >>> +out_free_l1: >>> + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, strtab, >>> + smmu->strtab_cfg.strtab_dma); >>> + return ret; >>> +} >>> + >>> +static void arm_smmu_free_strtab(struct arm_smmu_device *smmu) >>> +{ >>> + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; >>> + >>> + arm_smmu_free_l2_strtab(smmu); >>> + dma_free_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, cfg->strtab, >>> + cfg->strtab_dma); >>> +} >>> + >> >>> + >>> +static int arm_smmu_device_reset(struct arm_smmu_device *smmu) >>> +{ >>> + int ret; >>> + u32 reg, enables; >>> + struct arm_smmu_cmdq_ent cmd; >>> + >>> + /* Clear CR0 and sync (disables SMMU and queue processing) */ >>> + reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); >>> + if (reg & CR0_SMMUEN) >>> + dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); >>> + >>> + ret = arm_smmu_device_disable(smmu); >>> + if (ret) >>> + return ret; >>> + >>> + /* CR1 (table and queue memory attributes) */ >>> + reg = (CR1_SH_ISH << CR1_TABLE_SH_SHIFT) | >>> + (CR1_CACHE_WB << CR1_TABLE_OC_SHIFT) | >>> + (CR1_CACHE_WB << CR1_TABLE_IC_SHIFT) | >>> + (CR1_SH_ISH << CR1_QUEUE_SH_SHIFT) | >>> + (CR1_CACHE_WB << CR1_QUEUE_OC_SHIFT) | >>> + (CR1_CACHE_WB << CR1_QUEUE_IC_SHIFT); >>> + writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); >>> + >>> + /* CR2 (random crap) */ >>> + reg = CR2_PTM | CR2_RECINVMID | CR2_E2H; >> >> Do we need to explicitly set CR2_E2H? Linux only run at EL1. > > Setting E2H won't cause any harm and I'd expect Linux to run there in the > future. If we ever decide to share CPU page tables with the SMMU, then we'll > need this set to participate in DVM. OK > >>> + writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); >>> + >>> + /* Stream table */ >>> + writeq_relaxed(smmu->strtab_cfg.strtab_base, >>> + smmu->base + ARM_SMMU_STRTAB_BASE); >>> + writel_relaxed(smmu->strtab_cfg.strtab_base_cfg, >>> + smmu->base + ARM_SMMU_STRTAB_BASE_CFG); >>> + >>> + /* Command queue */ >>> + writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); >>> + writel_relaxed(smmu->cmdq.q.prod, smmu->base + ARM_SMMU_CMDQ_PROD); >>> + writel_relaxed(smmu->cmdq.q.cons, smmu->base + ARM_SMMU_CMDQ_CONS); >>> + >>> + enables = CR0_CMDQEN; >>> + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, >>> + ARM_SMMU_CR0ACK); >>> + if (ret) { >>> + dev_err(smmu->dev, "failed to enable command queue\n"); >>> + return ret; >>> + } >>> + >>> + /* Invalidate any cached configuration */ >>> + cmd.opcode = CMDQ_OP_CFGI_ALL; >>> + arm_smmu_cmdq_issue_cmd(smmu, &cmd); >>> + cmd.opcode = CMDQ_OP_CMD_SYNC; >>> + arm_smmu_cmdq_issue_cmd(smmu, &cmd); >>> + >>> + /* Invalidate any stale TLB entries */ >>> + cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; >> >> Do we need to execute CMDQ_OP_TLBI_EL2_ALL? Linux only run at EL1. It at >> least rely on SMMU_IDR0.Hyp > > The SMMU isn't guaranteed to come up clean out of reset, so it's a good > idea to perform this invalidation in case of junk in the TLB. Given that > Linux owns the stage-2 translation, then this is the right place to do it. OK. But it should be controled by SMMU_IDR0.Hyp. I means: if (SMMU_IDR0.Hyp) execute command CMDQ_OP_TLBI_EL2_ALL When SMMU_IDR0.Hyp=?0?, this command causes CERROR_ILL > > Will > > . > ^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <55530C4F.5000605-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-05-13 8:33 ` leizhen @ 2015-05-21 11:25 ` Will Deacon -1 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-21 11:25 UTC (permalink / raw) To: leizhen Cc: huxinwei-hv44wF8Li93QT0dZR+AlfA, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Sanil kumar, Gaojianbo, Dingtianhong, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hi again, Sorry for the delay in replying, I've been tied up with other stuff. On Wed, May 13, 2015 at 09:33:19AM +0100, leizhen wrote: > On 2015/5/13 0:55, Will Deacon wrote: > > The purpose of the two level approach isn't to save memory; it's to remove > > the need for a single (large) contiguous block. Furthermore, we need all > > master devices in the system to come up in a state where their transactions > > bypass the SMMU (i.e. we don't require them to use the SMMU for > > translation). Achieving this necessitates a fully-populated stream-table > > before any DMA occurs. > > OK, but for non-pci devices(maybe pci devices also), initialize all > devices(StreamIDs) to bypass mode maybe incorrect. Some devices maybe > capable bring attributes by itself, and access different memory with > different attributes(device attribute or cacheable attribute); some > devices maybe not capable bring attributes by itself, but need access > memory with cacheable attribute only, so we should set STE.MTCFG = 1. > Provide dts configuration will be better. If we want to make use of memory overrides, then I think we should add that as a separate patch because it would have implications on the IOMMU API. I don't particularly like putting this policy information in the device-tree binding on a per-driver basis. > Furthermore, I don't agree initialize all devices to bypass by default. > Suppose a non-pci device's StreamID can be dynamic configured. We require > StreamID-A, but the device actually issue StreamID-B because of software > configuration fault. We really hope SMMU can report Bad StreamID fault. I think the default behaviour has to be to bypass by default, otherwise we can break DMA for any devices behind an SMMU but not attached to an IOMMU domain. How about I add a cmdline parameter to change the default behaviour? > > I suppose we could look into populating it based on the ->add_device > > callback, which currently does have some range checks > > (arm_smmu_sid_in_range). Is that what you had in mind? > > Yes, maybe attach_dev. But we should allocated the whole Lv1 table base on > SMMU_IDR1.SIDSIZE I think it needs to be in add_device so that we can implement the default bypass case. We could even have one L2 table per PCI bus, but I need to think about how big the L1 table should be. > >>> + if (!desc->l2ptr) { > >>> + dev_err(smmu->dev, > >>> + "failed to allocate l2 stream table %u\n", i); > >>> + ret = -ENOMEM; > >>> + goto out_free_l2; > >>> + } > >>> + > >>> + arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); > >>> + arm_smmu_write_strtab_l1_desc(strtab, desc); > >>> + strtab += STRTAB_STE_DWORDS; > >>> + } > >>> + > >>> + return 0; > >>> + > >>> +out_free_l2: > >>> + arm_smmu_free_l2_strtab(smmu); > >>> + return ret; > >>> +} > >>> + > >>> +static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) > >>> +{ > >>> + void *strtab; > >>> + u64 reg; > >>> + u32 size; > >>> + int ret = 0; > >>> + > >>> + strtab = dma_zalloc_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, > >>> + &smmu->strtab_cfg.strtab_dma, GFP_KERNEL); > >> > >> As above, when Lv2 tables are dynamic allocation, we can create Lv1 table > >> base on SMMU_IDR1.SIDSIZE and support non-pic devices. Oh, if SIDSIZE is > >> too large, like 32. Maybe we should use 64K size Lv2 table. But we can > >> only use PAGE_SIZE first, for lazy. > > > > Right now, the l2 tables are 4k and l1 table is 8k. That's (a) nice for > > allocation on a system with 4k pages and (b) enough to cover a PCI host > > controller. The problem with supporting 32-bit SIDs is that the l1 will > > become a sizeable contiguous chunk which we'll have to allocate > > regardless. > > > > So, if we keep the l2 size at 4k for the moment, how big would you like > > the l1? For a 32-bit numberspace, it would be 4MB, which I don't think is > > practical. > > Yes, because I don't think SMMU_IDR1.SIDSIZE = 32 really exist, so I said > use PAGE_SIZE first. Well, I certainly wouldn't rule anything out. > But now, this patch only support SMMU_IDR1.SIDSIZE <= 16. Suppose > SMMU_IDR1.SIDSIZE = 25，Lv2 table size at 4K, then Lv1 table need 2^(25 - > 6 + 3) = 2^22 = 4M. If we pre-allocated all Lv2 table, we need 2^25 * 64 = > 2^31 = 2G, that's too big. So we must only allocate Lv2 table when we > needed. I agree that's way too big, but I have limited things to 16-bit for a reason ;) > If SMMU_IDR1.SIDSIZE = 32 really exist(or too big), we need dynamic choose > Lv2 table size(4K,16K,64K). Because Lv1 table maybe too big, and can not > be allocated by current API, a dts configuration should be added, like > lv1-table-base = <0x0 0x0>, and we use ioremap_cache get VA(maybe ioremap, > for non-coherent SMMU). > > Oh, I can do it after your patches upstreamed, because this problem maybe > only I met. I'll have a think about this and see what I can come up with for version 2 of the patch. I'd like to avoid adding additional properties to the DT until they're actually needed, though. > >>> + /* Invalidate any cached configuration */ > >>> + cmd.opcode = CMDQ_OP_CFGI_ALL; > >>> + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > >>> + cmd.opcode = CMDQ_OP_CMD_SYNC; > >>> + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > >>> + > >>> + /* Invalidate any stale TLB entries */ > >>> + cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; > >> > >> Do we need to execute CMDQ_OP_TLBI_EL2_ALL? Linux only run at EL1. It at > >> least rely on SMMU_IDR0.Hyp > > > > The SMMU isn't guaranteed to come up clean out of reset, so it's a good > > idea to perform this invalidation in case of junk in the TLB. Given that > > Linux owns the stage-2 translation, then this is the right place to do it. > > OK. But it should be controled by SMMU_IDR0.Hyp. I means: > if (SMMU_IDR0.Hyp) > execute command CMDQ_OP_TLBI_EL2_ALL > > When SMMU_IDR0.Hyp=’0’, this command causes CERROR_ILL Well spotted, thanks! Will _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-05-21 11:25 ` Will Deacon 0 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-21 11:25 UTC (permalink / raw) To: linux-arm-kernel Hi again, Sorry for the delay in replying, I've been tied up with other stuff. On Wed, May 13, 2015 at 09:33:19AM +0100, leizhen wrote: > On 2015/5/13 0:55, Will Deacon wrote: > > The purpose of the two level approach isn't to save memory; it's to remove > > the need for a single (large) contiguous block. Furthermore, we need all > > master devices in the system to come up in a state where their transactions > > bypass the SMMU (i.e. we don't require them to use the SMMU for > > translation). Achieving this necessitates a fully-populated stream-table > > before any DMA occurs. > > OK, but for non-pci devices(maybe pci devices also), initialize all > devices(StreamIDs) to bypass mode maybe incorrect. Some devices maybe > capable bring attributes by itself, and access different memory with > different attributes(device attribute or cacheable attribute); some > devices maybe not capable bring attributes by itself, but need access > memory with cacheable attribute only, so we should set STE.MTCFG = 1. > Provide dts configuration will be better. If we want to make use of memory overrides, then I think we should add that as a separate patch because it would have implications on the IOMMU API. I don't particularly like putting this policy information in the device-tree binding on a per-driver basis. > Furthermore, I don't agree initialize all devices to bypass by default. > Suppose a non-pci device's StreamID can be dynamic configured. We require > StreamID-A, but the device actually issue StreamID-B because of software > configuration fault. We really hope SMMU can report Bad StreamID fault. I think the default behaviour has to be to bypass by default, otherwise we can break DMA for any devices behind an SMMU but not attached to an IOMMU domain. How about I add a cmdline parameter to change the default behaviour? > > I suppose we could look into populating it based on the ->add_device > > callback, which currently does have some range checks > > (arm_smmu_sid_in_range). Is that what you had in mind? > > Yes, maybe attach_dev. But we should allocated the whole Lv1 table base on > SMMU_IDR1.SIDSIZE I think it needs to be in add_device so that we can implement the default bypass case. We could even have one L2 table per PCI bus, but I need to think about how big the L1 table should be. > >>> + if (!desc->l2ptr) { > >>> + dev_err(smmu->dev, > >>> + "failed to allocate l2 stream table %u\n", i); > >>> + ret = -ENOMEM; > >>> + goto out_free_l2; > >>> + } > >>> + > >>> + arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); > >>> + arm_smmu_write_strtab_l1_desc(strtab, desc); > >>> + strtab += STRTAB_STE_DWORDS; > >>> + } > >>> + > >>> + return 0; > >>> + > >>> +out_free_l2: > >>> + arm_smmu_free_l2_strtab(smmu); > >>> + return ret; > >>> +} > >>> + > >>> +static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) > >>> +{ > >>> + void *strtab; > >>> + u64 reg; > >>> + u32 size; > >>> + int ret = 0; > >>> + > >>> + strtab = dma_zalloc_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, > >>> + &smmu->strtab_cfg.strtab_dma, GFP_KERNEL); > >> > >> As above, when Lv2 tables are dynamic allocation, we can create Lv1 table > >> base on SMMU_IDR1.SIDSIZE and support non-pic devices. Oh, if SIDSIZE is > >> too large, like 32. Maybe we should use 64K size Lv2 table. But we can > >> only use PAGE_SIZE first, for lazy. > > > > Right now, the l2 tables are 4k and l1 table is 8k. That's (a) nice for > > allocation on a system with 4k pages and (b) enough to cover a PCI host > > controller. The problem with supporting 32-bit SIDs is that the l1 will > > become a sizeable contiguous chunk which we'll have to allocate > > regardless. > > > > So, if we keep the l2 size at 4k for the moment, how big would you like > > the l1? For a 32-bit numberspace, it would be 4MB, which I don't think is > > practical. > > Yes, because I don't think SMMU_IDR1.SIDSIZE = 32 really exist, so I said > use PAGE_SIZE first. Well, I certainly wouldn't rule anything out. > But now, this patch only support SMMU_IDR1.SIDSIZE <= 16. Suppose > SMMU_IDR1.SIDSIZE = 25?Lv2 table size at 4K, then Lv1 table need 2^(25 - > 6 + 3) = 2^22 = 4M. If we pre-allocated all Lv2 table, we need 2^25 * 64 = > 2^31 = 2G, that's too big. So we must only allocate Lv2 table when we > needed. I agree that's way too big, but I have limited things to 16-bit for a reason ;) > If SMMU_IDR1.SIDSIZE = 32 really exist(or too big), we need dynamic choose > Lv2 table size(4K,16K,64K). Because Lv1 table maybe too big, and can not > be allocated by current API, a dts configuration should be added, like > lv1-table-base = <0x0 0x0>, and we use ioremap_cache get VA(maybe ioremap, > for non-coherent SMMU). > > Oh, I can do it after your patches upstreamed, because this problem maybe > only I met. I'll have a think about this and see what I can come up with for version 2 of the patch. I'd like to avoid adding additional properties to the DT until they're actually needed, though. > >>> + /* Invalidate any cached configuration */ > >>> + cmd.opcode = CMDQ_OP_CFGI_ALL; > >>> + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > >>> + cmd.opcode = CMDQ_OP_CMD_SYNC; > >>> + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > >>> + > >>> + /* Invalidate any stale TLB entries */ > >>> + cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; > >> > >> Do we need to execute CMDQ_OP_TLBI_EL2_ALL? Linux only run at EL1. It at > >> least rely on SMMU_IDR0.Hyp > > > > The SMMU isn't guaranteed to come up clean out of reset, so it's a good > > idea to perform this invalidation in case of junk in the TLB. Given that > > Linux owns the stage-2 translation, then this is the right place to do it. > > OK. But it should be controled by SMMU_IDR0.Hyp. I means: > if (SMMU_IDR0.Hyp) > execute command CMDQ_OP_TLBI_EL2_ALL > > When SMMU_IDR0.Hyp=?0?, this command causes CERROR_ILL Well spotted, thanks! Will ^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <20150521112555.GH21920-5wv7dgnIgG8@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-05-21 11:25 ` Will Deacon @ 2015-05-25 2:07 ` leizhen -1 siblings, 0 replies; 40+ messages in thread From: leizhen @ 2015-05-25 2:07 UTC (permalink / raw) To: Will Deacon Cc: huxinwei-hv44wF8Li93QT0dZR+AlfA, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Sanil kumar, Gaojianbo, Dingtianhong, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On 2015/5/21 19:25, Will Deacon wrote: > Hi again, > > Sorry for the delay in replying, I've been tied up with other stuff. > > On Wed, May 13, 2015 at 09:33:19AM +0100, leizhen wrote: >> On 2015/5/13 0:55, Will Deacon wrote: >>> The purpose of the two level approach isn't to save memory; it's to remove >>> the need for a single (large) contiguous block. Furthermore, we need all >>> master devices in the system to come up in a state where their transactions >>> bypass the SMMU (i.e. we don't require them to use the SMMU for >>> translation). Achieving this necessitates a fully-populated stream-table >>> before any DMA occurs. >> >> OK, but for non-pci devices(maybe pci devices also), initialize all >> devices(StreamIDs) to bypass mode maybe incorrect. Some devices maybe >> capable bring attributes by itself, and access different memory with >> different attributes(device attribute or cacheable attribute); some >> devices maybe not capable bring attributes by itself, but need access >> memory with cacheable attribute only, so we should set STE.MTCFG = 1. >> Provide dts configuration will be better. > > If we want to make use of memory overrides, then I think we should add > that as a separate patch because it would have implications on the IOMMU > API. I don't particularly like putting this policy information in the > device-tree binding on a per-driver basis. OK. I will reconsider. > >> Furthermore, I don't agree initialize all devices to bypass by default. >> Suppose a non-pci device's StreamID can be dynamic configured. We require >> StreamID-A, but the device actually issue StreamID-B because of software >> configuration fault. We really hope SMMU can report Bad StreamID fault. > > I think the default behaviour has to be to bypass by default, otherwise > we can break DMA for any devices behind an SMMU but not attached to an > IOMMU domain. How about I add a cmdline parameter to change the default > behaviour? > Sure, so that people can choose by themselves. The cmdline parameter will be good for non-pci devices. >>> I suppose we could look into populating it based on the ->add_device >>> callback, which currently does have some range checks >>> (arm_smmu_sid_in_range). Is that what you had in mind? >> >> Yes, maybe attach_dev. But we should allocated the whole Lv1 table base on >> SMMU_IDR1.SIDSIZE > > I think it needs to be in add_device so that we can implement the default OK > bypass case. We could even have one L2 table per PCI bus, but I need to > think about how big the L1 table should be. > >>>>> + if (!desc->l2ptr) { >>>>> + dev_err(smmu->dev, >>>>> + "failed to allocate l2 stream table %u\n", i); >>>>> + ret = -ENOMEM; >>>>> + goto out_free_l2; >>>>> + } >>>>> + >>>>> + arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); >>>>> + arm_smmu_write_strtab_l1_desc(strtab, desc); >>>>> + strtab += STRTAB_STE_DWORDS; >>>>> + } >>>>> + >>>>> + return 0; >>>>> + >>>>> +out_free_l2: >>>>> + arm_smmu_free_l2_strtab(smmu); >>>>> + return ret; >>>>> +} >>>>> + >>>>> +static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) >>>>> +{ >>>>> + void *strtab; >>>>> + u64 reg; >>>>> + u32 size; >>>>> + int ret = 0; >>>>> + >>>>> + strtab = dma_zalloc_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, >>>>> + &smmu->strtab_cfg.strtab_dma, GFP_KERNEL); >>>> >>>> As above, when Lv2 tables are dynamic allocation, we can create Lv1 table >>>> base on SMMU_IDR1.SIDSIZE and support non-pic devices. Oh, if SIDSIZE is >>>> too large, like 32. Maybe we should use 64K size Lv2 table. But we can >>>> only use PAGE_SIZE first, for lazy. >>> >>> Right now, the l2 tables are 4k and l1 table is 8k. That's (a) nice for >>> allocation on a system with 4k pages and (b) enough to cover a PCI host >>> controller. The problem with supporting 32-bit SIDs is that the l1 will >>> become a sizeable contiguous chunk which we'll have to allocate >>> regardless. >>> >>> So, if we keep the l2 size at 4k for the moment, how big would you like >>> the l1? For a 32-bit numberspace, it would be 4MB, which I don't think is >>> practical. >> >> Yes, because I don't think SMMU_IDR1.SIDSIZE = 32 really exist, so I said >> use PAGE_SIZE first. > > Well, I certainly wouldn't rule anything out. > >> But now, this patch only support SMMU_IDR1.SIDSIZE <= 16. Suppose >> SMMU_IDR1.SIDSIZE = 25，Lv2 table size at 4K, then Lv1 table need 2^(25 - >> 6 + 3) = 2^22 = 4M. If we pre-allocated all Lv2 table, we need 2^25 * 64 = >> 2^31 = 2G, that's too big. So we must only allocate Lv2 table when we >> needed. > > I agree that's way too big, but I have limited things to 16-bit for a reason > ;) > >> If SMMU_IDR1.SIDSIZE = 32 really exist(or too big), we need dynamic choose >> Lv2 table size(4K,16K,64K). Because Lv1 table maybe too big, and can not >> be allocated by current API, a dts configuration should be added, like >> lv1-table-base = <0x0 0x0>, and we use ioremap_cache get VA(maybe ioremap, >> for non-coherent SMMU). >> >> Oh, I can do it after your patches upstreamed, because this problem maybe >> only I met. > > I'll have a think about this and see what I can come up with for version > 2 of the patch. I'd like to avoid adding additional properties to the DT > until they're actually needed, though. OK. Will you support non-pci devices in patch version 2? > >>>>> + /* Invalidate any cached configuration */ >>>>> + cmd.opcode = CMDQ_OP_CFGI_ALL; >>>>> + arm_smmu_cmdq_issue_cmd(smmu, &cmd); >>>>> + cmd.opcode = CMDQ_OP_CMD_SYNC; >>>>> + arm_smmu_cmdq_issue_cmd(smmu, &cmd); >>>>> + >>>>> + /* Invalidate any stale TLB entries */ >>>>> + cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; >>>> >>>> Do we need to execute CMDQ_OP_TLBI_EL2_ALL? Linux only run at EL1. It at >>>> least rely on SMMU_IDR0.Hyp >>> >>> The SMMU isn't guaranteed to come up clean out of reset, so it's a good >>> idea to perform this invalidation in case of junk in the TLB. Given that >>> Linux owns the stage-2 translation, then this is the right place to do it. >> >> OK. But it should be controled by SMMU_IDR0.Hyp. I means: >> if (SMMU_IDR0.Hyp) >> execute command CMDQ_OP_TLBI_EL2_ALL >> >> When SMMU_IDR0.Hyp=’0’, this command causes CERROR_ILL > > Well spotted, thanks! > > Will > > . > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-05-25 2:07 ` leizhen 0 siblings, 0 replies; 40+ messages in thread From: leizhen @ 2015-05-25 2:07 UTC (permalink / raw) To: linux-arm-kernel On 2015/5/21 19:25, Will Deacon wrote: > Hi again, > > Sorry for the delay in replying, I've been tied up with other stuff. > > On Wed, May 13, 2015 at 09:33:19AM +0100, leizhen wrote: >> On 2015/5/13 0:55, Will Deacon wrote: >>> The purpose of the two level approach isn't to save memory; it's to remove >>> the need for a single (large) contiguous block. Furthermore, we need all >>> master devices in the system to come up in a state where their transactions >>> bypass the SMMU (i.e. we don't require them to use the SMMU for >>> translation). Achieving this necessitates a fully-populated stream-table >>> before any DMA occurs. >> >> OK, but for non-pci devices(maybe pci devices also), initialize all >> devices(StreamIDs) to bypass mode maybe incorrect. Some devices maybe >> capable bring attributes by itself, and access different memory with >> different attributes(device attribute or cacheable attribute); some >> devices maybe not capable bring attributes by itself, but need access >> memory with cacheable attribute only, so we should set STE.MTCFG = 1. >> Provide dts configuration will be better. > > If we want to make use of memory overrides, then I think we should add > that as a separate patch because it would have implications on the IOMMU > API. I don't particularly like putting this policy information in the > device-tree binding on a per-driver basis. OK. I will reconsider. > >> Furthermore, I don't agree initialize all devices to bypass by default. >> Suppose a non-pci device's StreamID can be dynamic configured. We require >> StreamID-A, but the device actually issue StreamID-B because of software >> configuration fault. We really hope SMMU can report Bad StreamID fault. > > I think the default behaviour has to be to bypass by default, otherwise > we can break DMA for any devices behind an SMMU but not attached to an > IOMMU domain. How about I add a cmdline parameter to change the default > behaviour? > Sure, so that people can choose by themselves. The cmdline parameter will be good for non-pci devices. >>> I suppose we could look into populating it based on the ->add_device >>> callback, which currently does have some range checks >>> (arm_smmu_sid_in_range). Is that what you had in mind? >> >> Yes, maybe attach_dev. But we should allocated the whole Lv1 table base on >> SMMU_IDR1.SIDSIZE > > I think it needs to be in add_device so that we can implement the default OK > bypass case. We could even have one L2 table per PCI bus, but I need to > think about how big the L1 table should be. > >>>>> + if (!desc->l2ptr) { >>>>> + dev_err(smmu->dev, >>>>> + "failed to allocate l2 stream table %u\n", i); >>>>> + ret = -ENOMEM; >>>>> + goto out_free_l2; >>>>> + } >>>>> + >>>>> + arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); >>>>> + arm_smmu_write_strtab_l1_desc(strtab, desc); >>>>> + strtab += STRTAB_STE_DWORDS; >>>>> + } >>>>> + >>>>> + return 0; >>>>> + >>>>> +out_free_l2: >>>>> + arm_smmu_free_l2_strtab(smmu); >>>>> + return ret; >>>>> +} >>>>> + >>>>> +static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) >>>>> +{ >>>>> + void *strtab; >>>>> + u64 reg; >>>>> + u32 size; >>>>> + int ret = 0; >>>>> + >>>>> + strtab = dma_zalloc_coherent(smmu->dev, 1 << STRTAB_L1_SZ_SHIFT, >>>>> + &smmu->strtab_cfg.strtab_dma, GFP_KERNEL); >>>> >>>> As above, when Lv2 tables are dynamic allocation, we can create Lv1 table >>>> base on SMMU_IDR1.SIDSIZE and support non-pic devices. Oh, if SIDSIZE is >>>> too large, like 32. Maybe we should use 64K size Lv2 table. But we can >>>> only use PAGE_SIZE first, for lazy. >>> >>> Right now, the l2 tables are 4k and l1 table is 8k. That's (a) nice for >>> allocation on a system with 4k pages and (b) enough to cover a PCI host >>> controller. The problem with supporting 32-bit SIDs is that the l1 will >>> become a sizeable contiguous chunk which we'll have to allocate >>> regardless. >>> >>> So, if we keep the l2 size at 4k for the moment, how big would you like >>> the l1? For a 32-bit numberspace, it would be 4MB, which I don't think is >>> practical. >> >> Yes, because I don't think SMMU_IDR1.SIDSIZE = 32 really exist, so I said >> use PAGE_SIZE first. > > Well, I certainly wouldn't rule anything out. > >> But now, this patch only support SMMU_IDR1.SIDSIZE <= 16. Suppose >> SMMU_IDR1.SIDSIZE = 25?Lv2 table size at 4K, then Lv1 table need 2^(25 - >> 6 + 3) = 2^22 = 4M. If we pre-allocated all Lv2 table, we need 2^25 * 64 = >> 2^31 = 2G, that's too big. So we must only allocate Lv2 table when we >> needed. > > I agree that's way too big, but I have limited things to 16-bit for a reason > ;) > >> If SMMU_IDR1.SIDSIZE = 32 really exist(or too big), we need dynamic choose >> Lv2 table size(4K,16K,64K). Because Lv1 table maybe too big, and can not >> be allocated by current API, a dts configuration should be added, like >> lv1-table-base = <0x0 0x0>, and we use ioremap_cache get VA(maybe ioremap, >> for non-coherent SMMU). >> >> Oh, I can do it after your patches upstreamed, because this problem maybe >> only I met. > > I'll have a think about this and see what I can come up with for version > 2 of the patch. I'd like to avoid adding additional properties to the DT > until they're actually needed, though. OK. Will you support non-pci devices in patch version 2? > >>>>> + /* Invalidate any cached configuration */ >>>>> + cmd.opcode = CMDQ_OP_CFGI_ALL; >>>>> + arm_smmu_cmdq_issue_cmd(smmu, &cmd); >>>>> + cmd.opcode = CMDQ_OP_CMD_SYNC; >>>>> + arm_smmu_cmdq_issue_cmd(smmu, &cmd); >>>>> + >>>>> + /* Invalidate any stale TLB entries */ >>>>> + cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; >>>> >>>> Do we need to execute CMDQ_OP_TLBI_EL2_ALL? Linux only run at EL1. It at >>>> least rely on SMMU_IDR0.Hyp >>> >>> The SMMU isn't guaranteed to come up clean out of reset, so it's a good >>> idea to perform this invalidation in case of junk in the TLB. Given that >>> Linux owns the stage-2 translation, then this is the right place to do it. >> >> OK. But it should be controled by SMMU_IDR0.Hyp. I means: >> if (SMMU_IDR0.Hyp) >> execute command CMDQ_OP_TLBI_EL2_ALL >> >> When SMMU_IDR0.Hyp=?0?, this command causes CERROR_ILL > > Well spotted, thanks! > > Will > > . > ^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <556283D5.4030901-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-05-25 2:07 ` leizhen @ 2015-05-26 16:12 ` Will Deacon -1 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-26 16:12 UTC (permalink / raw) To: leizhen Cc: huxinwei-hv44wF8Li93QT0dZR+AlfA, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Sanil kumar, Gaojianbo, Dingtianhong, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On Mon, May 25, 2015 at 03:07:17AM +0100, leizhen wrote: > On 2015/5/21 19:25, Will Deacon wrote: > > On Wed, May 13, 2015 at 09:33:19AM +0100, leizhen wrote: > >> If SMMU_IDR1.SIDSIZE = 32 really exist(or too big), we need dynamic choose > >> Lv2 table size(4K,16K,64K). Because Lv1 table maybe too big, and can not > >> be allocated by current API, a dts configuration should be added, like > >> lv1-table-base = <0x0 0x0>, and we use ioremap_cache get VA(maybe ioremap, > >> for non-coherent SMMU). > >> > >> Oh, I can do it after your patches upstreamed, because this problem maybe > >> only I met. > > > > I'll have a think about this and see what I can come up with for version > > 2 of the patch. I'd like to avoid adding additional properties to the DT > > until they're actually needed, though. > > OK. Will you support non-pci devices in patch version 2? I don't (yet) plan to support non-PCI devices, for two reasons: (1) The support should be based on top of Laurent's RFC series here: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/343686.html which needs some review etc. (2) My simulator only has PCI endpoints Of course, if you have something that you can test with, then I'm more than happy to review patches adding this support providing that they're based on the series above. On the table front, my current v2 patch uses 16k level-2 tables allocated lazily (so each one has 256 entries and covers a single PCI bus). I've also capped the SIDSIZE to 21 for the moment, which means we get a 64k table there. Sound reasonable for the time being? Will ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-05-26 16:12 ` Will Deacon 0 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-26 16:12 UTC (permalink / raw) To: linux-arm-kernel On Mon, May 25, 2015 at 03:07:17AM +0100, leizhen wrote: > On 2015/5/21 19:25, Will Deacon wrote: > > On Wed, May 13, 2015 at 09:33:19AM +0100, leizhen wrote: > >> If SMMU_IDR1.SIDSIZE = 32 really exist(or too big), we need dynamic choose > >> Lv2 table size(4K,16K,64K). Because Lv1 table maybe too big, and can not > >> be allocated by current API, a dts configuration should be added, like > >> lv1-table-base = <0x0 0x0>, and we use ioremap_cache get VA(maybe ioremap, > >> for non-coherent SMMU). > >> > >> Oh, I can do it after your patches upstreamed, because this problem maybe > >> only I met. > > > > I'll have a think about this and see what I can come up with for version > > 2 of the patch. I'd like to avoid adding additional properties to the DT > > until they're actually needed, though. > > OK. Will you support non-pci devices in patch version 2? I don't (yet) plan to support non-PCI devices, for two reasons: (1) The support should be based on top of Laurent's RFC series here: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/343686.html which needs some review etc. (2) My simulator only has PCI endpoints Of course, if you have something that you can test with, then I'm more than happy to review patches adding this support providing that they're based on the series above. On the table front, my current v2 patch uses 16k level-2 tables allocated lazily (so each one has 256 entries and covers a single PCI bus). I've also capped the SIDSIZE to 21 for the moment, which means we get a 64k table there. Sound reasonable for the time being? Will ^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <20150526161245.GR1565-5wv7dgnIgG8@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-05-26 16:12 ` Will Deacon @ 2015-05-27 9:12 ` leizhen -1 siblings, 0 replies; 40+ messages in thread From: leizhen @ 2015-05-27 9:12 UTC (permalink / raw) To: Will Deacon Cc: huxinwei-hv44wF8Li93QT0dZR+AlfA, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Sanil kumar, Gaojianbo, Dingtianhong, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On 2015/5/27 0:12, Will Deacon wrote: > On Mon, May 25, 2015 at 03:07:17AM +0100, leizhen wrote: >> On 2015/5/21 19:25, Will Deacon wrote: >>> On Wed, May 13, 2015 at 09:33:19AM +0100, leizhen wrote: >>>> If SMMU_IDR1.SIDSIZE = 32 really exist(or too big), we need dynamic choose >>>> Lv2 table size(4K,16K,64K). Because Lv1 table maybe too big, and can not >>>> be allocated by current API, a dts configuration should be added, like >>>> lv1-table-base = <0x0 0x0>, and we use ioremap_cache get VA(maybe ioremap, >>>> for non-coherent SMMU). >>>> >>>> Oh, I can do it after your patches upstreamed, because this problem maybe >>>> only I met. >>> >>> I'll have a think about this and see what I can come up with for version >>> 2 of the patch. I'd like to avoid adding additional properties to the DT >>> until they're actually needed, though. >> >> OK. Will you support non-pci devices in patch version 2? > > I don't (yet) plan to support non-PCI devices, for two reasons: > > (1) The support should be based on top of Laurent's RFC series here: > > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/343686.html > > which needs some review etc. > > (2) My simulator only has PCI endpoints > > Of course, if you have something that you can test with, then I'm more > than happy to review patches adding this support providing that they're > based on the series above. OK. I'm so glad to do it. > > On the table front, my current v2 patch uses 16k level-2 tables allocated > lazily (so each one has 256 entries and covers a single PCI bus). I've > also capped the SIDSIZE to 21 for the moment, which means we get a 64k > table there. > > Sound reasonable for the time being? OK. My SIDSIZE is 25, I will also do this. > > Will > > . > ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-05-27 9:12 ` leizhen 0 siblings, 0 replies; 40+ messages in thread From: leizhen @ 2015-05-27 9:12 UTC (permalink / raw) To: linux-arm-kernel On 2015/5/27 0:12, Will Deacon wrote: > On Mon, May 25, 2015 at 03:07:17AM +0100, leizhen wrote: >> On 2015/5/21 19:25, Will Deacon wrote: >>> On Wed, May 13, 2015 at 09:33:19AM +0100, leizhen wrote: >>>> If SMMU_IDR1.SIDSIZE = 32 really exist(or too big), we need dynamic choose >>>> Lv2 table size(4K,16K,64K). Because Lv1 table maybe too big, and can not >>>> be allocated by current API, a dts configuration should be added, like >>>> lv1-table-base = <0x0 0x0>, and we use ioremap_cache get VA(maybe ioremap, >>>> for non-coherent SMMU). >>>> >>>> Oh, I can do it after your patches upstreamed, because this problem maybe >>>> only I met. >>> >>> I'll have a think about this and see what I can come up with for version >>> 2 of the patch. I'd like to avoid adding additional properties to the DT >>> until they're actually needed, though. >> >> OK. Will you support non-pci devices in patch version 2? > > I don't (yet) plan to support non-PCI devices, for two reasons: > > (1) The support should be based on top of Laurent's RFC series here: > > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/343686.html > > which needs some review etc. > > (2) My simulator only has PCI endpoints > > Of course, if you have something that you can test with, then I'm more > than happy to review patches adding this support providing that they're > based on the series above. OK. I'm so glad to do it. > > On the table front, my current v2 patch uses 16k level-2 tables allocated > lazily (so each one has 256 entries and covers a single PCI bus). I've > also capped the SIDSIZE to 21 for the moment, which means we get a 64k > table there. > > Sound reasonable for the time being? OK. My SIDSIZE is 25, I will also do this. > > Will > > . > ^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-05-08 18:00 ` Will Deacon @ 2015-05-19 15:24 ` Joerg Roedel -1 siblings, 0 replies; 40+ messages in thread From: Joerg Roedel @ 2015-05-19 15:24 UTC (permalink / raw) To: Will Deacon Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hi Will, the code looks good overall, I just have some questions below. On Fri, May 08, 2015 at 07:00:45PM +0100, Will Deacon wrote: > +static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) > +{ > + int ret = 0; > + struct arm_smmu_device *smmu; > + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); > + struct arm_smmu_group *smmu_group = arm_smmu_group_get(dev); > + > + if (!smmu_group) > + return -ENOENT; > + > + /* Already attached to a different domain? */ > + if (smmu_group->domain && smmu_group->domain != smmu_domain) > + return -EEXIST; > + > + smmu = smmu_group->smmu; > + mutex_lock(&smmu_domain->init_mutex); > + > + if (!smmu_domain->smmu) { > + smmu_domain->smmu = smmu; > + ret = arm_smmu_domain_finalise(domain); > + if (ret) { > + smmu_domain->smmu = NULL; > + goto out_unlock; > + } > + } else if (smmu_domain->smmu != smmu) { > + dev_err(dev, > + "cannot attach to SMMU %s (upstream of %s)\n", > + dev_name(smmu_domain->smmu->dev), > + dev_name(smmu->dev)); > + ret = -ENXIO; > + goto out_unlock; > + } This looks like all devices in a domain need to be behind the same SMMU device, right? > + /* Page sizes */ > + if (reg & IDR5_GRAN64K) > + pgsize_bitmap |= SZ_64K | SZ_512M; > + if (reg & IDR5_GRAN16K) > + pgsize_bitmap |= SZ_16K | SZ_32M; > + if (reg & IDR5_GRAN4K) > + pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; > + > + arm_smmu_ops.pgsize_bitmap &= pgsize_bitmap; So this could effictivly lead to a zero pgsize_bitmap when there are SMMUs in the system with support for different page sizes, no? Joerg ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-05-19 15:24 ` Joerg Roedel 0 siblings, 0 replies; 40+ messages in thread From: Joerg Roedel @ 2015-05-19 15:24 UTC (permalink / raw) To: linux-arm-kernel Hi Will, the code looks good overall, I just have some questions below. On Fri, May 08, 2015 at 07:00:45PM +0100, Will Deacon wrote: > +static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) > +{ > + int ret = 0; > + struct arm_smmu_device *smmu; > + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); > + struct arm_smmu_group *smmu_group = arm_smmu_group_get(dev); > + > + if (!smmu_group) > + return -ENOENT; > + > + /* Already attached to a different domain? */ > + if (smmu_group->domain && smmu_group->domain != smmu_domain) > + return -EEXIST; > + > + smmu = smmu_group->smmu; > + mutex_lock(&smmu_domain->init_mutex); > + > + if (!smmu_domain->smmu) { > + smmu_domain->smmu = smmu; > + ret = arm_smmu_domain_finalise(domain); > + if (ret) { > + smmu_domain->smmu = NULL; > + goto out_unlock; > + } > + } else if (smmu_domain->smmu != smmu) { > + dev_err(dev, > + "cannot attach to SMMU %s (upstream of %s)\n", > + dev_name(smmu_domain->smmu->dev), > + dev_name(smmu->dev)); > + ret = -ENXIO; > + goto out_unlock; > + } This looks like all devices in a domain need to be behind the same SMMU device, right? > + /* Page sizes */ > + if (reg & IDR5_GRAN64K) > + pgsize_bitmap |= SZ_64K | SZ_512M; > + if (reg & IDR5_GRAN16K) > + pgsize_bitmap |= SZ_16K | SZ_32M; > + if (reg & IDR5_GRAN4K) > + pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; > + > + arm_smmu_ops.pgsize_bitmap &= pgsize_bitmap; So this could effictivly lead to a zero pgsize_bitmap when there are SMMUs in the system with support for different page sizes, no? Joerg ^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <20150519152435.GL20611-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-05-19 15:24 ` Joerg Roedel @ 2015-05-20 17:09 ` Will Deacon -1 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-20 17:09 UTC (permalink / raw) To: Joerg Roedel Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On Tue, May 19, 2015 at 04:24:35PM +0100, Joerg Roedel wrote: > Hi Will, Hi Joerg, > the code looks good overall, I just have some questions below. Great, thanks for having a look. I'll still need to post a v2 to address some of the other comments I've had. > On Fri, May 08, 2015 at 07:00:45PM +0100, Will Deacon wrote: > > +static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) > > +{ > > + int ret = 0; > > + struct arm_smmu_device *smmu; > > + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); > > + struct arm_smmu_group *smmu_group = arm_smmu_group_get(dev); > > + > > + if (!smmu_group) > > + return -ENOENT; > > + > > + /* Already attached to a different domain? */ > > + if (smmu_group->domain && smmu_group->domain != smmu_domain) > > + return -EEXIST; > > + > > + smmu = smmu_group->smmu; > > + mutex_lock(&smmu_domain->init_mutex); > > + > > + if (!smmu_domain->smmu) { > > + smmu_domain->smmu = smmu; > > + ret = arm_smmu_domain_finalise(domain); > > + if (ret) { > > + smmu_domain->smmu = NULL; > > + goto out_unlock; > > + } > > + } else if (smmu_domain->smmu != smmu) { > > + dev_err(dev, > > + "cannot attach to SMMU %s (upstream of %s)\n", > > + dev_name(smmu_domain->smmu->dev), > > + dev_name(smmu->dev)); > > + ret = -ENXIO; > > + goto out_unlock; > > + } > > This looks like all devices in a domain need to be behind the same SMMU > device, right? Yes, that's correct. This matches what we do for the arm-smmu driver already and is mainly brought about by the potential for hardware differences between different SMMU instances in the same SoC. > > + /* Page sizes */ > > + if (reg & IDR5_GRAN64K) > > + pgsize_bitmap |= SZ_64K | SZ_512M; > > + if (reg & IDR5_GRAN16K) > > + pgsize_bitmap |= SZ_16K | SZ_32M; > > + if (reg & IDR5_GRAN4K) > > + pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; > > + > > + arm_smmu_ops.pgsize_bitmap &= pgsize_bitmap; > > So this could effictivly lead to a zero pgsize_bitmap when there are > SMMUs in the system with support for different page sizes, no? Indeed, if there is no common page size then we end up not being able to support any. I tried to resolve this by moving the bitmap out of the iommu_ops and into the iommu_domain, but you weren't fond of that idea ;) Will ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-05-20 17:09 ` Will Deacon 0 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-20 17:09 UTC (permalink / raw) To: linux-arm-kernel On Tue, May 19, 2015 at 04:24:35PM +0100, Joerg Roedel wrote: > Hi Will, Hi Joerg, > the code looks good overall, I just have some questions below. Great, thanks for having a look. I'll still need to post a v2 to address some of the other comments I've had. > On Fri, May 08, 2015 at 07:00:45PM +0100, Will Deacon wrote: > > +static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) > > +{ > > + int ret = 0; > > + struct arm_smmu_device *smmu; > > + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); > > + struct arm_smmu_group *smmu_group = arm_smmu_group_get(dev); > > + > > + if (!smmu_group) > > + return -ENOENT; > > + > > + /* Already attached to a different domain? */ > > + if (smmu_group->domain && smmu_group->domain != smmu_domain) > > + return -EEXIST; > > + > > + smmu = smmu_group->smmu; > > + mutex_lock(&smmu_domain->init_mutex); > > + > > + if (!smmu_domain->smmu) { > > + smmu_domain->smmu = smmu; > > + ret = arm_smmu_domain_finalise(domain); > > + if (ret) { > > + smmu_domain->smmu = NULL; > > + goto out_unlock; > > + } > > + } else if (smmu_domain->smmu != smmu) { > > + dev_err(dev, > > + "cannot attach to SMMU %s (upstream of %s)\n", > > + dev_name(smmu_domain->smmu->dev), > > + dev_name(smmu->dev)); > > + ret = -ENXIO; > > + goto out_unlock; > > + } > > This looks like all devices in a domain need to be behind the same SMMU > device, right? Yes, that's correct. This matches what we do for the arm-smmu driver already and is mainly brought about by the potential for hardware differences between different SMMU instances in the same SoC. > > + /* Page sizes */ > > + if (reg & IDR5_GRAN64K) > > + pgsize_bitmap |= SZ_64K | SZ_512M; > > + if (reg & IDR5_GRAN16K) > > + pgsize_bitmap |= SZ_16K | SZ_32M; > > + if (reg & IDR5_GRAN4K) > > + pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; > > + > > + arm_smmu_ops.pgsize_bitmap &= pgsize_bitmap; > > So this could effictivly lead to a zero pgsize_bitmap when there are > SMMUs in the system with support for different page sizes, no? Indeed, if there is no common page size then we end up not being able to support any. I tried to resolve this by moving the bitmap out of the iommu_ops and into the iommu_domain, but you weren't fond of that idea ;) Will ^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <20150520170926.GI11498-5wv7dgnIgG8@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-05-20 17:09 ` Will Deacon @ 2015-05-29 6:43 ` Joerg Roedel -1 siblings, 0 replies; 40+ messages in thread From: Joerg Roedel @ 2015-05-29 6:43 UTC (permalink / raw) To: Will Deacon Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hi Will, On Wed, May 20, 2015 at 06:09:26PM +0100, Will Deacon wrote: > On Tue, May 19, 2015 at 04:24:35PM +0100, Joerg Roedel wrote: > > > + /* Page sizes */ > > > + if (reg & IDR5_GRAN64K) > > > + pgsize_bitmap |= SZ_64K | SZ_512M; > > > + if (reg & IDR5_GRAN16K) > > > + pgsize_bitmap |= SZ_16K | SZ_32M; > > > + if (reg & IDR5_GRAN4K) > > > + pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; > > > + > > > + arm_smmu_ops.pgsize_bitmap &= pgsize_bitmap; > > > > So this could effictivly lead to a zero pgsize_bitmap when there are > > SMMUs in the system with support for different page sizes, no? > > Indeed, if there is no common page size then we end up not being able to > support any. I tried to resolve this by moving the bitmap out of the > iommu_ops and into the iommu_domain, but you weren't fond of that idea ;) Well, what you could do (and what I think the core should do at some point) is to build the resulting page-size bitmap by taking the biggest minimum page-size from all iommus and OR the page-size bigger than that together. For a system with 3 SMMUs supporting all of the above pgsize_bitmaps the resulting bitmap would look like this: SZ_64K | SZ_32M | SZ_2M | SZ_512M | SZ_1G; With the biggest minimum page-size all of the bigger page-sizes can be emulated. But that is not necessary for this patch-set, just a suggestion for future work. Joerg ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-05-29 6:43 ` Joerg Roedel 0 siblings, 0 replies; 40+ messages in thread From: Joerg Roedel @ 2015-05-29 6:43 UTC (permalink / raw) To: linux-arm-kernel Hi Will, On Wed, May 20, 2015 at 06:09:26PM +0100, Will Deacon wrote: > On Tue, May 19, 2015 at 04:24:35PM +0100, Joerg Roedel wrote: > > > + /* Page sizes */ > > > + if (reg & IDR5_GRAN64K) > > > + pgsize_bitmap |= SZ_64K | SZ_512M; > > > + if (reg & IDR5_GRAN16K) > > > + pgsize_bitmap |= SZ_16K | SZ_32M; > > > + if (reg & IDR5_GRAN4K) > > > + pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; > > > + > > > + arm_smmu_ops.pgsize_bitmap &= pgsize_bitmap; > > > > So this could effictivly lead to a zero pgsize_bitmap when there are > > SMMUs in the system with support for different page sizes, no? > > Indeed, if there is no common page size then we end up not being able to > support any. I tried to resolve this by moving the bitmap out of the > iommu_ops and into the iommu_domain, but you weren't fond of that idea ;) Well, what you could do (and what I think the core should do at some point) is to build the resulting page-size bitmap by taking the biggest minimum page-size from all iommus and OR the page-size bigger than that together. For a system with 3 SMMUs supporting all of the above pgsize_bitmaps the resulting bitmap would look like this: SZ_64K | SZ_32M | SZ_2M | SZ_512M | SZ_1G; With the biggest minimum page-size all of the bigger page-sizes can be emulated. But that is not necessary for this patch-set, just a suggestion for future work. Joerg ^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <20150529064337.GN20611-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-05-29 6:43 ` Joerg Roedel @ 2015-05-29 11:35 ` Robin Murphy -1 siblings, 0 replies; 40+ messages in thread From: Robin Murphy @ 2015-05-29 11:35 UTC (permalink / raw) To: Joerg Roedel, Will Deacon Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hi Joerg, On 29/05/15 07:43, Joerg Roedel wrote: > Hi Will, > > On Wed, May 20, 2015 at 06:09:26PM +0100, Will Deacon wrote: >> On Tue, May 19, 2015 at 04:24:35PM +0100, Joerg Roedel wrote: >>>> + /* Page sizes */ >>>> + if (reg & IDR5_GRAN64K) >>>> + pgsize_bitmap |= SZ_64K | SZ_512M; >>>> + if (reg & IDR5_GRAN16K) >>>> + pgsize_bitmap |= SZ_16K | SZ_32M; >>>> + if (reg & IDR5_GRAN4K) >>>> + pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; >>>> + >>>> + arm_smmu_ops.pgsize_bitmap &= pgsize_bitmap; >>> >>> So this could effictivly lead to a zero pgsize_bitmap when there are >>> SMMUs in the system with support for different page sizes, no? >> >> Indeed, if there is no common page size then we end up not being able to >> support any. I tried to resolve this by moving the bitmap out of the >> iommu_ops and into the iommu_domain, but you weren't fond of that idea ;) > > Well, what you could do (and what I think the core should do at some > point) is to build the resulting page-size bitmap by taking the biggest > minimum page-size from all iommus and OR the page-size bigger than that > together. For a system with 3 SMMUs supporting all of the above > pgsize_bitmaps the resulting bitmap would look like this: > > SZ_64K | SZ_32M | SZ_2M | SZ_512M | SZ_1G; > > With the biggest minimum page-size all of the bigger page-sizes can be > emulated. But that is not necessary for this patch-set, just a > suggestion for future work. The trouble with this is, what about the CPU page size? Say you have some multimedia subsystem with its own integrated SMMU and for that they've only implemented the 16K granule scheme because it works best for the video hardware (and the GPU driver is making direct IOMMU API calls to remap carved-out RAM rather than using DMA-mapping). Now, the SMMU on the compute side of the SoC serving the general peripherals will be rendered useless by bumping the system-wide minimum page size up to 16K, because it then can't map that scatterlist of discontiguous 4K pages that the USB controller needs... I think this really represents another push to get away from (or at least around) the page-at-a-time paradigm - if the IOMMU API itself wasn't too fussed about page sizes and could let drivers handle the full map/unmap requests however they see fit, I think we could bypass a lot of these issues. We've already got the Intel IOMMU driver doing horrible hacks with the pgsize_bitmap to cheat the system, I'm sure we don't want to add any more of that. How about something like the below diff as a first step? Robin. ---8<--- From: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> Date: Fri, 29 May 2015 12:05:58 +0100 Subject: [PATCH] iommu: Allow drivers to support arbitrary map/unmap requests In certain situations, the page-at-a-time operation of the IOMMU API becomes problematic. For instance, IOMMUs which can support different page sizes per domain confound the use of a single pgsize_bitmap, and more generally it can be horribly inefficient for large operations (such as tearing down VFIO domains). To resolve this, allow drivers to expose their own low-level map/unmap handlers, in the manner of iommu_map_sg, which may bypass this restriction as necessary. The existing callbacks are renamed to better reflect their page-oriented nature. Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> --- drivers/iommu/amd_iommu.c | 4 ++-- drivers/iommu/arm-smmu.c | 4 ++-- drivers/iommu/exynos-iommu.c | 4 ++-- drivers/iommu/intel-iommu.c | 4 ++-- drivers/iommu/iommu.c | 14 ++++++++++---- drivers/iommu/ipmmu-vmsa.c | 4 ++-- drivers/iommu/msm_iommu.c | 4 ++-- drivers/iommu/omap-iommu.c | 4 ++-- drivers/iommu/rockchip-iommu.c | 4 ++-- drivers/iommu/shmobile-iommu.c | 4 ++-- drivers/iommu/tegra-gart.c | 4 ++-- drivers/iommu/tegra-smmu.c | 4 ++-- include/linux/iommu.h | 8 +++++++- 13 files changed, 39 insertions(+), 27 deletions(-) diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index e43d489..13e94ae 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -3418,8 +3418,8 @@ static const struct iommu_ops amd_iommu_ops = { .domain_free = amd_iommu_domain_free, .attach_dev = amd_iommu_attach_device, .detach_dev = amd_iommu_detach_device, - .map = amd_iommu_map, - .unmap = amd_iommu_unmap, + .map_page = amd_iommu_map, + .unmap_page = amd_iommu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = amd_iommu_iova_to_phys, .pgsize_bitmap = AMD_IOMMU_PGSIZES, diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 66a803b..427ae40 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1447,8 +1447,8 @@ static struct iommu_ops arm_smmu_ops = { .domain_free = arm_smmu_domain_free, .attach_dev = arm_smmu_attach_dev, .detach_dev = arm_smmu_detach_dev, - .map = arm_smmu_map, - .unmap = arm_smmu_unmap, + .map_page = arm_smmu_map, + .unmap_page = arm_smmu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = arm_smmu_iova_to_phys, .add_device = arm_smmu_add_device, diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 3e89850..9edf14a 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -1182,8 +1182,8 @@ static const struct iommu_ops exynos_iommu_ops = { .domain_free = exynos_iommu_domain_free, .attach_dev = exynos_iommu_attach_device, .detach_dev = exynos_iommu_detach_device, - .map = exynos_iommu_map, - .unmap = exynos_iommu_unmap, + .map_page = exynos_iommu_map, + .unmap_page = exynos_iommu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = exynos_iommu_iova_to_phys, .add_device = exynos_iommu_add_device, diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index 68d43be..67de73d 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c @@ -4597,8 +4597,8 @@ static const struct iommu_ops intel_iommu_ops = { .domain_free = intel_iommu_domain_free, .attach_dev = intel_iommu_attach_device, .detach_dev = intel_iommu_detach_device, - .map = intel_iommu_map, - .unmap = intel_iommu_unmap, + .map_page = intel_iommu_map, + .unmap_page = intel_iommu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = intel_iommu_iova_to_phys, .add_device = intel_iommu_add_device, diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index d4f527e..7312623 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1033,7 +1033,10 @@ int iommu_map(struct iommu_domain *domain, unsigned long iova, size_t orig_size = size; int ret = 0; - if (unlikely(domain->ops->map == NULL || + if (domain->ops->map) + return domain->ops->map(domain, iova, paddr, size, prot); + + if (unlikely(domain->ops->map_page == NULL || domain->ops->pgsize_bitmap == 0UL)) return -ENODEV; @@ -1062,7 +1065,7 @@ int iommu_map(struct iommu_domain *domain, unsigned long iova, pr_debug("mapping: iova 0x%lx pa %pa pgsize 0x%zx\n", iova, &paddr, pgsize); - ret = domain->ops->map(domain, iova, paddr, pgsize, prot); + ret = domain->ops->map_page(domain, iova, paddr, pgsize, prot); if (ret) break; @@ -1087,7 +1090,10 @@ size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size) unsigned int min_pagesz; unsigned long orig_iova = iova; - if (unlikely(domain->ops->unmap == NULL || + if (domain->ops->unmap) + return domain->ops->unmap(domain, iova, size); + + if (unlikely(domain->ops->unmap_page == NULL || domain->ops->pgsize_bitmap == 0UL)) return -ENODEV; @@ -1117,7 +1123,7 @@ size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size) while (unmapped < size) { size_t pgsize = iommu_pgsize(domain, iova, size - unmapped); - unmapped_page = domain->ops->unmap(domain, iova, pgsize); + unmapped_page = domain->ops->unmap_page(domain, iova, pgsize); if (!unmapped_page) break; diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index 1a67c53..1db3486 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -746,8 +746,8 @@ static const struct iommu_ops ipmmu_ops = { .domain_free = ipmmu_domain_free, .attach_dev = ipmmu_attach_device, .detach_dev = ipmmu_detach_device, - .map = ipmmu_map, - .unmap = ipmmu_unmap, + .map_page = ipmmu_map, + .unmap_page = ipmmu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = ipmmu_iova_to_phys, .add_device = ipmmu_add_device, diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 15a2063..ea40c86 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -677,8 +677,8 @@ static const struct iommu_ops msm_iommu_ops = { .domain_free = msm_iommu_domain_free, .attach_dev = msm_iommu_attach_dev, .detach_dev = msm_iommu_detach_dev, - .map = msm_iommu_map, - .unmap = msm_iommu_unmap, + .map_page = msm_iommu_map, + .unmap_page = msm_iommu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = msm_iommu_iova_to_phys, .pgsize_bitmap = MSM_IOMMU_PGSIZES, diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index a22c33d..784d29c 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1371,8 +1371,8 @@ static const struct iommu_ops omap_iommu_ops = { .domain_free = omap_iommu_domain_free, .attach_dev = omap_iommu_attach_dev, .detach_dev = omap_iommu_detach_dev, - .map = omap_iommu_map, - .unmap = omap_iommu_unmap, + .map_page = omap_iommu_map, + .unmap_page = omap_iommu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = omap_iommu_iova_to_phys, .add_device = omap_iommu_add_device, diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index cab2145..b10d5b2 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -964,8 +964,8 @@ static const struct iommu_ops rk_iommu_ops = { .domain_free = rk_iommu_domain_free, .attach_dev = rk_iommu_attach_device, .detach_dev = rk_iommu_detach_device, - .map = rk_iommu_map, - .unmap = rk_iommu_unmap, + .map_page = rk_iommu_map, + .unmap_page = rk_iommu_unmap, .add_device = rk_iommu_add_device, .remove_device = rk_iommu_remove_device, .iova_to_phys = rk_iommu_iova_to_phys, diff --git a/drivers/iommu/shmobile-iommu.c b/drivers/iommu/shmobile-iommu.c index a028751..f587313 100644 --- a/drivers/iommu/shmobile-iommu.c +++ b/drivers/iommu/shmobile-iommu.c @@ -366,8 +366,8 @@ static const struct iommu_ops shmobile_iommu_ops = { .domain_free = shmobile_iommu_domain_free, .attach_dev = shmobile_iommu_attach_device, .detach_dev = shmobile_iommu_detach_device, - .map = shmobile_iommu_map, - .unmap = shmobile_iommu_unmap, + .map_page = shmobile_iommu_map, + .unmap_page = shmobile_iommu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = shmobile_iommu_iova_to_phys, .add_device = shmobile_iommu_add_device, diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c index 37e708f..8e4d6f1 100644 --- a/drivers/iommu/tegra-gart.c +++ b/drivers/iommu/tegra-gart.c @@ -340,9 +340,9 @@ static const struct iommu_ops gart_iommu_ops = { .domain_free = gart_iommu_domain_free, .attach_dev = gart_iommu_attach_dev, .detach_dev = gart_iommu_detach_dev, - .map = gart_iommu_map, + .map_page = gart_iommu_map, .map_sg = default_iommu_map_sg, - .unmap = gart_iommu_unmap, + .unmap_page = gart_iommu_unmap, .iova_to_phys = gart_iommu_iova_to_phys, .pgsize_bitmap = GART_IOMMU_PGSIZES, }; diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index c845d99..38915fc 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -650,8 +650,8 @@ static const struct iommu_ops tegra_smmu_ops = { .detach_dev = tegra_smmu_detach_dev, .add_device = tegra_smmu_add_device, .remove_device = tegra_smmu_remove_device, - .map = tegra_smmu_map, - .unmap = tegra_smmu_unmap, + .map_page = tegra_smmu_map, + .unmap_page = tegra_smmu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = tegra_smmu_iova_to_phys, diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 0546b87..5857bd6 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -124,6 +124,8 @@ enum iommu_attr { * @detach_dev: detach device from an iommu domain * @map: map a physically contiguous memory region to an iommu domain * @unmap: unmap a physically contiguous memory region from an iommu domain + * @map_page: map a physical region corresponding to a single iommu page + * @unmap_page: unmap a physical region corresponding to a single iommu page * @map_sg: map a scatter-gather list of physically contiguous memory chunks * to an iommu domain * @iova_to_phys: translate iova to physical address @@ -147,7 +149,11 @@ struct iommu_ops { int (*map)(struct iommu_domain *domain, unsigned long iova, phys_addr_t paddr, size_t size, int prot); size_t (*unmap)(struct iommu_domain *domain, unsigned long iova, - size_t size); + size_t size); + int (*map_page)(struct iommu_domain *domain, unsigned long iova, + phys_addr_t paddr, size_t size, int prot); + size_t (*unmap_page)(struct iommu_domain *domain, unsigned long iova, + size_t size); size_t (*map_sg)(struct iommu_domain *domain, unsigned long iova, struct scatterlist *sg, unsigned int nents, int prot); phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova); ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-05-29 11:35 ` Robin Murphy 0 siblings, 0 replies; 40+ messages in thread From: Robin Murphy @ 2015-05-29 11:35 UTC (permalink / raw) To: linux-arm-kernel Hi Joerg, On 29/05/15 07:43, Joerg Roedel wrote: > Hi Will, > > On Wed, May 20, 2015 at 06:09:26PM +0100, Will Deacon wrote: >> On Tue, May 19, 2015 at 04:24:35PM +0100, Joerg Roedel wrote: >>>> + /* Page sizes */ >>>> + if (reg & IDR5_GRAN64K) >>>> + pgsize_bitmap |= SZ_64K | SZ_512M; >>>> + if (reg & IDR5_GRAN16K) >>>> + pgsize_bitmap |= SZ_16K | SZ_32M; >>>> + if (reg & IDR5_GRAN4K) >>>> + pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; >>>> + >>>> + arm_smmu_ops.pgsize_bitmap &= pgsize_bitmap; >>> >>> So this could effictivly lead to a zero pgsize_bitmap when there are >>> SMMUs in the system with support for different page sizes, no? >> >> Indeed, if there is no common page size then we end up not being able to >> support any. I tried to resolve this by moving the bitmap out of the >> iommu_ops and into the iommu_domain, but you weren't fond of that idea ;) > > Well, what you could do (and what I think the core should do at some > point) is to build the resulting page-size bitmap by taking the biggest > minimum page-size from all iommus and OR the page-size bigger than that > together. For a system with 3 SMMUs supporting all of the above > pgsize_bitmaps the resulting bitmap would look like this: > > SZ_64K | SZ_32M | SZ_2M | SZ_512M | SZ_1G; > > With the biggest minimum page-size all of the bigger page-sizes can be > emulated. But that is not necessary for this patch-set, just a > suggestion for future work. The trouble with this is, what about the CPU page size? Say you have some multimedia subsystem with its own integrated SMMU and for that they've only implemented the 16K granule scheme because it works best for the video hardware (and the GPU driver is making direct IOMMU API calls to remap carved-out RAM rather than using DMA-mapping). Now, the SMMU on the compute side of the SoC serving the general peripherals will be rendered useless by bumping the system-wide minimum page size up to 16K, because it then can't map that scatterlist of discontiguous 4K pages that the USB controller needs... I think this really represents another push to get away from (or at least around) the page-at-a-time paradigm - if the IOMMU API itself wasn't too fussed about page sizes and could let drivers handle the full map/unmap requests however they see fit, I think we could bypass a lot of these issues. We've already got the Intel IOMMU driver doing horrible hacks with the pgsize_bitmap to cheat the system, I'm sure we don't want to add any more of that. How about something like the below diff as a first step? Robin. ---8<--- From: Robin Murphy <robin.murphy@arm.com> Date: Fri, 29 May 2015 12:05:58 +0100 Subject: [PATCH] iommu: Allow drivers to support arbitrary map/unmap requests In certain situations, the page-at-a-time operation of the IOMMU API becomes problematic. For instance, IOMMUs which can support different page sizes per domain confound the use of a single pgsize_bitmap, and more generally it can be horribly inefficient for large operations (such as tearing down VFIO domains). To resolve this, allow drivers to expose their own low-level map/unmap handlers, in the manner of iommu_map_sg, which may bypass this restriction as necessary. The existing callbacks are renamed to better reflect their page-oriented nature. Signed-off-by: Robin Murphy <robin.murphy@arm.com> --- drivers/iommu/amd_iommu.c | 4 ++-- drivers/iommu/arm-smmu.c | 4 ++-- drivers/iommu/exynos-iommu.c | 4 ++-- drivers/iommu/intel-iommu.c | 4 ++-- drivers/iommu/iommu.c | 14 ++++++++++---- drivers/iommu/ipmmu-vmsa.c | 4 ++-- drivers/iommu/msm_iommu.c | 4 ++-- drivers/iommu/omap-iommu.c | 4 ++-- drivers/iommu/rockchip-iommu.c | 4 ++-- drivers/iommu/shmobile-iommu.c | 4 ++-- drivers/iommu/tegra-gart.c | 4 ++-- drivers/iommu/tegra-smmu.c | 4 ++-- include/linux/iommu.h | 8 +++++++- 13 files changed, 39 insertions(+), 27 deletions(-) diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index e43d489..13e94ae 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -3418,8 +3418,8 @@ static const struct iommu_ops amd_iommu_ops = { .domain_free = amd_iommu_domain_free, .attach_dev = amd_iommu_attach_device, .detach_dev = amd_iommu_detach_device, - .map = amd_iommu_map, - .unmap = amd_iommu_unmap, + .map_page = amd_iommu_map, + .unmap_page = amd_iommu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = amd_iommu_iova_to_phys, .pgsize_bitmap = AMD_IOMMU_PGSIZES, diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 66a803b..427ae40 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1447,8 +1447,8 @@ static struct iommu_ops arm_smmu_ops = { .domain_free = arm_smmu_domain_free, .attach_dev = arm_smmu_attach_dev, .detach_dev = arm_smmu_detach_dev, - .map = arm_smmu_map, - .unmap = arm_smmu_unmap, + .map_page = arm_smmu_map, + .unmap_page = arm_smmu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = arm_smmu_iova_to_phys, .add_device = arm_smmu_add_device, diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 3e89850..9edf14a 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -1182,8 +1182,8 @@ static const struct iommu_ops exynos_iommu_ops = { .domain_free = exynos_iommu_domain_free, .attach_dev = exynos_iommu_attach_device, .detach_dev = exynos_iommu_detach_device, - .map = exynos_iommu_map, - .unmap = exynos_iommu_unmap, + .map_page = exynos_iommu_map, + .unmap_page = exynos_iommu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = exynos_iommu_iova_to_phys, .add_device = exynos_iommu_add_device, diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index 68d43be..67de73d 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c @@ -4597,8 +4597,8 @@ static const struct iommu_ops intel_iommu_ops = { .domain_free = intel_iommu_domain_free, .attach_dev = intel_iommu_attach_device, .detach_dev = intel_iommu_detach_device, - .map = intel_iommu_map, - .unmap = intel_iommu_unmap, + .map_page = intel_iommu_map, + .unmap_page = intel_iommu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = intel_iommu_iova_to_phys, .add_device = intel_iommu_add_device, diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index d4f527e..7312623 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1033,7 +1033,10 @@ int iommu_map(struct iommu_domain *domain, unsigned long iova, size_t orig_size = size; int ret = 0; - if (unlikely(domain->ops->map == NULL || + if (domain->ops->map) + return domain->ops->map(domain, iova, paddr, size, prot); + + if (unlikely(domain->ops->map_page == NULL || domain->ops->pgsize_bitmap == 0UL)) return -ENODEV; @@ -1062,7 +1065,7 @@ int iommu_map(struct iommu_domain *domain, unsigned long iova, pr_debug("mapping: iova 0x%lx pa %pa pgsize 0x%zx\n", iova, &paddr, pgsize); - ret = domain->ops->map(domain, iova, paddr, pgsize, prot); + ret = domain->ops->map_page(domain, iova, paddr, pgsize, prot); if (ret) break; @@ -1087,7 +1090,10 @@ size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size) unsigned int min_pagesz; unsigned long orig_iova = iova; - if (unlikely(domain->ops->unmap == NULL || + if (domain->ops->unmap) + return domain->ops->unmap(domain, iova, size); + + if (unlikely(domain->ops->unmap_page == NULL || domain->ops->pgsize_bitmap == 0UL)) return -ENODEV; @@ -1117,7 +1123,7 @@ size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size) while (unmapped < size) { size_t pgsize = iommu_pgsize(domain, iova, size - unmapped); - unmapped_page = domain->ops->unmap(domain, iova, pgsize); + unmapped_page = domain->ops->unmap_page(domain, iova, pgsize); if (!unmapped_page) break; diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index 1a67c53..1db3486 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -746,8 +746,8 @@ static const struct iommu_ops ipmmu_ops = { .domain_free = ipmmu_domain_free, .attach_dev = ipmmu_attach_device, .detach_dev = ipmmu_detach_device, - .map = ipmmu_map, - .unmap = ipmmu_unmap, + .map_page = ipmmu_map, + .unmap_page = ipmmu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = ipmmu_iova_to_phys, .add_device = ipmmu_add_device, diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 15a2063..ea40c86 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -677,8 +677,8 @@ static const struct iommu_ops msm_iommu_ops = { .domain_free = msm_iommu_domain_free, .attach_dev = msm_iommu_attach_dev, .detach_dev = msm_iommu_detach_dev, - .map = msm_iommu_map, - .unmap = msm_iommu_unmap, + .map_page = msm_iommu_map, + .unmap_page = msm_iommu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = msm_iommu_iova_to_phys, .pgsize_bitmap = MSM_IOMMU_PGSIZES, diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index a22c33d..784d29c 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1371,8 +1371,8 @@ static const struct iommu_ops omap_iommu_ops = { .domain_free = omap_iommu_domain_free, .attach_dev = omap_iommu_attach_dev, .detach_dev = omap_iommu_detach_dev, - .map = omap_iommu_map, - .unmap = omap_iommu_unmap, + .map_page = omap_iommu_map, + .unmap_page = omap_iommu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = omap_iommu_iova_to_phys, .add_device = omap_iommu_add_device, diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index cab2145..b10d5b2 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -964,8 +964,8 @@ static const struct iommu_ops rk_iommu_ops = { .domain_free = rk_iommu_domain_free, .attach_dev = rk_iommu_attach_device, .detach_dev = rk_iommu_detach_device, - .map = rk_iommu_map, - .unmap = rk_iommu_unmap, + .map_page = rk_iommu_map, + .unmap_page = rk_iommu_unmap, .add_device = rk_iommu_add_device, .remove_device = rk_iommu_remove_device, .iova_to_phys = rk_iommu_iova_to_phys, diff --git a/drivers/iommu/shmobile-iommu.c b/drivers/iommu/shmobile-iommu.c index a028751..f587313 100644 --- a/drivers/iommu/shmobile-iommu.c +++ b/drivers/iommu/shmobile-iommu.c @@ -366,8 +366,8 @@ static const struct iommu_ops shmobile_iommu_ops = { .domain_free = shmobile_iommu_domain_free, .attach_dev = shmobile_iommu_attach_device, .detach_dev = shmobile_iommu_detach_device, - .map = shmobile_iommu_map, - .unmap = shmobile_iommu_unmap, + .map_page = shmobile_iommu_map, + .unmap_page = shmobile_iommu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = shmobile_iommu_iova_to_phys, .add_device = shmobile_iommu_add_device, diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c index 37e708f..8e4d6f1 100644 --- a/drivers/iommu/tegra-gart.c +++ b/drivers/iommu/tegra-gart.c @@ -340,9 +340,9 @@ static const struct iommu_ops gart_iommu_ops = { .domain_free = gart_iommu_domain_free, .attach_dev = gart_iommu_attach_dev, .detach_dev = gart_iommu_detach_dev, - .map = gart_iommu_map, + .map_page = gart_iommu_map, .map_sg = default_iommu_map_sg, - .unmap = gart_iommu_unmap, + .unmap_page = gart_iommu_unmap, .iova_to_phys = gart_iommu_iova_to_phys, .pgsize_bitmap = GART_IOMMU_PGSIZES, }; diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index c845d99..38915fc 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -650,8 +650,8 @@ static const struct iommu_ops tegra_smmu_ops = { .detach_dev = tegra_smmu_detach_dev, .add_device = tegra_smmu_add_device, .remove_device = tegra_smmu_remove_device, - .map = tegra_smmu_map, - .unmap = tegra_smmu_unmap, + .map_page = tegra_smmu_map, + .unmap_page = tegra_smmu_unmap, .map_sg = default_iommu_map_sg, .iova_to_phys = tegra_smmu_iova_to_phys, diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 0546b87..5857bd6 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -124,6 +124,8 @@ enum iommu_attr { * @detach_dev: detach device from an iommu domain * @map: map a physically contiguous memory region to an iommu domain * @unmap: unmap a physically contiguous memory region from an iommu domain + * @map_page: map a physical region corresponding to a single iommu page + * @unmap_page: unmap a physical region corresponding to a single iommu page * @map_sg: map a scatter-gather list of physically contiguous memory chunks * to an iommu domain * @iova_to_phys: translate iova to physical address @@ -147,7 +149,11 @@ struct iommu_ops { int (*map)(struct iommu_domain *domain, unsigned long iova, phys_addr_t paddr, size_t size, int prot); size_t (*unmap)(struct iommu_domain *domain, unsigned long iova, - size_t size); + size_t size); + int (*map_page)(struct iommu_domain *domain, unsigned long iova, + phys_addr_t paddr, size_t size, int prot); + size_t (*unmap_page)(struct iommu_domain *domain, unsigned long iova, + size_t size); size_t (*map_sg)(struct iommu_domain *domain, unsigned long iova, struct scatterlist *sg, unsigned int nents, int prot); phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova); ^ permalink raw reply related [flat|nested] 40+ messages in thread
[parent not found: <55684F1C.3050702-5wv7dgnIgG8@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-05-29 11:35 ` Robin Murphy @ 2015-05-29 14:40 ` Joerg Roedel -1 siblings, 0 replies; 40+ messages in thread From: Joerg Roedel @ 2015-05-29 14:40 UTC (permalink / raw) To: Robin Murphy Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Will Deacon, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On Fri, May 29, 2015 at 12:35:56PM +0100, Robin Murphy wrote: > The trouble with this is, what about the CPU page size? Say you have > some multimedia subsystem with its own integrated SMMU and for that > they've only implemented the 16K granule scheme because it works > best for the video hardware (and the GPU driver is making direct > IOMMU API calls to remap carved-out RAM rather than using > DMA-mapping). Now, the SMMU on the compute side of the SoC serving > the general peripherals will be rendered useless by bumping the > system-wide minimum page size up to 16K, because it then can't map > that scatterlist of discontiguous 4K pages that the USB controller > needs... > > I think this really represents another push to get away from (or at > least around) the page-at-a-time paradigm - if the IOMMU API itself > wasn't too fussed about page sizes and could let drivers handle the > full map/unmap requests however they see fit, I think we could > bypass a lot of these issues. We've already got the Intel IOMMU > driver doing horrible hacks with the pgsize_bitmap to cheat the > system, I'm sure we don't want to add any more of that. How about > something like the below diff as a first step? Moving functionality out of the iommu core code into the drivers is the wrong direction imo. It is better to solve it with something like struct iommu_domain *iommu_domain_alloc_for_group(struct iommu_group *group); Which gets us a domain that can only be assigned to that particular group. Since there is a clear one-to-many relationship between a hardware iommu and the groups of devices behind it, we could propagate the pgsize_bitmap from the iommu to the group and then to the domain. Domains allocated via iommu_domain_alloc() would get the merged pgsize_bitmap like I described in my previous mail. But to make this happen we need a representation of single hardware iommu instances in the iommu core first. Joerg ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-05-29 14:40 ` Joerg Roedel 0 siblings, 0 replies; 40+ messages in thread From: Joerg Roedel @ 2015-05-29 14:40 UTC (permalink / raw) To: linux-arm-kernel On Fri, May 29, 2015 at 12:35:56PM +0100, Robin Murphy wrote: > The trouble with this is, what about the CPU page size? Say you have > some multimedia subsystem with its own integrated SMMU and for that > they've only implemented the 16K granule scheme because it works > best for the video hardware (and the GPU driver is making direct > IOMMU API calls to remap carved-out RAM rather than using > DMA-mapping). Now, the SMMU on the compute side of the SoC serving > the general peripherals will be rendered useless by bumping the > system-wide minimum page size up to 16K, because it then can't map > that scatterlist of discontiguous 4K pages that the USB controller > needs... > > I think this really represents another push to get away from (or at > least around) the page-at-a-time paradigm - if the IOMMU API itself > wasn't too fussed about page sizes and could let drivers handle the > full map/unmap requests however they see fit, I think we could > bypass a lot of these issues. We've already got the Intel IOMMU > driver doing horrible hacks with the pgsize_bitmap to cheat the > system, I'm sure we don't want to add any more of that. How about > something like the below diff as a first step? Moving functionality out of the iommu core code into the drivers is the wrong direction imo. It is better to solve it with something like struct iommu_domain *iommu_domain_alloc_for_group(struct iommu_group *group); Which gets us a domain that can only be assigned to that particular group. Since there is a clear one-to-many relationship between a hardware iommu and the groups of devices behind it, we could propagate the pgsize_bitmap from the iommu to the group and then to the domain. Domains allocated via iommu_domain_alloc() would get the merged pgsize_bitmap like I described in my previous mail. But to make this happen we need a representation of single hardware iommu instances in the iommu core first. Joerg ^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <20150529144043.GA20384-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-05-29 14:40 ` Joerg Roedel @ 2015-06-01 9:40 ` Will Deacon -1 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-06-01 9:40 UTC (permalink / raw) To: Joerg Roedel Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hi Joerg, On Fri, May 29, 2015 at 03:40:43PM +0100, Joerg Roedel wrote: > On Fri, May 29, 2015 at 12:35:56PM +0100, Robin Murphy wrote: > > The trouble with this is, what about the CPU page size? Say you have > > some multimedia subsystem with its own integrated SMMU and for that > > they've only implemented the 16K granule scheme because it works > > best for the video hardware (and the GPU driver is making direct > > IOMMU API calls to remap carved-out RAM rather than using > > DMA-mapping). Now, the SMMU on the compute side of the SoC serving > > the general peripherals will be rendered useless by bumping the > > system-wide minimum page size up to 16K, because it then can't map > > that scatterlist of discontiguous 4K pages that the USB controller > > needs... > > > > I think this really represents another push to get away from (or at > > least around) the page-at-a-time paradigm - if the IOMMU API itself > > wasn't too fussed about page sizes and could let drivers handle the > > full map/unmap requests however they see fit, I think we could > > bypass a lot of these issues. We've already got the Intel IOMMU > > driver doing horrible hacks with the pgsize_bitmap to cheat the > > system, I'm sure we don't want to add any more of that. How about > > something like the below diff as a first step? > > Moving functionality out of the iommu core code into the drivers is the > wrong direction imo. It is better to solve it with something like > > struct iommu_domain *iommu_domain_alloc_for_group(struct iommu_group *group); > > Which gets us a domain that can only be assigned to that particular > group. Since there is a clear one-to-many relationship between a > hardware iommu and the groups of devices behind it, we could propagate > the pgsize_bitmap from the iommu to the group and then to the domain. > > Domains allocated via iommu_domain_alloc() would get the merged > pgsize_bitmap like I described in my previous mail. > > But to make this happen we need a representation of single hardware > iommu instances in the iommu core first. I like this proposal. The only remaining part is that the pgsize bitmap inherited by the domain can only truly be finalised once the page table is allocated, which in turn can only happen once we've identified the IOMMU instance. In the case of iommu_domain_alloc_for_group, that's nice and straightforward (i.e. as part of the call) but for the default iommu_domain_alloc() case, we'd have to continue postponing things to ->attach time before we could provide a reliable pgsize_bitmap. This is to handle the case where an SMMU may be able to support only a subset of the pgsize_bitmap on a per-domain basis. In which situation do you think the merged pgsize_bitmap would get used? The only place I can think of is if we're trying to call iommu_map on a domain with no devices attached. However, if that domain was created using iommu_domain_alloc() then the pgsize_bitmap is the least of our worries -- we don't even know the page table format! Will ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-06-01 9:40 ` Will Deacon 0 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-06-01 9:40 UTC (permalink / raw) To: linux-arm-kernel Hi Joerg, On Fri, May 29, 2015 at 03:40:43PM +0100, Joerg Roedel wrote: > On Fri, May 29, 2015 at 12:35:56PM +0100, Robin Murphy wrote: > > The trouble with this is, what about the CPU page size? Say you have > > some multimedia subsystem with its own integrated SMMU and for that > > they've only implemented the 16K granule scheme because it works > > best for the video hardware (and the GPU driver is making direct > > IOMMU API calls to remap carved-out RAM rather than using > > DMA-mapping). Now, the SMMU on the compute side of the SoC serving > > the general peripherals will be rendered useless by bumping the > > system-wide minimum page size up to 16K, because it then can't map > > that scatterlist of discontiguous 4K pages that the USB controller > > needs... > > > > I think this really represents another push to get away from (or at > > least around) the page-at-a-time paradigm - if the IOMMU API itself > > wasn't too fussed about page sizes and could let drivers handle the > > full map/unmap requests however they see fit, I think we could > > bypass a lot of these issues. We've already got the Intel IOMMU > > driver doing horrible hacks with the pgsize_bitmap to cheat the > > system, I'm sure we don't want to add any more of that. How about > > something like the below diff as a first step? > > Moving functionality out of the iommu core code into the drivers is the > wrong direction imo. It is better to solve it with something like > > struct iommu_domain *iommu_domain_alloc_for_group(struct iommu_group *group); > > Which gets us a domain that can only be assigned to that particular > group. Since there is a clear one-to-many relationship between a > hardware iommu and the groups of devices behind it, we could propagate > the pgsize_bitmap from the iommu to the group and then to the domain. > > Domains allocated via iommu_domain_alloc() would get the merged > pgsize_bitmap like I described in my previous mail. > > But to make this happen we need a representation of single hardware > iommu instances in the iommu core first. I like this proposal. The only remaining part is that the pgsize bitmap inherited by the domain can only truly be finalised once the page table is allocated, which in turn can only happen once we've identified the IOMMU instance. In the case of iommu_domain_alloc_for_group, that's nice and straightforward (i.e. as part of the call) but for the default iommu_domain_alloc() case, we'd have to continue postponing things to ->attach time before we could provide a reliable pgsize_bitmap. This is to handle the case where an SMMU may be able to support only a subset of the pgsize_bitmap on a per-domain basis. In which situation do you think the merged pgsize_bitmap would get used? The only place I can think of is if we're trying to call iommu_map on a domain with no devices attached. However, if that domain was created using iommu_domain_alloc() then the pgsize_bitmap is the least of our worries -- we don't even know the page table format! Will ^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <20150601094014.GC1641-5wv7dgnIgG8@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-06-01 9:40 ` Will Deacon @ 2015-06-02 7:39 ` Joerg Roedel -1 siblings, 0 replies; 40+ messages in thread From: Joerg Roedel @ 2015-06-02 7:39 UTC (permalink / raw) To: Will Deacon Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hi Will, On Mon, Jun 01, 2015 at 10:40:14AM +0100, Will Deacon wrote: > I like this proposal. The only remaining part is that the pgsize bitmap > inherited by the domain can only truly be finalised once the page table > is allocated, which in turn can only happen once we've identified the > IOMMU instance. We know the IOMMU instance for domains allocted with iommu_domain_alloc_for_group because every group is behind a single IOMMU instance. So the page-table can be allocated at domain creation time and mappings can be created before the group itself is attached. > In the case of iommu_domain_alloc_for_group, that's nice and > straightforward (i.e. as part of the call) but for the default > iommu_domain_alloc() case, we'd have to continue postponing things to > ->attach time before we could provide a reliable pgsize_bitmap. This is > to handle the case where an SMMU may be able to support only a subset of > the pgsize_bitmap on a per-domain basis. I don't think we need to postpone anything. Domains returned by iommu_domain_alloc() need to work for all groups. If there are multiple IOMMUs in the system with different capabilities/page-table formats the IOMMU core needs to build multiple page-tables for that domain. VFIO already does that as a workaround of how things are done currently, but I really think this should be done in the IOMMU core code. > In which situation do you think the merged pgsize_bitmap would get used? > The only place I can think of is if we're trying to call iommu_map on a > domain with no devices attached. However, if that domain was created > using iommu_domain_alloc() then the pgsize_bitmap is the least of our > worries -- we don't even know the page table format! The first usecase for the merged pgsize_bitmap that comes to mind is to determine the minimum page-size that can be used for a domain. In the SMMUv3 case when there are IOMMUs with different minium page-sizes in one system, this would be the biggest minimum page-size of all IOMMUs. Probably there are other uses for that bitmap that show up at implementation time. Joerg ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-06-02 7:39 ` Joerg Roedel 0 siblings, 0 replies; 40+ messages in thread From: Joerg Roedel @ 2015-06-02 7:39 UTC (permalink / raw) To: linux-arm-kernel Hi Will, On Mon, Jun 01, 2015 at 10:40:14AM +0100, Will Deacon wrote: > I like this proposal. The only remaining part is that the pgsize bitmap > inherited by the domain can only truly be finalised once the page table > is allocated, which in turn can only happen once we've identified the > IOMMU instance. We know the IOMMU instance for domains allocted with iommu_domain_alloc_for_group because every group is behind a single IOMMU instance. So the page-table can be allocated at domain creation time and mappings can be created before the group itself is attached. > In the case of iommu_domain_alloc_for_group, that's nice and > straightforward (i.e. as part of the call) but for the default > iommu_domain_alloc() case, we'd have to continue postponing things to > ->attach time before we could provide a reliable pgsize_bitmap. This is > to handle the case where an SMMU may be able to support only a subset of > the pgsize_bitmap on a per-domain basis. I don't think we need to postpone anything. Domains returned by iommu_domain_alloc() need to work for all groups. If there are multiple IOMMUs in the system with different capabilities/page-table formats the IOMMU core needs to build multiple page-tables for that domain. VFIO already does that as a workaround of how things are done currently, but I really think this should be done in the IOMMU core code. > In which situation do you think the merged pgsize_bitmap would get used? > The only place I can think of is if we're trying to call iommu_map on a > domain with no devices attached. However, if that domain was created > using iommu_domain_alloc() then the pgsize_bitmap is the least of our > worries -- we don't even know the page table format! The first usecase for the merged pgsize_bitmap that comes to mind is to determine the minimum page-size that can be used for a domain. In the SMMUv3 case when there are IOMMUs with different minium page-sizes in one system, this would be the biggest minimum page-size of all IOMMUs. Probably there are other uses for that bitmap that show up at implementation time. Joerg ^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <20150602073956.GG20384-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-06-02 7:39 ` Joerg Roedel @ 2015-06-02 9:47 ` Will Deacon -1 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-06-02 9:47 UTC (permalink / raw) To: Joerg Roedel Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On Tue, Jun 02, 2015 at 08:39:56AM +0100, Joerg Roedel wrote: > On Mon, Jun 01, 2015 at 10:40:14AM +0100, Will Deacon wrote: > > I like this proposal. The only remaining part is that the pgsize bitmap > > inherited by the domain can only truly be finalised once the page table > > is allocated, which in turn can only happen once we've identified the > > IOMMU instance. > > We know the IOMMU instance for domains allocted with > iommu_domain_alloc_for_group because every group is behind a single > IOMMU instance. So the page-table can be allocated at domain creation > time and mappings can be created before the group itself is attached. Indeed -- I think this form of allocation makes a lot of sense. > > In the case of iommu_domain_alloc_for_group, that's nice and > > straightforward (i.e. as part of the call) but for the default > > iommu_domain_alloc() case, we'd have to continue postponing things to > > ->attach time before we could provide a reliable pgsize_bitmap. This is > > to handle the case where an SMMU may be able to support only a subset of > > the pgsize_bitmap on a per-domain basis. > > I don't think we need to postpone anything. Domains returned by > iommu_domain_alloc() need to work for all groups. If there are multiple > IOMMUs in the system with different capabilities/page-table formats the > IOMMU core needs to build multiple page-tables for that domain. I really don't think that's feasible. We support an awful lot of combinations that affect the page table format on ARM: there are 5 different formats, each supporting different translation regimes (sets of page size) and each of those needs configuring for input/output address sizes to compute the number of levels. You could easily end up with over 20 page tables and their corresponding sets of control register values. Given that we only install one page table in the end, I'm struggling to see the issue with postponing its allocation until we've figured out the IOMMU instance thanks to a device attach. > VFIO already does that as a workaround of how things are done currently, > but I really think this should be done in the IOMMU core code. Postponing page table creation to ->attach works fine with VFIO today. AFAICT, it never tries to map pages for an empty domain and therefore the IOMMU instance is always known by the IOMMU driver at ->map time. > > In which situation do you think the merged pgsize_bitmap would get used? > > The only place I can think of is if we're trying to call iommu_map on a > > domain with no devices attached. However, if that domain was created > > using iommu_domain_alloc() then the pgsize_bitmap is the least of our > > worries -- we don't even know the page table format! > > The first usecase for the merged pgsize_bitmap that comes to mind is to > determine the minimum page-size that can be used for a domain. In the > SMMUv3 case when there are IOMMUs with different minium page-sizes in one > system, this would be the biggest minimum page-size of all IOMMUs. Understood, but I'm trying to understand why you'd want to know that for an empty (no devices attached) domain. I don't think we currently have any use-cases for that and it's really not a practical thing to support. Will ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-06-02 9:47 ` Will Deacon 0 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-06-02 9:47 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jun 02, 2015 at 08:39:56AM +0100, Joerg Roedel wrote: > On Mon, Jun 01, 2015 at 10:40:14AM +0100, Will Deacon wrote: > > I like this proposal. The only remaining part is that the pgsize bitmap > > inherited by the domain can only truly be finalised once the page table > > is allocated, which in turn can only happen once we've identified the > > IOMMU instance. > > We know the IOMMU instance for domains allocted with > iommu_domain_alloc_for_group because every group is behind a single > IOMMU instance. So the page-table can be allocated at domain creation > time and mappings can be created before the group itself is attached. Indeed -- I think this form of allocation makes a lot of sense. > > In the case of iommu_domain_alloc_for_group, that's nice and > > straightforward (i.e. as part of the call) but for the default > > iommu_domain_alloc() case, we'd have to continue postponing things to > > ->attach time before we could provide a reliable pgsize_bitmap. This is > > to handle the case where an SMMU may be able to support only a subset of > > the pgsize_bitmap on a per-domain basis. > > I don't think we need to postpone anything. Domains returned by > iommu_domain_alloc() need to work for all groups. If there are multiple > IOMMUs in the system with different capabilities/page-table formats the > IOMMU core needs to build multiple page-tables for that domain. I really don't think that's feasible. We support an awful lot of combinations that affect the page table format on ARM: there are 5 different formats, each supporting different translation regimes (sets of page size) and each of those needs configuring for input/output address sizes to compute the number of levels. You could easily end up with over 20 page tables and their corresponding sets of control register values. Given that we only install one page table in the end, I'm struggling to see the issue with postponing its allocation until we've figured out the IOMMU instance thanks to a device attach. > VFIO already does that as a workaround of how things are done currently, > but I really think this should be done in the IOMMU core code. Postponing page table creation to ->attach works fine with VFIO today. AFAICT, it never tries to map pages for an empty domain and therefore the IOMMU instance is always known by the IOMMU driver at ->map time. > > In which situation do you think the merged pgsize_bitmap would get used? > > The only place I can think of is if we're trying to call iommu_map on a > > domain with no devices attached. However, if that domain was created > > using iommu_domain_alloc() then the pgsize_bitmap is the least of our > > worries -- we don't even know the page table format! > > The first usecase for the merged pgsize_bitmap that comes to mind is to > determine the minimum page-size that can be used for a domain. In the > SMMUv3 case when there are IOMMUs with different minium page-sizes in one > system, this would be the biggest minimum page-size of all IOMMUs. Understood, but I'm trying to understand why you'd want to know that for an empty (no devices attached) domain. I don't think we currently have any use-cases for that and it's really not a practical thing to support. Will ^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <20150602094746.GC22569-5wv7dgnIgG8@public.gmane.org>]
* Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices 2015-06-02 9:47 ` Will Deacon @ 2015-06-02 18:43 ` Joerg Roedel -1 siblings, 0 replies; 40+ messages in thread From: Joerg Roedel @ 2015-06-02 18:43 UTC (permalink / raw) To: Will Deacon Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On Tue, Jun 02, 2015 at 10:47:46AM +0100, Will Deacon wrote: > On Tue, Jun 02, 2015 at 08:39:56AM +0100, Joerg Roedel wrote: > > I don't think we need to postpone anything. Domains returned by > > iommu_domain_alloc() need to work for all groups. If there are multiple > > IOMMUs in the system with different capabilities/page-table formats the > > IOMMU core needs to build multiple page-tables for that domain. > > I really don't think that's feasible. We support an awful lot of > combinations that affect the page table format on ARM: there are 5 > different formats, each supporting different translation regimes (sets > of page size) and each of those needs configuring for input/output > address sizes to compute the number of levels. You could easily end up > with over 20 page tables and their corresponding sets of control > register values. We only need to build page-tables for IOMMUs that are actually in the system. And this also only for domains that are not tied to a particular group. If some hardware vendor is crazy enough to put 20 IOMMUs in the system with each having its own page-table format, then be it so. But in reality I think we will have only a handful of different page-tables. > Given that we only install one page table in the end, I'm struggling to > see the issue with postponing its allocation until we've figured out > the IOMMU instance thanks to a device attach. It is a question of the use-case for the domain. A device driver (like for USB or graphics) would allocate the domain with the _for_group function and end up with only one page-table. But if VFIO comes around and wants to attach devices to a KVM guest it would use iommu_domain_alloc() and has then all page-tables it possibly needs (for devices attached at start and even devices that might later be hotplugged into the guest). Joerg ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices @ 2015-06-02 18:43 ` Joerg Roedel 0 siblings, 0 replies; 40+ messages in thread From: Joerg Roedel @ 2015-06-02 18:43 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jun 02, 2015 at 10:47:46AM +0100, Will Deacon wrote: > On Tue, Jun 02, 2015 at 08:39:56AM +0100, Joerg Roedel wrote: > > I don't think we need to postpone anything. Domains returned by > > iommu_domain_alloc() need to work for all groups. If there are multiple > > IOMMUs in the system with different capabilities/page-table formats the > > IOMMU core needs to build multiple page-tables for that domain. > > I really don't think that's feasible. We support an awful lot of > combinations that affect the page table format on ARM: there are 5 > different formats, each supporting different translation regimes (sets > of page size) and each of those needs configuring for input/output > address sizes to compute the number of levels. You could easily end up > with over 20 page tables and their corresponding sets of control > register values. We only need to build page-tables for IOMMUs that are actually in the system. And this also only for domains that are not tied to a particular group. If some hardware vendor is crazy enough to put 20 IOMMUs in the system with each having its own page-table format, then be it so. But in reality I think we will have only a handful of different page-tables. > Given that we only install one page table in the end, I'm struggling to > see the issue with postponing its allocation until we've figured out > the IOMMU instance thanks to a device attach. It is a question of the use-case for the domain. A device driver (like for USB or graphics) would allocate the domain with the _for_group function and end up with only one page-table. But if VFIO comes around and wants to attach devices to a KVM guest it would use iommu_domain_alloc() and has then all page-tables it possibly needs (for devices attached at start and even devices that might later be hotplugged into the guest). Joerg ^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 3/3] drivers/vfio: Allow type-1 IOMMU instantiation on top of an ARM SMMUv3 2015-05-08 18:00 ` Will Deacon @ 2015-05-08 18:00 ` Will Deacon -1 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-08 18:00 UTC (permalink / raw) To: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA Cc: Will Deacon, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r The ARM SMMUv3 driver is compatible with the notion of a type-1 IOMMU in VFIO. This patch allows VFIO_IOMMU_TYPE1 to be selected if ARM_SMMU_V3=y. Signed-off-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> --- drivers/vfio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig index 7d092ddc8119..454017928ed0 100644 --- a/drivers/vfio/Kconfig +++ b/drivers/vfio/Kconfig @@ -21,7 +21,7 @@ config VFIO_VIRQFD menuconfig VFIO tristate "VFIO Non-Privileged userspace driver framework" depends on IOMMU_API - select VFIO_IOMMU_TYPE1 if (X86 || S390 || ARM_SMMU) + select VFIO_IOMMU_TYPE1 if (X86 || S390 || ARM_SMMU || ARM_SMMU_V3) select VFIO_IOMMU_SPAPR_TCE if (PPC_POWERNV || PPC_PSERIES) select VFIO_SPAPR_EEH if (PPC_POWERNV || PPC_PSERIES) select ANON_INODES -- 2.1.4 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 3/3] drivers/vfio: Allow type-1 IOMMU instantiation on top of an ARM SMMUv3 @ 2015-05-08 18:00 ` Will Deacon 0 siblings, 0 replies; 40+ messages in thread From: Will Deacon @ 2015-05-08 18:00 UTC (permalink / raw) To: linux-arm-kernel The ARM SMMUv3 driver is compatible with the notion of a type-1 IOMMU in VFIO. This patch allows VFIO_IOMMU_TYPE1 to be selected if ARM_SMMU_V3=y. Signed-off-by: Will Deacon <will.deacon@arm.com> --- drivers/vfio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig index 7d092ddc8119..454017928ed0 100644 --- a/drivers/vfio/Kconfig +++ b/drivers/vfio/Kconfig @@ -21,7 +21,7 @@ config VFIO_VIRQFD menuconfig VFIO tristate "VFIO Non-Privileged userspace driver framework" depends on IOMMU_API - select VFIO_IOMMU_TYPE1 if (X86 || S390 || ARM_SMMU) + select VFIO_IOMMU_TYPE1 if (X86 || S390 || ARM_SMMU || ARM_SMMU_V3) select VFIO_IOMMU_SPAPR_TCE if (PPC_POWERNV || PPC_PSERIES) select VFIO_SPAPR_EEH if (PPC_POWERNV || PPC_PSERIES) select ANON_INODES -- 2.1.4 ^ permalink raw reply related [flat|nested] 40+ messages in thread
end of thread, other threads:[~2015-06-02 18:43 UTC | newest]
Thread overview: 40+ messages (download: mbox.gz / follow: Atom feed)
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2015-05-08 18:00 [PATCH 0/3] iommu/arm-smmu: Add driver for ARM SMMUv3 devices Will Deacon
2015-05-08 18:00 ` Will Deacon
[not found] ` <1431108046-9675-1-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org>
2015-05-08 18:00 ` [PATCH 1/3] Documentation: dt-bindings: Add device-tree binding for ARM SMMUv3 IOMMU Will Deacon
2015-05-08 18:00 ` Will Deacon
2015-05-08 18:00 ` [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices Will Deacon
2015-05-08 18:00 ` Will Deacon
[not found] ` <1431108046-9675-3-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org>
2015-05-12 7:40 ` leizhen
2015-05-12 7:40 ` leizhen
[not found] ` <5551AE56.6050906-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-05-12 16:55 ` Will Deacon
2015-05-12 16:55 ` Will Deacon
[not found] ` <20150512165500.GE2062-5wv7dgnIgG8@public.gmane.org>
2015-05-13 8:33 ` leizhen
2015-05-13 8:33 ` leizhen
[not found] ` <55530C4F.5000605-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-05-21 11:25 ` Will Deacon
2015-05-21 11:25 ` Will Deacon
[not found] ` <20150521112555.GH21920-5wv7dgnIgG8@public.gmane.org>
2015-05-25 2:07 ` leizhen
2015-05-25 2:07 ` leizhen
[not found] ` <556283D5.4030901-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-05-26 16:12 ` Will Deacon
2015-05-26 16:12 ` Will Deacon
[not found] ` <20150526161245.GR1565-5wv7dgnIgG8@public.gmane.org>
2015-05-27 9:12 ` leizhen
2015-05-27 9:12 ` leizhen
2015-05-19 15:24 ` Joerg Roedel
2015-05-19 15:24 ` Joerg Roedel
[not found] ` <20150519152435.GL20611-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
2015-05-20 17:09 ` Will Deacon
2015-05-20 17:09 ` Will Deacon
[not found] ` <20150520170926.GI11498-5wv7dgnIgG8@public.gmane.org>
2015-05-29 6:43 ` Joerg Roedel
2015-05-29 6:43 ` Joerg Roedel
[not found] ` <20150529064337.GN20611-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
2015-05-29 11:35 ` Robin Murphy
2015-05-29 11:35 ` Robin Murphy
[not found] ` <55684F1C.3050702-5wv7dgnIgG8@public.gmane.org>
2015-05-29 14:40 ` Joerg Roedel
2015-05-29 14:40 ` Joerg Roedel
[not found] ` <20150529144043.GA20384-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
2015-06-01 9:40 ` Will Deacon
2015-06-01 9:40 ` Will Deacon
[not found] ` <20150601094014.GC1641-5wv7dgnIgG8@public.gmane.org>
2015-06-02 7:39 ` Joerg Roedel
2015-06-02 7:39 ` Joerg Roedel
[not found] ` <20150602073956.GG20384-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
2015-06-02 9:47 ` Will Deacon
2015-06-02 9:47 ` Will Deacon
[not found] ` <20150602094746.GC22569-5wv7dgnIgG8@public.gmane.org>
2015-06-02 18:43 ` Joerg Roedel
2015-06-02 18:43 ` Joerg Roedel
2015-05-08 18:00 ` [PATCH 3/3] drivers/vfio: Allow type-1 IOMMU instantiation on top of an ARM SMMUv3 Will Deacon
2015-05-08 18:00 ` Will Deacon
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