From: Will Deacon <will.deacon@arm.com>
To: David Daney <ddaney@caviumnetworks.com>
Cc: David Daney <ddaney.cavm@gmail.com>,
linux-arm-kernel@lists.infradead.org,
Mark Rutland <mark.rutland@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Marc Zyngier <marc.zyngier@arm.com>,
linux-kernel@vger.kernel.org, Andrew Pinski <apinski@cavium.com>,
David Daney <david.daney@cavium.com>
Subject: Re: [PATCH] arm64: Add workaround for Cavium erratum 27456
Date: Wed, 10 Feb 2016 18:15:22 +0000 [thread overview]
Message-ID: <20160210181522.GW1052@arm.com> (raw)
In-Reply-To: <56BB7C91.5010205@caviumnetworks.com>
On Wed, Feb 10, 2016 at 10:08:17AM -0800, David Daney wrote:
> On 02/10/2016 01:28 AM, Will Deacon wrote:
> >On Tue, Feb 09, 2016 at 11:29:16AM -0800, David Daney wrote:
> >>From: Andrew Pinski <apinski@cavium.com>
> >>
> >>On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
> >>instructions may cause the icache to become invalid if it contains
> >>data for a non-current ASID.
> >>
> >>This patch implements the workaround (which flushes the local icache
> >>when switching the mm) by using code patching.
> >
> >So, to be clear, is this "just" a performance problem as opposed to a
> >correctness issue?
>
> No. It is a correctness issue. Without this workaround in place, userspace
> programs end up executing the wrong instructions, which leads to
> unpredictable behavior and program crashes.
Ok, so I think the description in the commit log isn't quite right. An
"invalid" line in i-cache simply means that it needs to be refetched.
What you're talking about sounds like data corruption.
I also don't understand how the workaround fixes things like TLBIs due
to copy-on-write faults triggered by another core. Also, what's the
interaction with virtual machines, or is the VMID not affected in the
same way as the ASID?
Sorry to be a pain on this, but we need to understand the issue well
enough to maintain the workaround in the future!
> >If so, do you have any numbers with and without this
> >change?
>
> We tried to measure it, but the impact is not measurable in the tests we
> have done. Switching the mm is not often done so the extra ICache
> invalidation is rare.
Oh, sure. I was only interested in perf figures if this was a performance
problem rather than a functional one.
Will
WARNING: multiple messages have this Message-ID (diff)
From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] arm64: Add workaround for Cavium erratum 27456
Date: Wed, 10 Feb 2016 18:15:22 +0000 [thread overview]
Message-ID: <20160210181522.GW1052@arm.com> (raw)
In-Reply-To: <56BB7C91.5010205@caviumnetworks.com>
On Wed, Feb 10, 2016 at 10:08:17AM -0800, David Daney wrote:
> On 02/10/2016 01:28 AM, Will Deacon wrote:
> >On Tue, Feb 09, 2016 at 11:29:16AM -0800, David Daney wrote:
> >>From: Andrew Pinski <apinski@cavium.com>
> >>
> >>On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
> >>instructions may cause the icache to become invalid if it contains
> >>data for a non-current ASID.
> >>
> >>This patch implements the workaround (which flushes the local icache
> >>when switching the mm) by using code patching.
> >
> >So, to be clear, is this "just" a performance problem as opposed to a
> >correctness issue?
>
> No. It is a correctness issue. Without this workaround in place, userspace
> programs end up executing the wrong instructions, which leads to
> unpredictable behavior and program crashes.
Ok, so I think the description in the commit log isn't quite right. An
"invalid" line in i-cache simply means that it needs to be refetched.
What you're talking about sounds like data corruption.
I also don't understand how the workaround fixes things like TLBIs due
to copy-on-write faults triggered by another core. Also, what's the
interaction with virtual machines, or is the VMID not affected in the
same way as the ASID?
Sorry to be a pain on this, but we need to understand the issue well
enough to maintain the workaround in the future!
> >If so, do you have any numbers with and without this
> >change?
>
> We tried to measure it, but the impact is not measurable in the tests we
> have done. Switching the mm is not often done so the extra ICache
> invalidation is rare.
Oh, sure. I was only interested in perf figures if this was a performance
problem rather than a functional one.
Will
next prev parent reply other threads:[~2016-02-10 18:15 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-09 19:29 [PATCH] arm64: Add workaround for Cavium erratum 27456 David Daney
2016-02-09 19:29 ` David Daney
2016-02-09 19:52 ` Marc Zyngier
2016-02-09 19:52 ` Marc Zyngier
2016-02-09 19:59 ` David Daney
2016-02-09 19:59 ` David Daney
2016-02-09 20:07 ` Marc Zyngier
2016-02-09 20:07 ` Marc Zyngier
2016-02-10 9:28 ` Will Deacon
2016-02-10 9:28 ` Will Deacon
2016-02-10 18:08 ` David Daney
2016-02-10 18:08 ` David Daney
2016-02-10 18:15 ` Will Deacon [this message]
2016-02-10 18:15 ` Will Deacon
2016-02-10 18:42 ` David Daney
2016-02-10 18:42 ` David Daney
2016-02-11 13:07 ` Will Deacon
2016-02-11 13:07 ` Will Deacon
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