From: David Daney <ddaney@caviumnetworks.com>
To: Will Deacon <will.deacon@arm.com>
Cc: David Daney <ddaney.cavm@gmail.com>,
<linux-arm-kernel@lists.infradead.org>,
Mark Rutland <mark.rutland@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Marc Zyngier <marc.zyngier@arm.com>,
<linux-kernel@vger.kernel.org>,
Andrew Pinski <apinski@cavium.com>,
David Daney <david.daney@cavium.com>
Subject: Re: [PATCH] arm64: Add workaround for Cavium erratum 27456
Date: Wed, 10 Feb 2016 10:42:18 -0800 [thread overview]
Message-ID: <56BB848A.6060603@caviumnetworks.com> (raw)
In-Reply-To: <20160210181522.GW1052@arm.com>
On 02/10/2016 10:15 AM, Will Deacon wrote:
> On Wed, Feb 10, 2016 at 10:08:17AM -0800, David Daney wrote:
>> On 02/10/2016 01:28 AM, Will Deacon wrote:
>>> On Tue, Feb 09, 2016 at 11:29:16AM -0800, David Daney wrote:
>>>> From: Andrew Pinski <apinski@cavium.com>
>>>>
>>>> On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
>>>> instructions may cause the icache to become invalid if it contains
>>>> data for a non-current ASID.
>>>>
>>>> This patch implements the workaround (which flushes the local icache
>>>> when switching the mm) by using code patching.
>>>
>>> So, to be clear, is this "just" a performance problem as opposed to a
>>> correctness issue?
>>
>> No. It is a correctness issue. Without this workaround in place, userspace
>> programs end up executing the wrong instructions, which leads to
>> unpredictable behavior and program crashes.
>
> Ok, so I think the description in the commit log isn't quite right. An
> "invalid" line in i-cache simply means that it needs to be refetched.
> What you're talking about sounds like data corruption.
Yes. I guess I will be sending v3 with an improved description.
>
> I also don't understand how the workaround fixes things like TLBIs due
> to copy-on-write faults triggered by another core.
Caveat: I don't fully understand the internal ICache implementation
details. But ...
External broadcast TLBIs arriving for the current ASID (as set in
TTBR0_EL1) are handled properly. The issue is that cached data for
other ASIDs, under some circumstances, may be inadvertently "blessed"
into the current ASID. If we take care that no data for "foreign" ASIDs
is in the Icache, the problematical case can never occur.
> Also, what's the
> interaction with virtual machines, or is the VMID not affected in the
> same way as the ASID?
Ah, the $10^6 question. Current information on how this interacts with
KVM is less well developed. We think the workaround doesn't cause
failures in virtual machines.
I realize that this is different than asserting that virtual machines
are guaranteed to operate error free.
>
> Sorry to be a pain on this, but we need to understand the issue well
> enough to maintain the workaround in the future!
>
>>> If so, do you have any numbers with and without this
>>> change?
>>
>> We tried to measure it, but the impact is not measurable in the tests we
>> have done. Switching the mm is not often done so the extra ICache
>> invalidation is rare.
>
> Oh, sure. I was only interested in perf figures if this was a performance
> problem rather than a functional one.
>
> Will
>
WARNING: multiple messages have this Message-ID (diff)
From: ddaney@caviumnetworks.com (David Daney)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] arm64: Add workaround for Cavium erratum 27456
Date: Wed, 10 Feb 2016 10:42:18 -0800 [thread overview]
Message-ID: <56BB848A.6060603@caviumnetworks.com> (raw)
In-Reply-To: <20160210181522.GW1052@arm.com>
On 02/10/2016 10:15 AM, Will Deacon wrote:
> On Wed, Feb 10, 2016 at 10:08:17AM -0800, David Daney wrote:
>> On 02/10/2016 01:28 AM, Will Deacon wrote:
>>> On Tue, Feb 09, 2016 at 11:29:16AM -0800, David Daney wrote:
>>>> From: Andrew Pinski <apinski@cavium.com>
>>>>
>>>> On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
>>>> instructions may cause the icache to become invalid if it contains
>>>> data for a non-current ASID.
>>>>
>>>> This patch implements the workaround (which flushes the local icache
>>>> when switching the mm) by using code patching.
>>>
>>> So, to be clear, is this "just" a performance problem as opposed to a
>>> correctness issue?
>>
>> No. It is a correctness issue. Without this workaround in place, userspace
>> programs end up executing the wrong instructions, which leads to
>> unpredictable behavior and program crashes.
>
> Ok, so I think the description in the commit log isn't quite right. An
> "invalid" line in i-cache simply means that it needs to be refetched.
> What you're talking about sounds like data corruption.
Yes. I guess I will be sending v3 with an improved description.
>
> I also don't understand how the workaround fixes things like TLBIs due
> to copy-on-write faults triggered by another core.
Caveat: I don't fully understand the internal ICache implementation
details. But ...
External broadcast TLBIs arriving for the current ASID (as set in
TTBR0_EL1) are handled properly. The issue is that cached data for
other ASIDs, under some circumstances, may be inadvertently "blessed"
into the current ASID. If we take care that no data for "foreign" ASIDs
is in the Icache, the problematical case can never occur.
> Also, what's the
> interaction with virtual machines, or is the VMID not affected in the
> same way as the ASID?
Ah, the $10^6 question. Current information on how this interacts with
KVM is less well developed. We think the workaround doesn't cause
failures in virtual machines.
I realize that this is different than asserting that virtual machines
are guaranteed to operate error free.
>
> Sorry to be a pain on this, but we need to understand the issue well
> enough to maintain the workaround in the future!
>
>>> If so, do you have any numbers with and without this
>>> change?
>>
>> We tried to measure it, but the impact is not measurable in the tests we
>> have done. Switching the mm is not often done so the extra ICache
>> invalidation is rare.
>
> Oh, sure. I was only interested in perf figures if this was a performance
> problem rather than a functional one.
>
> Will
>
next prev parent reply other threads:[~2016-02-10 18:42 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-09 19:29 [PATCH] arm64: Add workaround for Cavium erratum 27456 David Daney
2016-02-09 19:29 ` David Daney
2016-02-09 19:52 ` Marc Zyngier
2016-02-09 19:52 ` Marc Zyngier
2016-02-09 19:59 ` David Daney
2016-02-09 19:59 ` David Daney
2016-02-09 20:07 ` Marc Zyngier
2016-02-09 20:07 ` Marc Zyngier
2016-02-10 9:28 ` Will Deacon
2016-02-10 9:28 ` Will Deacon
2016-02-10 18:08 ` David Daney
2016-02-10 18:08 ` David Daney
2016-02-10 18:15 ` Will Deacon
2016-02-10 18:15 ` Will Deacon
2016-02-10 18:42 ` David Daney [this message]
2016-02-10 18:42 ` David Daney
2016-02-11 13:07 ` Will Deacon
2016-02-11 13:07 ` Will Deacon
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