* [PATCH] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
@ 2016-03-14 18:24 Michał Winiarski
2016-03-14 19:48 ` Chris Wilson
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Michał Winiarski @ 2016-03-14 18:24 UTC (permalink / raw)
To: intel-gfx
On gen8+ size of PIPE_CONTROL with Post Sync Operation should be 6 dwords.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6fcbf6b..8fabca5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1933,7 +1933,7 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
* need a prior CS_STALL, which is emitted by the flush
* following the batch.
*/
- intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5));
+ intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
intel_logical_ring_emit(ringbuf,
(PIPE_CONTROL_GLOBAL_GTT_IVB |
PIPE_CONTROL_CS_STALL |
@@ -1941,6 +1941,7 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
intel_logical_ring_emit(ringbuf, hws_seqno_address(request->ring));
intel_logical_ring_emit(ringbuf, 0);
intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
+ intel_logical_ring_emit(ringbuf, 0);
intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
return intel_logical_ring_advance_and_submit(request);
}
--
2.7.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
2016-03-14 18:24 [PATCH] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write Michał Winiarski
@ 2016-03-14 19:48 ` Chris Wilson
2016-03-15 7:32 ` ✗ Fi.CI.BAT: failure for " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2016-03-14 19:48 UTC (permalink / raw)
To: Michał Winiarski; +Cc: intel-gfx
On Mon, Mar 14, 2016 at 07:24:56PM +0100, Michał Winiarski wrote:
> On gen8+ size of PIPE_CONTROL with Post Sync Operation should be 6 dwords.
5 or 6 depending on the size of the write.
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 6fcbf6b..8fabca5 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1933,7 +1933,7 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
> * need a prior CS_STALL, which is emitted by the flush
> * following the batch.
> */
> - intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5));
> + intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
> intel_logical_ring_emit(ringbuf,
> (PIPE_CONTROL_GLOBAL_GTT_IVB |
> PIPE_CONTROL_CS_STALL |
> @@ -1941,6 +1941,7 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
> intel_logical_ring_emit(ringbuf, hws_seqno_address(request->ring));
> intel_logical_ring_emit(ringbuf, 0);
> intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
> + intel_logical_ring_emit(ringbuf, 0);
> intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
Qword alignment forgotten anyway.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
2016-03-14 18:24 [PATCH] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write Michał Winiarski
2016-03-14 19:48 ` Chris Wilson
@ 2016-03-15 7:32 ` Patchwork
2016-03-15 9:20 ` [PATCH v2] " Michał Winiarski
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2016-03-15 7:32 UTC (permalink / raw)
To: Michał Winiarski; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
URL : https://patchwork.freedesktop.org/series/4446/
State : failure
== Summary ==
Series 4446v1 drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
http://patchwork.freedesktop.org/api/1.0/series/4446/revisions/1/mbox/
Test drv_module_reload_basic:
pass -> DMESG-WARN (bsw-nuc-2)
pass -> SKIP (skl-i5k-2)
pass -> DMESG-WARN (bdw-ultra)
pass -> DMESG-WARN (skl-i7k-2)
pass -> SKIP (snb-dellxps)
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (bdw-nuci7)
Test gem_exec_basic:
Subgroup readonly-render:
incomplete -> PASS (ilk-hp8440p)
Test gem_exec_whisper:
Subgroup basic:
pass -> DMESG-WARN (bdw-ultra)
pass -> DMESG-WARN (skl-i7k-2)
Test gem_mmap_gtt:
Subgroup basic-write-no-prefault:
incomplete -> PASS (ilk-hp8440p)
Test gem_pread:
Subgroup basic:
pass -> DMESG-WARN (skl-i5k-2)
Test gem_render_linear_blits:
Subgroup basic:
pass -> DMESG-WARN (bdw-nuci7)
Test gem_render_tiled_blits:
Subgroup basic:
pass -> DMESG-WARN (bdw-nuci7)
Test gem_ringfill:
Subgroup basic-default:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (bsw-nuc-2)
pass -> DMESG-WARN (bdw-nuci7)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-default-bomb:
pass -> DMESG-WARN (bsw-nuc-2)
Subgroup basic-default-child:
pass -> DMESG-WARN (skl-nuci5)
Subgroup basic-default-hang:
pass -> DMESG-WARN (bsw-nuc-2)
pass -> DMESG-WARN (bdw-ultra)
Subgroup basic-default-interruptible:
pass -> DMESG-WARN (skl-nuci5)
Subgroup basic-default-s3:
dmesg-warn -> PASS (bsw-nuc-2)
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (bdw-nuci7)
incomplete -> DMESG-WARN (ilk-hp8440p)
Test gem_storedw_loop:
Subgroup basic-blt:
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-default:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (bdw-ultra)
Subgroup basic-render:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (bdw-ultra) UNSTABLE
Test gem_sync:
Subgroup basic-all:
pass -> DMESG-FAIL (bsw-nuc-2)
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (bdw-ultra)
pass -> DMESG-FAIL (skl-i7k-2)
pass -> DMESG-FAIL (skl-nuci5)
pass -> DMESG-FAIL (bdw-nuci7)
Subgroup basic-blt:
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-default:
pass -> DMESG-FAIL (bsw-nuc-2)
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (bdw-ultra)
pass -> DMESG-FAIL (skl-i7k-2)
pass -> DMESG-FAIL (skl-nuci5)
pass -> DMESG-FAIL (bdw-nuci7)
Subgroup basic-render:
pass -> DMESG-FAIL (bsw-nuc-2)
pass -> DMESG-FAIL (skl-i5k-2) UNSTABLE
pass -> DMESG-FAIL (bdw-ultra) UNSTABLE
pass -> DMESG-FAIL (skl-i7k-2) UNSTABLE
pass -> DMESG-FAIL (skl-nuci5)
pass -> DMESG-FAIL (bdw-nuci7) UNSTABLE
Test gem_tiled_pread_basic:
incomplete -> PASS (byt-nuc)
Test kms_addfb_basic:
Subgroup addfb25-x-tiled:
pass -> DMESG-WARN (skl-i7k-2)
Subgroup addfb25-yf-tiled:
incomplete -> PASS (ilk-hp8440p)
Subgroup bad-pitch-1024:
incomplete -> PASS (ilk-hp8440p)
Subgroup basic-y-tiled:
pass -> DMESG-WARN (skl-i5k-2)
Subgroup size-max:
incomplete -> PASS (ilk-hp8440p)
Subgroup small-bo:
incomplete -> PASS (ilk-hp8440p)
Subgroup unused-modifier:
pass -> DMESG-WARN (skl-i5k-2)
Subgroup unused-offsets:
incomplete -> PASS (ilk-hp8440p)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (bdw-ultra)
pass -> DMESG-WARN (ilk-hp8440p) UNSTABLE
Subgroup basic-flip-vs-modeset:
incomplete -> PASS (bsw-nuc-2)
pass -> DMESG-WARN (bdw-ultra)
Subgroup basic-flip-vs-wf_vblank:
pass -> DMESG-WARN (hsw-gt2)
Subgroup basic-plain-flip:
pass -> DMESG-WARN (hsw-brixbox)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
skip -> INCOMPLETE (bsw-nuc-2)
Subgroup read-crc-pipe-a-frame-sequence:
pass -> DMESG-WARN (ilk-hp8440p)
Subgroup read-crc-pipe-b-frame-sequence:
pass -> DMESG-WARN (skl-i7k-2)
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS (hsw-gt2)
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (skl-i7k-2)
Test pm_rpm:
Subgroup basic-pci-d3-state:
dmesg-warn -> PASS (bsw-nuc-2)
pass -> DMESG-WARN (snb-dellxps)
Test prime_self_import:
Subgroup basic-llseek-size:
incomplete -> PASS (ilk-hp8440p)
bdw-nuci7 total:194 pass:174 dwarn:5 dfail:3 fail:0 skip:12
bdw-ultra total:194 pass:164 dwarn:6 dfail:3 fail:0 skip:21
bsw-nuc-2 total:183 pass:142 dwarn:6 dfail:3 fail:0 skip:31
byt-nuc total:194 pass:154 dwarn:4 dfail:0 fail:1 skip:35
hsw-brixbox total:194 pass:171 dwarn:1 dfail:0 fail:0 skip:22
hsw-gt2 total:194 pass:176 dwarn:1 dfail:0 fail:0 skip:17
ilk-hp8440p total:194 pass:124 dwarn:6 dfail:0 fail:1 skip:63
ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25
skl-i5k-2 total:194 pass:163 dwarn:4 dfail:3 fail:0 skip:24
skl-i7k-2 total:194 pass:160 dwarn:8 dfail:3 fail:0 skip:23
skl-nuci5 total:194 pass:174 dwarn:6 dfail:3 fail:0 skip:11
snb-dellxps total:194 pass:157 dwarn:2 dfail:0 fail:0 skip:35
snb-x220t total:194 pass:158 dwarn:1 dfail:0 fail:1 skip:34
Results at /archive/results/CI_IGT_test/Patchwork_1598/
3e5ecc8c5ff80cb1fb635ce1cf16b7cd4cfb1979 drm-intel-nightly: 2016y-03m-14d-09h-06m-00s UTC integration manifest
de42ebd047a5e2d47990a394526fc345d1dc849f drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
2016-03-14 18:24 [PATCH] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write Michał Winiarski
2016-03-14 19:48 ` Chris Wilson
2016-03-15 7:32 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2016-03-15 9:20 ` Michał Winiarski
2016-03-15 10:01 ` Chris Wilson
2016-03-15 17:52 ` [PATCH v3] " Michał Winiarski
2016-03-15 10:37 ` ✗ Fi.CI.BAT: warning for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev2) Patchwork
2016-03-16 6:57 ` ✗ Fi.CI.BAT: warning for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev3) Patchwork
4 siblings, 2 replies; 8+ messages in thread
From: Michał Winiarski @ 2016-03-15 9:20 UTC (permalink / raw)
To: intel-gfx
On gen8+ size of PIPE_CONTROL with Post Sync Operation should be 6 dwords.
v2: Fix BAT failures
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6fcbf6b..5b7b2ae 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1925,7 +1925,7 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
struct intel_ringbuffer *ringbuf = request->ringbuf;
int ret;
- ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);
+ ret = intel_logical_ring_begin(request, 8 + WA_TAIL_DWORDS);
if (ret)
return ret;
@@ -1933,7 +1933,7 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
* need a prior CS_STALL, which is emitted by the flush
* following the batch.
*/
- intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5));
+ intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
intel_logical_ring_emit(ringbuf,
(PIPE_CONTROL_GLOBAL_GTT_IVB |
PIPE_CONTROL_CS_STALL |
@@ -1941,7 +1941,9 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
intel_logical_ring_emit(ringbuf, hws_seqno_address(request->ring));
intel_logical_ring_emit(ringbuf, 0);
intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
+ intel_logical_ring_emit(ringbuf, 0);
intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
+ intel_logical_ring_emit(ringbuf, 0);
return intel_logical_ring_advance_and_submit(request);
}
--
2.7.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
2016-03-15 9:20 ` [PATCH v2] " Michał Winiarski
@ 2016-03-15 10:01 ` Chris Wilson
2016-03-15 17:52 ` [PATCH v3] " Michał Winiarski
1 sibling, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2016-03-15 10:01 UTC (permalink / raw)
To: Michał Winiarski; +Cc: intel-gfx
On Tue, Mar 15, 2016 at 10:20:09AM +0100, Michał Winiarski wrote:
> On gen8+ size of PIPE_CONTROL with Post Sync Operation should be 6 dwords.
But gen8/gen9 still respect 5 for a dword write instead of a qword write.
Please include an explanation of the impact.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev2)
2016-03-14 18:24 [PATCH] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write Michał Winiarski
` (2 preceding siblings ...)
2016-03-15 9:20 ` [PATCH v2] " Michał Winiarski
@ 2016-03-15 10:37 ` Patchwork
2016-03-16 6:57 ` ✗ Fi.CI.BAT: warning for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev3) Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2016-03-15 10:37 UTC (permalink / raw)
To: Michał Winiarski; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev2)
URL : https://patchwork.freedesktop.org/series/4446/
State : warning
== Summary ==
Series 4446v2 drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
http://patchwork.freedesktop.org/api/1.0/series/4446/revisions/2/mbox/
Test drv_module_reload_basic:
skip -> PASS (hsw-brixbox)
Test gem_exec_basic:
Subgroup gtt-render:
dmesg-warn -> PASS (bsw-nuc-2)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (hsw-brixbox)
Subgroup basic-flip-vs-modeset:
pass -> DMESG-WARN (hsw-brixbox)
Subgroup basic-plain-flip:
pass -> DMESG-WARN (hsw-gt2)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b:
dmesg-warn -> PASS (hsw-gt2)
Subgroup read-crc-pipe-c-frame-sequence:
pass -> DMESG-WARN (hsw-gt2)
Test pm_rpm:
Subgroup basic-rte:
pass -> DMESG-WARN (snb-dellxps)
bdw-nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip:12
bdw-ultra total:194 pass:173 dwarn:0 dfail:0 fail:0 skip:21
bsw-nuc-2 total:194 pass:157 dwarn:0 dfail:0 fail:0 skip:37
byt-nuc total:194 pass:155 dwarn:4 dfail:0 fail:0 skip:35
hsw-brixbox total:194 pass:171 dwarn:1 dfail:0 fail:0 skip:22
hsw-gt2 total:194 pass:175 dwarn:2 dfail:0 fail:0 skip:17
ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25
skl-i5k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
skl-nuci5 total:194 pass:183 dwarn:0 dfail:0 fail:0 skip:11
snb-dellxps total:194 pass:158 dwarn:2 dfail:0 fail:0 skip:34
snb-x220t total:194 pass:160 dwarn:0 dfail:1 fail:0 skip:33
Results at /archive/results/CI_IGT_test/Patchwork_1600/
3e5ecc8c5ff80cb1fb635ce1cf16b7cd4cfb1979 drm-intel-nightly: 2016y-03m-14d-09h-06m-00s UTC integration manifest
0739b41c7c5d73597668f969418b6ddef9bde7aa drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
2016-03-15 9:20 ` [PATCH v2] " Michał Winiarski
2016-03-15 10:01 ` Chris Wilson
@ 2016-03-15 17:52 ` Michał Winiarski
1 sibling, 0 replies; 8+ messages in thread
From: Michał Winiarski @ 2016-03-15 17:52 UTC (permalink / raw)
To: intel-gfx
On gen8+ size of PIPE_CONTROL with Post Sync Operation should be
6 dwords. When we're using older 5-dword variant it's possible to
observe inconsistent values written by 6-dword PIPE_CONTROL with Post
Sync Operation from user batches.
v2: Fix BAT failures
v3: Comments on alignment and thrashing high dword of seqno (Chris)
Testcase: igt/gem_pipe_control_store_loop/*-qword-write
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6fcbf6b..4c7ebc4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1925,15 +1925,18 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
struct intel_ringbuffer *ringbuf = request->ringbuf;
int ret;
- ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);
+ ret = intel_logical_ring_begin(request, 8 + WA_TAIL_DWORDS);
if (ret)
return ret;
+ /* We're using qword write, seqno should be aligned to 8 bytes. */
+ BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
+
/* w/a for post sync ops following a GPGPU operation we
* need a prior CS_STALL, which is emitted by the flush
* following the batch.
*/
- intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5));
+ intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
intel_logical_ring_emit(ringbuf,
(PIPE_CONTROL_GLOBAL_GTT_IVB |
PIPE_CONTROL_CS_STALL |
@@ -1941,7 +1944,10 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
intel_logical_ring_emit(ringbuf, hws_seqno_address(request->ring));
intel_logical_ring_emit(ringbuf, 0);
intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
+ /* We're thrashing one dword of HWS. */
+ intel_logical_ring_emit(ringbuf, 0);
intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
return intel_logical_ring_advance_and_submit(request);
}
--
2.7.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev3)
2016-03-14 18:24 [PATCH] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write Michał Winiarski
` (3 preceding siblings ...)
2016-03-15 10:37 ` ✗ Fi.CI.BAT: warning for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev2) Patchwork
@ 2016-03-16 6:57 ` Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2016-03-16 6:57 UTC (permalink / raw)
To: Michał Winiarski; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev3)
URL : https://patchwork.freedesktop.org/series/4446/
State : warning
== Summary ==
Series 4446v3 drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
http://patchwork.freedesktop.org/api/1.0/series/4446/revisions/3/mbox/
Test drv_module_reload_basic:
skip -> PASS (bdw-nuci7)
Test gem_ringfill:
Subgroup basic-default-s3:
pass -> DMESG-WARN (bsw-nuc-2)
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
dmesg-warn -> PASS (hsw-brixbox)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c:
fail -> PASS (hsw-brixbox)
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS (skl-nuci5)
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass -> DMESG-WARN (snb-dellxps)
Subgroup basic-rte:
pass -> DMESG-WARN (bsw-nuc-2)
pass -> DMESG-WARN (byt-nuc) UNSTABLE
bdw-nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip:12
bdw-ultra total:194 pass:173 dwarn:0 dfail:0 fail:0 skip:21
bsw-nuc-2 total:194 pass:155 dwarn:2 dfail:0 fail:0 skip:37
byt-nuc total:194 pass:154 dwarn:5 dfail:0 fail:0 skip:35
hsw-brixbox total:194 pass:172 dwarn:0 dfail:0 fail:0 skip:22
hsw-gt2 total:194 pass:177 dwarn:0 dfail:0 fail:0 skip:17
ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25
skl-i5k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
skl-nuci5 total:194 pass:183 dwarn:0 dfail:0 fail:0 skip:11
snb-dellxps total:194 pass:158 dwarn:2 dfail:0 fail:0 skip:34
Results at /archive/results/CI_IGT_test/Patchwork_1606/
fc881ebd9c3c26919c7d1113f8bf7014e1a05563 drm-intel-nightly: 2016y-03m-15d-13h-10m-41s UTC integration manifest
ace9fe27af8fed36ba4401dfee7eae1785e213ea drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-03-16 6:57 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-03-14 18:24 [PATCH] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write Michał Winiarski
2016-03-14 19:48 ` Chris Wilson
2016-03-15 7:32 ` ✗ Fi.CI.BAT: failure for " Patchwork
2016-03-15 9:20 ` [PATCH v2] " Michał Winiarski
2016-03-15 10:01 ` Chris Wilson
2016-03-15 17:52 ` [PATCH v3] " Michał Winiarski
2016-03-15 10:37 ` ✗ Fi.CI.BAT: warning for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev2) Patchwork
2016-03-16 6:57 ` ✗ Fi.CI.BAT: warning for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev3) Patchwork
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