From: marcel@ziswiler.com
To: devicetree@vger.kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>,
Alexandre Courbot <gnurou@gmail.com>,
Stephen Warren <swarren@wwwdotorg.org>,
Marcel Ziswiler <marcel.ziswiler@toradex.com>,
linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Russell King <linux@armlinux.org.uk>,
Thierry Reding <thierry.reding@gmail.com>,
linux-tegra@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH 4/6] apalis-tk1: adjust pin muxing for v1.1 hw
Date: Thu, 24 Nov 2016 02:04:54 +0100 [thread overview]
Message-ID: <20161124010456.24604-5-marcel@ziswiler.com> (raw)
In-Reply-To: <20161124010456.24604-1-marcel@ziswiler.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Configure Apalis MMC1 D6 GPIO on SDMMC3_CLK_LB_IN as reserved function
without any pull-up/down.
Configure GPIO_PV2 as SD1_CD# according to latest V1.1 HW.
Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output driver enabled aka
not tristated and input driver enabled as well as it features some
magic properties even though the external loopback is disabled and the
internal loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 register's
SDMMC_SPARE1 bits being set to 0xfffd according to the TRM! This pin is
now a not-connect on V1.1 HW in order to avoid any interference.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra124-apalis.dtsi | 53 +++++++++++++++-------------------
1 file changed, 23 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 747ce81..2bfc579 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -414,18 +414,10 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
- /*
- * Don't use MMC1_D6 aka SDMMC3_CLK_LB_IN for now as it
- * features some magic properties even though the
- * external loopback is disabled and the internal
- * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
- * register's SDMMC_SPARE1 bits being set to 0xfffd
- * according to the TRM!
- */
sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
nvidia,pins = "sdmmc3_clk_lb_in_pee5";
- nvidia,function = "sdmmc3";
- nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
@@ -520,20 +512,12 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
- /*
- * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it
- * features some magic properties even though the
- * external loopback is disabled and the internal
- * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
- * register's SDMMC_SPARE1 bits being set to 0xfffd
- * according to the TRM!
- */
- sdmmc3_clk_lb_out_pee4 { /* CD# GPIO */
- nvidia,pins = "sdmmc3_clk_lb_out_pee4";
- nvidia,function = "rsvd2";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ sdmmc3_cd_n_pv2 { /* CD# GPIO */
+ nvidia,pins = "sdmmc3_cd_n_pv2";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* Apalis SPDIF */
@@ -1512,13 +1496,6 @@
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
- sdmmc3_cd_n_pv2 { /* NC */
- nvidia,pins = "sdmmc3_cd_n_pv2";
- nvidia,function = "rsvd3";
- nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- };
gpio_x1_aud_px1 { /* NC */
nvidia,pins = "gpio_x1_aud_px1";
nvidia,function = "rsvd2";
@@ -1568,6 +1545,22 @@
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
+ /*
+ * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
+ * driver enabled aka not tristated and input driver
+ * enabled as well as it features some magic properties
+ * even though the external loopback is disabled and the
+ * internal loopback used as per
+ * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
+ * bits being set to 0xfffd according to the TRM!
+ */
+ sdmmc3_clk_lb_out_pee4 { /* NC */
+ nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
};
};
--
2.9.3
WARNING: multiple messages have this Message-ID (diff)
From: marcel@ziswiler.com
To: devicetree@vger.kernel.org
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>,
Thierry Reding <thierry.reding@gmail.com>,
linux-kernel@vger.kernel.org,
Stephen Warren <swarren@wwwdotorg.org>,
Rob Herring <robh+dt@kernel.org>,
linux-tegra@vger.kernel.org, Mark Rutland <mark.rutland@arm.com>,
Alexandre Courbot <gnurou@gmail.com>,
Russell King <linux@armlinux.org.uk>,
linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH 4/6] apalis-tk1: adjust pin muxing for v1.1 hw
Date: Thu, 24 Nov 2016 02:04:54 +0100 [thread overview]
Message-ID: <20161124010456.24604-5-marcel@ziswiler.com> (raw)
In-Reply-To: <20161124010456.24604-1-marcel@ziswiler.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Configure Apalis MMC1 D6 GPIO on SDMMC3_CLK_LB_IN as reserved function
without any pull-up/down.
Configure GPIO_PV2 as SD1_CD# according to latest V1.1 HW.
Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output driver enabled aka
not tristated and input driver enabled as well as it features some
magic properties even though the external loopback is disabled and the
internal loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 register's
SDMMC_SPARE1 bits being set to 0xfffd according to the TRM! This pin is
now a not-connect on V1.1 HW in order to avoid any interference.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra124-apalis.dtsi | 53 +++++++++++++++-------------------
1 file changed, 23 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 747ce81..2bfc579 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -414,18 +414,10 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
- /*
- * Don't use MMC1_D6 aka SDMMC3_CLK_LB_IN for now as it
- * features some magic properties even though the
- * external loopback is disabled and the internal
- * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
- * register's SDMMC_SPARE1 bits being set to 0xfffd
- * according to the TRM!
- */
sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
nvidia,pins = "sdmmc3_clk_lb_in_pee5";
- nvidia,function = "sdmmc3";
- nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
@@ -520,20 +512,12 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
- /*
- * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it
- * features some magic properties even though the
- * external loopback is disabled and the internal
- * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
- * register's SDMMC_SPARE1 bits being set to 0xfffd
- * according to the TRM!
- */
- sdmmc3_clk_lb_out_pee4 { /* CD# GPIO */
- nvidia,pins = "sdmmc3_clk_lb_out_pee4";
- nvidia,function = "rsvd2";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ sdmmc3_cd_n_pv2 { /* CD# GPIO */
+ nvidia,pins = "sdmmc3_cd_n_pv2";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* Apalis SPDIF */
@@ -1512,13 +1496,6 @@
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
- sdmmc3_cd_n_pv2 { /* NC */
- nvidia,pins = "sdmmc3_cd_n_pv2";
- nvidia,function = "rsvd3";
- nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- };
gpio_x1_aud_px1 { /* NC */
nvidia,pins = "gpio_x1_aud_px1";
nvidia,function = "rsvd2";
@@ -1568,6 +1545,22 @@
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
+ /*
+ * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
+ * driver enabled aka not tristated and input driver
+ * enabled as well as it features some magic properties
+ * even though the external loopback is disabled and the
+ * internal loopback used as per
+ * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
+ * bits being set to 0xfffd according to the TRM!
+ */
+ sdmmc3_clk_lb_out_pee4 { /* NC */
+ nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
};
};
--
2.9.3
WARNING: multiple messages have this Message-ID (diff)
From: marcel@ziswiler.com (marcel at ziswiler.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH 4/6] apalis-tk1: adjust pin muxing for v1.1 hw
Date: Thu, 24 Nov 2016 02:04:54 +0100 [thread overview]
Message-ID: <20161124010456.24604-5-marcel@ziswiler.com> (raw)
In-Reply-To: <20161124010456.24604-1-marcel@ziswiler.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Configure Apalis MMC1 D6 GPIO on SDMMC3_CLK_LB_IN as reserved function
without any pull-up/down.
Configure GPIO_PV2 as SD1_CD# according to latest V1.1 HW.
Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output driver enabled aka
not tristated and input driver enabled as well as it features some
magic properties even though the external loopback is disabled and the
internal loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 register's
SDMMC_SPARE1 bits being set to 0xfffd according to the TRM! This pin is
now a not-connect on V1.1 HW in order to avoid any interference.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra124-apalis.dtsi | 53 +++++++++++++++-------------------
1 file changed, 23 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 747ce81..2bfc579 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -414,18 +414,10 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
- /*
- * Don't use MMC1_D6 aka SDMMC3_CLK_LB_IN for now as it
- * features some magic properties even though the
- * external loopback is disabled and the internal
- * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
- * register's SDMMC_SPARE1 bits being set to 0xfffd
- * according to the TRM!
- */
sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
nvidia,pins = "sdmmc3_clk_lb_in_pee5";
- nvidia,function = "sdmmc3";
- nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
@@ -520,20 +512,12 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
- /*
- * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it
- * features some magic properties even though the
- * external loopback is disabled and the internal
- * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
- * register's SDMMC_SPARE1 bits being set to 0xfffd
- * according to the TRM!
- */
- sdmmc3_clk_lb_out_pee4 { /* CD# GPIO */
- nvidia,pins = "sdmmc3_clk_lb_out_pee4";
- nvidia,function = "rsvd2";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ sdmmc3_cd_n_pv2 { /* CD# GPIO */
+ nvidia,pins = "sdmmc3_cd_n_pv2";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* Apalis SPDIF */
@@ -1512,13 +1496,6 @@
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
- sdmmc3_cd_n_pv2 { /* NC */
- nvidia,pins = "sdmmc3_cd_n_pv2";
- nvidia,function = "rsvd3";
- nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- };
gpio_x1_aud_px1 { /* NC */
nvidia,pins = "gpio_x1_aud_px1";
nvidia,function = "rsvd2";
@@ -1568,6 +1545,22 @@
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
+ /*
+ * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
+ * driver enabled aka not tristated and input driver
+ * enabled as well as it features some magic properties
+ * even though the external loopback is disabled and the
+ * internal loopback used as per
+ * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
+ * bits being set to 0xfffd according to the TRM!
+ */
+ sdmmc3_clk_lb_out_pee4 { /* NC */
+ nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
};
};
--
2.9.3
next prev parent reply other threads:[~2016-11-24 1:04 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-24 1:04 [RESEND PATCH 0/6] apalis-tk1: updates for v1.1 hw marcel
2016-11-24 1:04 ` marcel at ziswiler.com
2016-11-24 1:04 ` [RESEND PATCH 1/6] apalis-tk1: remove spurious new lines marcel
2016-11-24 1:04 ` marcel at ziswiler.com
2016-11-24 1:04 ` [RESEND PATCH 2/6] apalis-tk1: temp alert pull-up marcel
2016-11-24 1:04 ` marcel at ziswiler.com
[not found] ` <20161124010456.24604-1-marcel-mitwqZ+T+m9Wk0Htik3J/w@public.gmane.org>
2016-11-24 1:04 ` [RESEND PATCH 3/6] apalis-tk1: optional displayport hot-plug detect marcel-mitwqZ+T+m9Wk0Htik3J/w
2016-11-24 1:04 ` marcel at ziswiler.com
2016-11-24 1:04 ` marcel
2016-11-24 1:04 ` marcel [this message]
2016-11-24 1:04 ` [RESEND PATCH 4/6] apalis-tk1: adjust pin muxing for v1.1 hw marcel at ziswiler.com
2016-11-24 1:04 ` marcel
2016-11-24 1:04 ` [RESEND PATCH 5/6] apalis-tk1: working sd card detect on " marcel
2016-11-24 1:04 ` marcel at ziswiler.com
2016-11-24 1:04 ` [RESEND PATCH 6/6] apalis-tk1: update compatibility comment marcel
2016-11-24 1:04 ` marcel at ziswiler.com
2017-01-03 13:20 ` [RESEND PATCH 0/6] apalis-tk1: updates for v1.1 hw Marcel Ziswiler
2017-01-03 13:20 ` Marcel Ziswiler
2017-01-03 13:20 ` Marcel Ziswiler
[not found] ` <1483449646.2745.1.camel-2KBjVHiyJgBBDgjK7y7TUQ@public.gmane.org>
2017-01-25 6:56 ` Thierry Reding
2017-01-25 6:56 ` Thierry Reding
2017-01-25 6:56 ` Thierry Reding
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