[OpenRISC] [PATCH] target-openrisc: Fix exception handling status registers

[Stafford Horne <shorne@gmail.com>]

Hello,

Sorry for the duplicate. There was an issue with my copy to qemu-devel
group.  Resent to everyone with proper cc to qemu-devel.

Please ignore this one.

-Stafford

On Sat, Jan 14, 2017 at 06:57:20AM +0900, Stafford Horne wrote:
> I am working on testing instruction emulation patches for the linux
> kernel. During testing I found these 2 issues:
> 
>  - sets DSX (delay slot exception) but never clears it
>  - EEAR for illegal insns should point to the bad exception (as per
>    openrisc spec) but its not
> 
> This patch fixes these two issues by clearing the DSX flag when not in a
> delay slot and by setting EEAR to exception PC when handling illegal
> instruction exceptions.
> 
> After this patch the openrisc kernel with latest patches boots great on
> qemu and instruction emulation works.
> 
> Cc: qemu-trivial at nongnu.org
> Cc: openrisc at lists.librecores.org
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
>  target/openrisc/interrupt.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
> index 5fe3f11..e1b0142 100644
> --- a/target/openrisc/interrupt.c
> +++ b/target/openrisc/interrupt.c
> @@ -38,10 +38,17 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
>          env->flags &= ~D_FLAG;
>          env->sr |= SR_DSX;
>          env->epcr -= 4;
> +    } else {
> +        env->sr &= ~SR_DSX;
>      }
>      if (cs->exception_index == EXCP_SYSCALL) {
>          env->epcr += 4;
>      }
> +    /* When we have an illegal instruction the error effective address
> +       shall be set to the illegal instruction address.  */
> +    if (cs->exception_index == EXCP_ILLEGAL) {
> +        env->eear = env->pc;
> +    }
>  
>      /* For machine-state changed between user-mode and supervisor mode,
>         we need flush TLB when we enter&exit EXCP.  */
> -- 
> 2.9.3
>