[U-Boot] [PATCH] x86: baytrail: Configure SPI BIOS parameters

[U-Boot] [PATCH] x86: baytrail: Configure SPI BIOS parameters

[Stefan Roese]

Without configuring these registers in the SPI controller, the Linux
MTD device driver is not able to correctly read/write to the SPI
NOR chip at all. In fact, the chip is not detected at all.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
---
 arch/x86/cpu/baytrail/cpu.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
index 0bb08524f8..4e12c8ce76 100644
--- a/arch/x86/cpu/baytrail/cpu.c
+++ b/arch/x86/cpu/baytrail/cpu.c
@@ -16,6 +16,7 @@
 #include <asm/lapic.h>
 #include <asm/msr.h>
 #include <asm/turbo.h>
+#include <asm/arch/iomap.h>
 
 #define BYT_PRV_CLK			0x800
 #define BYT_PRV_CLK_EN			(1 << 0)
@@ -23,6 +24,44 @@
 #define BYT_PRV_CLK_N_VAL_SHIFT		16
 #define BYT_PRV_CLK_UPDATE		(1 << 31)
 
+/* SPI register offsets */
+#define OPTYPE				0x96
+#define OPMENU0				0x98
+#define OPMENU1				0x9c
+
+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 0x01 /* Write, no address */
+
+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 0x03 /* Write, address required */
+
+#define SPI_OPMENU_2 0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 0x02 /* Read, address required */
+
+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 0x00 /* Read, no address */
+
+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 0x03 /* Write, address required */
+
+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 0x00 /* Read, no address */
+
+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 0x03 /* Write, address required */
+
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
+
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 <<  8) | \
+		    (SPI_OPTYPE_3 <<  6) | (SPI_OPTYPE_2 <<  4) | \
+		    (SPI_OPTYPE_1 <<  2) | (SPI_OPTYPE_0 <<  0))
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+			  (SPI_OPMENU_5 <<  8) | (SPI_OPMENU_4 <<  0))
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+			  (SPI_OPMENU_1 <<  8) | (SPI_OPMENU_0 <<  0))
+
 static void hsuart_clock_set(void *base)
 {
 	u32 m, n, reg;
@@ -40,6 +79,17 @@ static void hsuart_clock_set(void *base)
 }
 
 /*
+ * Configure SPI controller so that the Linux MTD driver can fully
+ * access the SPI NOR chip
+ */
+static void spi_controller_config(void *base)
+{
+	writew(SPI_OPTYPE, base + OPTYPE);
+	writel(SPI_OPMENU_LOWER, base + OPMENU0);
+	writel(SPI_OPMENU_UPPER, base + OPMENU1);
+}
+
+/*
  * Configure the internal clock of both SIO HS-UARTs, if they are enabled
  * via FSP
  */
@@ -60,6 +110,13 @@ int arch_cpu_init_dm(void)
 		}
 	}
 
+	/*
+	 * Configure the SPI-NOR controller in a way that the Linux
+	 * MTD SPI-NOR device driver has full read-write access to
+	 * the SPI-NOR chips
+	 */
+	spi_controller_config((void *)SPI_BASE_ADDRESS);
+
 	return 0;
 }
 
-- 
2.11.0

[U-Boot] [PATCH] x86: baytrail: Configure SPI BIOS parameters

[Simon Glass]

Hi Stefan,

On 20 January 2017 at 07:26, Stefan Roese <sr@denx.de> wrote:
> Without configuring these registers in the SPI controller, the Linux
> MTD device driver is not able to correctly read/write to the SPI
> NOR chip at all. In fact, the chip is not detected at all.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Bin Meng <bmeng.cn@gmail.com>
> ---
>  arch/x86/cpu/baytrail/cpu.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 57 insertions(+)

Can we do this in the SPI driver? It already has register definitions.

Regards,
Simon

[U-Boot] [PATCH] x86: baytrail: Configure SPI BIOS parameters

[Bin Meng]

Hi Stefan,

On Sat, Jan 21, 2017 at 11:52 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Stefan,
>
> On 20 January 2017 at 07:26, Stefan Roese <sr@denx.de> wrote:
>> Without configuring these registers in the SPI controller, the Linux
>> MTD device driver is not able to correctly read/write to the SPI
>> NOR chip at all. In fact, the chip is not detected at all.
>>
>> Signed-off-by: Stefan Roese <sr@denx.de>
>> Cc: Simon Glass <sjg@chromium.org>
>> Cc: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>  arch/x86/cpu/baytrail/cpu.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 57 insertions(+)
>
> Can we do this in the SPI driver? It already has register definitions.

I would also do this in the SPI driver, unless it is not possible?

Regards,
Bin

[U-Boot] [PATCH v2] spi: ich: Configure SPI BIOS parameters

[Stefan Roese]

Without configuring these registers in the SPI controller, the Linux
MTD device driver is not able to correctly read/write to the SPI
NOR chip at all. In fact, the chip is not detected at all.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagan Teki <jteki@openedev.com>
---
v2:
- Moved code into the ICH SPI driver as suggested by Simon and Bin

 drivers/spi/ich.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index caf0103dc3..586b4e9024 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -18,6 +18,39 @@
 
 #include "ich.h"
 
+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 0x01 /* Write, no address */
+
+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 0x03 /* Write, address required */
+
+#define SPI_OPMENU_2 0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 0x02 /* Read, address required */
+
+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 0x00 /* Read, no address */
+
+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 0x03 /* Write, address required */
+
+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 0x00 /* Read, no address */
+
+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 0x03 /* Write, address required */
+
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
+
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 <<  8) | \
+		    (SPI_OPTYPE_3 <<  6) | (SPI_OPTYPE_2 <<  4) | \
+		    (SPI_OPTYPE_1 <<  2) | (SPI_OPTYPE_0 <<  0))
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+			  (SPI_OPMENU_5 <<  8) | (SPI_OPMENU_4 <<  0))
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+			  (SPI_OPMENU_1 <<  8) | (SPI_OPMENU_0 <<  0))
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef DEBUG_TRACE
@@ -111,6 +144,17 @@ static int ich9_can_do_33mhz(struct udevice *dev)
 	return speed == 1;
 }
 
+/*
+ * Configure SPI controller so that the Linux MTD driver can fully
+ * access the SPI NOR chip
+ */
+static void spi_controller_config(struct ich_spi_priv *ctlr)
+{
+	ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
+	ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
+	ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
+}
+
 static int ich_init_controller(struct udevice *dev,
 			       struct ich_spi_platdata *plat,
 			       struct ich_spi_priv *ctlr)
@@ -172,6 +216,13 @@ static int ich_init_controller(struct udevice *dev,
 
 	ich_set_bbar(ctlr, 0);
 
+	/*
+	 * Configure the SPI-NOR controller in a way that the Linux
+	 * MTD SPI-NOR device driver has full read-write access to
+	 * the SPI-NOR chips
+	 */
+	spi_controller_config(ctlr);
+
 	return 0;
 }
 
-- 
2.11.0

[U-Boot] [PATCH v2] spi: ich: Configure SPI BIOS parameters

[Bin Meng]

Hi Stefan,

On Mon, Jan 23, 2017 at 10:55 PM, Stefan Roese <sr@denx.de> wrote:
> Without configuring these registers in the SPI controller, the Linux
> MTD device driver is not able to correctly read/write to the SPI
> NOR chip at all. In fact, the chip is not detected at all.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Bin Meng <bmeng.cn@gmail.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Jagan Teki <jteki@openedev.com>
> ---
> v2:
> - Moved code into the ICH SPI driver as suggested by Simon and Bin
>
>  drivers/spi/ich.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 51 insertions(+)
>
> diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
> index caf0103dc3..586b4e9024 100644
> --- a/drivers/spi/ich.c
> +++ b/drivers/spi/ich.c
> @@ -18,6 +18,39 @@
>
>  #include "ich.h"
>
> +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
> +#define SPI_OPTYPE_0 0x01 /* Write, no address */
> +
> +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
> +#define SPI_OPTYPE_1 0x03 /* Write, address required */
> +
> +#define SPI_OPMENU_2 0x03 /* READ: Read Data */
> +#define SPI_OPTYPE_2 0x02 /* Read, address required */
> +
> +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
> +#define SPI_OPTYPE_3 0x00 /* Read, no address */
> +
> +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
> +#define SPI_OPTYPE_4 0x03 /* Write, address required */
> +
> +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
> +#define SPI_OPTYPE_5 0x00 /* Read, no address */
> +
> +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
> +#define SPI_OPTYPE_6 0x03 /* Write, address required */
> +
> +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
> +#define SPI_OPTYPE_7 0x02 /* Read, address required */
> +

nits: can we move these defines to ich.h?

In ich.h, I see such macros are defined using enum, not sure the
coding standard here, but I guess we may either follow the enum
defines, or use a new patch to convert enum to #defines...

> +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
> +                   (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 <<  8) | \
> +                   (SPI_OPTYPE_3 <<  6) | (SPI_OPTYPE_2 <<  4) | \
> +                   (SPI_OPTYPE_1 <<  2) | (SPI_OPTYPE_0 <<  0))
> +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
> +                         (SPI_OPMENU_5 <<  8) | (SPI_OPMENU_4 <<  0))
> +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
> +                         (SPI_OPMENU_1 <<  8) | (SPI_OPMENU_0 <<  0))
> +
>  DECLARE_GLOBAL_DATA_PTR;
>
>  #ifdef DEBUG_TRACE
> @@ -111,6 +144,17 @@ static int ich9_can_do_33mhz(struct udevice *dev)
>         return speed == 1;
>  }
>
> +/*
> + * Configure SPI controller so that the Linux MTD driver can fully
> + * access the SPI NOR chip
> + */
> +static void spi_controller_config(struct ich_spi_priv *ctlr)
> +{
> +       ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
> +       ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
> +       ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
> +}
> +
>  static int ich_init_controller(struct udevice *dev,
>                                struct ich_spi_platdata *plat,
>                                struct ich_spi_priv *ctlr)
> @@ -172,6 +216,13 @@ static int ich_init_controller(struct udevice *dev,
>
>         ich_set_bbar(ctlr, 0);
>
> +       /*
> +        * Configure the SPI-NOR controller in a way that the Linux
> +        * MTD SPI-NOR device driver has full read-write access to
> +        * the SPI-NOR chips
> +        */
> +       spi_controller_config(ctlr);
> +
>         return 0;
>  }
>
> --

Regards,
Bin

[U-Boot] [PATCH v2] spi: ich: Configure SPI BIOS parameters

[Stefan Roese]

Hi Bin,

On 04.02.2017 06:57, Bin Meng wrote:
> On Mon, Jan 23, 2017 at 10:55 PM, Stefan Roese <sr@denx.de> wrote:
>> Without configuring these registers in the SPI controller, the Linux
>> MTD device driver is not able to correctly read/write to the SPI
>> NOR chip at all. In fact, the chip is not detected at all.
>>
>> Signed-off-by: Stefan Roese <sr@denx.de>
>> Cc: Bin Meng <bmeng.cn@gmail.com>
>> Cc: Simon Glass <sjg@chromium.org>
>> Cc: Jagan Teki <jteki@openedev.com>
>> ---
>> v2:
>> - Moved code into the ICH SPI driver as suggested by Simon and Bin
>>
>>  drivers/spi/ich.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 51 insertions(+)
>>
>> diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
>> index caf0103dc3..586b4e9024 100644
>> --- a/drivers/spi/ich.c
>> +++ b/drivers/spi/ich.c
>> @@ -18,6 +18,39 @@
>>
>>  #include "ich.h"
>>
>> +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
>> +#define SPI_OPTYPE_0 0x01 /* Write, no address */
>> +
>> +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
>> +#define SPI_OPTYPE_1 0x03 /* Write, address required */
>> +
>> +#define SPI_OPMENU_2 0x03 /* READ: Read Data */
>> +#define SPI_OPTYPE_2 0x02 /* Read, address required */
>> +
>> +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
>> +#define SPI_OPTYPE_3 0x00 /* Read, no address */
>> +
>> +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
>> +#define SPI_OPTYPE_4 0x03 /* Write, address required */
>> +
>> +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
>> +#define SPI_OPTYPE_5 0x00 /* Read, no address */
>> +
>> +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
>> +#define SPI_OPTYPE_6 0x03 /* Write, address required */
>> +
>> +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
>> +#define SPI_OPTYPE_7 0x02 /* Read, address required */
>> +
>
> nits: can we move these defines to ich.h?

Sure, no problem.

> In ich.h, I see such macros are defined using enum,

You are referring to these here?

enum {
	SPI_OPCODE_TYPE_READ_NO_ADDRESS =	0,
	SPI_OPCODE_TYPE_WRITE_NO_ADDRESS =	1,
	SPI_OPCODE_TYPE_READ_WITH_ADDRESS =	2,
	SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS =	3
};

> not sure the
> coding standard here, but I guess we may either follow the enum
> defines, or use a new patch to convert enum to #defines...

I personally prefer #defines in such cases. So if nobody objects,
I can send a patch to move those enums to defines.

Thanks,
Stefan

[U-Boot] [PATCH v2] spi: ich: Configure SPI BIOS parameters

[Bin Meng]

Hi Stefan,

On Thu, Feb 9, 2017 at 12:44 AM, Stefan Roese <sr@denx.de> wrote:
> Hi Bin,
>
>
> On 04.02.2017 06:57, Bin Meng wrote:
>>
>> On Mon, Jan 23, 2017 at 10:55 PM, Stefan Roese <sr@denx.de> wrote:
>>>
>>> Without configuring these registers in the SPI controller, the Linux
>>> MTD device driver is not able to correctly read/write to the SPI
>>> NOR chip at all. In fact, the chip is not detected at all.
>>>
>>> Signed-off-by: Stefan Roese <sr@denx.de>
>>> Cc: Bin Meng <bmeng.cn@gmail.com>
>>> Cc: Simon Glass <sjg@chromium.org>
>>> Cc: Jagan Teki <jteki@openedev.com>
>>> ---
>>> v2:
>>> - Moved code into the ICH SPI driver as suggested by Simon and Bin
>>>
>>>  drivers/spi/ich.c | 51
>>> +++++++++++++++++++++++++++++++++++++++++++++++++++
>>>  1 file changed, 51 insertions(+)
>>>
>>> diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
>>> index caf0103dc3..586b4e9024 100644
>>> --- a/drivers/spi/ich.c
>>> +++ b/drivers/spi/ich.c
>>> @@ -18,6 +18,39 @@
>>>
>>>  #include "ich.h"
>>>
>>> +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
>>> +#define SPI_OPTYPE_0 0x01 /* Write, no address */
>>> +
>>> +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
>>> +#define SPI_OPTYPE_1 0x03 /* Write, address required */
>>> +
>>> +#define SPI_OPMENU_2 0x03 /* READ: Read Data */
>>> +#define SPI_OPTYPE_2 0x02 /* Read, address required */
>>> +
>>> +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
>>> +#define SPI_OPTYPE_3 0x00 /* Read, no address */
>>> +
>>> +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
>>> +#define SPI_OPTYPE_4 0x03 /* Write, address required */
>>> +
>>> +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
>>> +#define SPI_OPTYPE_5 0x00 /* Read, no address */
>>> +
>>> +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
>>> +#define SPI_OPTYPE_6 0x03 /* Write, address required */
>>> +
>>> +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
>>> +#define SPI_OPTYPE_7 0x02 /* Read, address required */
>>> +
>>
>>
>> nits: can we move these defines to ich.h?
>
>
> Sure, no problem.
>
>> In ich.h, I see such macros are defined using enum,
>
>
> You are referring to these here?
>
> enum {
>         SPI_OPCODE_TYPE_READ_NO_ADDRESS =       0,
>         SPI_OPCODE_TYPE_WRITE_NO_ADDRESS =      1,
>         SPI_OPCODE_TYPE_READ_WITH_ADDRESS =     2,
>         SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS =    3
> };

Yep

>
>> not sure the
>> coding standard here, but I guess we may either follow the enum
>> defines, or use a new patch to convert enum to #defines...
>
>
> I personally prefer #defines in such cases. So if nobody objects,
> I can send a patch to move those enums to defines.

Thanks!

Regards,
Bin