* [PATCH v10 0/5] Add support for the STM32F4 I2C @ 2017-01-19 13:25 ` M'boumba Cedric Madianga 0 siblings, 0 replies; 27+ messages in thread From: M'boumba Cedric Madianga @ 2017-01-19 13:25 UTC (permalink / raw) To: wsa, robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij, patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, u.kleine-koenig Cc: M'boumba Cedric Madianga This patchset adds support for the I2C controller embedded in STM32F4xx SoC. It enables I2C transfer in interrupt mode with Standard-mode and Fast-mode bus speed. Changes since v9: - Fix minor typo in some comments - Add some comments to explain how the driver check TRISE and CCR value have no chance of overflow Changes since v8: - Rework I2C Clock Control Register computation (Uwe) - Save register accesses as often as possible (Uwe) - Don't use mask before saving rx buffer (Uwe) - Add more comments to explain hardware way of working (Uwe) - Rename stm32f4_i2c_handle_rx_btf function by stm32f4_i2c_handle_rx_done (Uwe) - Set/Clear Ack position bit during address match phase Changes since v7: - Remove unneeded parenthesis in some macro definitions (Uwe) - Fix some typo (s/KhzkHZ, s/PEC/POC) (Uwe) - Fix alignment issues in some structures declaration (Uwe) - Clarify comments to argue i2c_timing values chosen (Uwe) - Raise an error if parent clk rate is out of scope during I2C hw config (Uwe) - Use dev_dbg instead of dev_err message when I2C bus is busy (Uwe) - Add more comments about stuff done by stm32f4_i2c_handle_rx_btf() (Uwe) - Simplify stm32f4_i2c_isr_error() routine implementation by removing possible status checking (Uwe) - Rework stm32f4_i2c_isr_error() routine by removing the loop to check which status occured (Uwe) - Add open-drain property for SCL pins (Uwe) - Rework unneeded mul_ccr field from i2c_timing structure - Remove min_ccr field from i2c_timing structure as default scl_period is chosen to have a correct minimal ccr value - Execute hw_config once during probe - Remove soft_reset after an I2C error as all errors are now handled and hw_config is done once during probe - Generate STOP by software when Acknowledge failure occurs - Set the max speed mode for I2C pins - Add bias-disable property for I2C pins - Use intrinsic limitation of APB bus to set I2C max input clk Changes since v6: - Add commit message for the patches in defconfig, .dtsi and .dts files (Alex) - Order I2C instance base address in .dtsi file (Alex) - Add commit message for the patch in stm32429i-eval.dts (Alex) - Add link to the STM32F4 Soc ref manual where I2C device is described (Uwe) - Use more usal way to define constants with several lines (Uwe) - Remove rate variable from stm32f4_i2c_timings as it is not used (Uwe) - Remove irq variable from stm32f4_i2c_dev struct are they are only needed during probe (Uwe) - Add comment from datasheet to explain stm32f4_i2c_timings values (Uwe) - Rework i2c soft_reset implementation (Uwe) - Replace "it" by "irq" as it is a more usual abbreviation for interrupt (Uwe) - Add comment from datasheet to explain periph clk freq calculation (Uwe) - Use DIV_ROUND_UP instead of plain division when required (Uwe) - Add comment from datasheet to explain timing rise calculation (Uwe) - Rework timing rise calculation by using shorter computation (Uwe) - Remove (u8) cast when reading I2C data register (Uwe) - Rework isr_event routine to handle several events during one call of the routine (Uwe) - Precise which type of irq is failed when a irq request error occurs (Uwe) - Use devm_request_irq() instead of devm_request_threaded_irq() to avoid spurious evt irq when clearing status registers in threaded context Changes since v5: - Change commit header from "ARM: dts:" to "ARM: dts: stm32:" (Alex) - Change commit header from "ARM: configs:" to "ARM: configs: stm32:" (Alex) - Fix warnings due to variable set but unused (Wolfram) - Remove double space in Kconfig (Wolfram) - Fix warning due to bad type parameter when using clamp() function (build-bot) Changes since v4: - Use clamp() function to use a value in a given range as it was missed in V4 Changes since v3 after Wolfram's review: - Add COMPILE_TEST flag in Kconfig - Use correct driver name in Kconfig i.e i2c-stm32f4 instead of i2c-st - Use more comprehensible name stm32f4_i2c_msg for client specific data - Don't store reset control node as just needed in probe - Use clamp() function to test value between 2 ranges - Use new "i2c_8bit_addr_from_msg() function to build I2C address - Don't write error messages for timeout - Remove error message when i2c_add_adapter() fails as it is already handled by the i2c core driver Changes since v2: - remove interrupt configuration management from DT - remove FIFO configuration management from DT except threshold as it is very hard to handle it in the driver due to many possible combinations according to burst and bus width - update DMA client message in DT documentation file - specify the order to be used to set per-channel DMA interrupts in the DT - remove unused enumerations for channel and request ids - keep as soon as possible 80 lines char for more readability - replace unsigned int by u32 - return error if burst is not supported in stm32_dma_get_burst() - return error if bus_width is not supported in stm32_dma_get_width() - add FIFO configuration management inside the driver except for threshold - add interrupt configuration management inside the driver - rework stm32_dma_chan_irq() to handle error interrupt in one way - rework stm32_dma_set_xfer_param() to be easier to read - update stm32_dma_tx_status() to always return status from dma_cookie_status() - disable clk if we don't manage to stop the DMA channel during channel resources allocation - set driver as built-in as DMA will be required by other built-in driver Changes since v1: - use compatible st,stm32f4-i2c instead of st,i2c-stm32f4 (Rob) - fix typo s/enmpty/empty (Maxime) - use one function to handle TX fifo empty and byte xfer finished IT (Maxime) - set duty cycle in timing struct in Fast mode - Rework clock management (call prepare/unprepare at probe and remove, call clk_enable/clk_disable for each I2C transfer) M'boumba Cedric Madianga (5): dt-bindings: Document the STM32 I2C bindings i2c: Add STM32F4 I2C driver ARM: dts: stm32: Add I2C1 support for STM32F429 SoC ARM: dts: stm32: Add I2C1 support for STM32429 eval board ARM: configs: stm32: Add I2C support for STM32 defconfig .../devicetree/bindings/i2c/i2c-stm32.txt | 33 + arch/arm/boot/dts/stm32429i-eval.dts | 6 + arch/arm/boot/dts/stm32f429.dtsi | 23 + arch/arm/configs/stm32_defconfig | 3 + drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-stm32f4.c | 897 +++++++++++++++++++++ 7 files changed, 973 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-stm32.txt create mode 100644 drivers/i2c/busses/i2c-stm32f4.c -- 1.9.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v10 0/5] Add support for the STM32F4 I2C @ 2017-01-19 13:25 ` M'boumba Cedric Madianga 0 siblings, 0 replies; 27+ messages in thread From: M'boumba Cedric Madianga @ 2017-01-19 13:25 UTC (permalink / raw) To: linux-arm-kernel This patchset adds support for the I2C controller embedded in STM32F4xx SoC. It enables I2C transfer in interrupt mode with Standard-mode and Fast-mode bus speed. Changes since v9: - Fix minor typo in some comments - Add some comments to explain how the driver check TRISE and CCR value have no chance of overflow Changes since v8: - Rework I2C Clock Control Register computation (Uwe) - Save register accesses as often as possible (Uwe) - Don't use mask before saving rx buffer (Uwe) - Add more comments to explain hardware way of working (Uwe) - Rename stm32f4_i2c_handle_rx_btf function by stm32f4_i2c_handle_rx_done (Uwe) - Set/Clear Ack position bit during address match phase Changes since v7: - Remove unneeded parenthesis in some macro definitions (Uwe) - Fix some typo (s/KhzkHZ, s/PEC/POC) (Uwe) - Fix alignment issues in some structures declaration (Uwe) - Clarify comments to argue i2c_timing values chosen (Uwe) - Raise an error if parent clk rate is out of scope during I2C hw config (Uwe) - Use dev_dbg instead of dev_err message when I2C bus is busy (Uwe) - Add more comments about stuff done by stm32f4_i2c_handle_rx_btf() (Uwe) - Simplify stm32f4_i2c_isr_error() routine implementation by removing possible status checking (Uwe) - Rework stm32f4_i2c_isr_error() routine by removing the loop to check which status occured (Uwe) - Add open-drain property for SCL pins (Uwe) - Rework unneeded mul_ccr field from i2c_timing structure - Remove min_ccr field from i2c_timing structure as default scl_period is chosen to have a correct minimal ccr value - Execute hw_config once during probe - Remove soft_reset after an I2C error as all errors are now handled and hw_config is done once during probe - Generate STOP by software when Acknowledge failure occurs - Set the max speed mode for I2C pins - Add bias-disable property for I2C pins - Use intrinsic limitation of APB bus to set I2C max input clk Changes since v6: - Add commit message for the patches in defconfig, .dtsi and .dts files (Alex) - Order I2C instance base address in .dtsi file (Alex) - Add commit message for the patch in stm32429i-eval.dts (Alex) - Add link to the STM32F4 Soc ref manual where I2C device is described (Uwe) - Use more usal way to define constants with several lines (Uwe) - Remove rate variable from stm32f4_i2c_timings as it is not used (Uwe) - Remove irq variable from stm32f4_i2c_dev struct are they are only needed during probe (Uwe) - Add comment from datasheet to explain stm32f4_i2c_timings values (Uwe) - Rework i2c soft_reset implementation (Uwe) - Replace "it" by "irq" as it is a more usual abbreviation for interrupt (Uwe) - Add comment from datasheet to explain periph clk freq calculation (Uwe) - Use DIV_ROUND_UP instead of plain division when required (Uwe) - Add comment from datasheet to explain timing rise calculation (Uwe) - Rework timing rise calculation by using shorter computation (Uwe) - Remove (u8) cast when reading I2C data register (Uwe) - Rework isr_event routine to handle several events during one call of the routine (Uwe) - Precise which type of irq is failed when a irq request error occurs (Uwe) - Use devm_request_irq() instead of devm_request_threaded_irq() to avoid spurious evt irq when clearing status registers in threaded context Changes since v5: - Change commit header from "ARM: dts:" to "ARM: dts: stm32:" (Alex) - Change commit header from "ARM: configs:" to "ARM: configs: stm32:" (Alex) - Fix warnings due to variable set but unused (Wolfram) - Remove double space in Kconfig (Wolfram) - Fix warning due to bad type parameter when using clamp() function (build-bot) Changes since v4: - Use clamp() function to use a value in a given range as it was missed in V4 Changes since v3 after Wolfram's review: - Add COMPILE_TEST flag in Kconfig - Use correct driver name in Kconfig i.e i2c-stm32f4 instead of i2c-st - Use more comprehensible name stm32f4_i2c_msg for client specific data - Don't store reset control node as just needed in probe - Use clamp() function to test value between 2 ranges - Use new "i2c_8bit_addr_from_msg() function to build I2C address - Don't write error messages for timeout - Remove error message when i2c_add_adapter() fails as it is already handled by the i2c core driver Changes since v2: - remove interrupt configuration management from DT - remove FIFO configuration management from DT except threshold as it is very hard to handle it in the driver due to many possible combinations according to burst and bus width - update DMA client message in DT documentation file - specify the order to be used to set per-channel DMA interrupts in the DT - remove unused enumerations for channel and request ids - keep as soon as possible 80 lines char for more readability - replace unsigned int by u32 - return error if burst is not supported in stm32_dma_get_burst() - return error if bus_width is not supported in stm32_dma_get_width() - add FIFO configuration management inside the driver except for threshold - add interrupt configuration management inside the driver - rework stm32_dma_chan_irq() to handle error interrupt in one way - rework stm32_dma_set_xfer_param() to be easier to read - update stm32_dma_tx_status() to always return status from dma_cookie_status() - disable clk if we don't manage to stop the DMA channel during channel resources allocation - set driver as built-in as DMA will be required by other built-in driver Changes since v1: - use compatible st,stm32f4-i2c instead of st,i2c-stm32f4 (Rob) - fix typo s/enmpty/empty (Maxime) - use one function to handle TX fifo empty and byte xfer finished IT (Maxime) - set duty cycle in timing struct in Fast mode - Rework clock management (call prepare/unprepare at probe and remove, call clk_enable/clk_disable for each I2C transfer) M'boumba Cedric Madianga (5): dt-bindings: Document the STM32 I2C bindings i2c: Add STM32F4 I2C driver ARM: dts: stm32: Add I2C1 support for STM32F429 SoC ARM: dts: stm32: Add I2C1 support for STM32429 eval board ARM: configs: stm32: Add I2C support for STM32 defconfig .../devicetree/bindings/i2c/i2c-stm32.txt | 33 + arch/arm/boot/dts/stm32429i-eval.dts | 6 + arch/arm/boot/dts/stm32f429.dtsi | 23 + arch/arm/configs/stm32_defconfig | 3 + drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-stm32f4.c | 897 +++++++++++++++++++++ 7 files changed, 973 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-stm32.txt create mode 100644 drivers/i2c/busses/i2c-stm32f4.c -- 1.9.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v10 1/5] dt-bindings: Document the STM32 I2C bindings 2017-01-19 13:25 ` M'boumba Cedric Madianga @ 2017-01-19 13:25 ` M'boumba Cedric Madianga -1 siblings, 0 replies; 27+ messages in thread From: M'boumba Cedric Madianga @ 2017-01-19 13:25 UTC (permalink / raw) To: wsa, robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij, patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, u.kleine-koenig Cc: M'boumba Cedric Madianga This patch adds documentation of device tree bindings for the STM32 I2C controller. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Acked-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/i2c/i2c-stm32.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-stm32.txt diff --git a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt new file mode 100644 index 0000000..78eaf7b --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt @@ -0,0 +1,33 @@ +* I2C controller embedded in STMicroelectronics STM32 I2C platform + +Required properties : +- compatible : Must be "st,stm32f4-i2c" +- reg : Offset and length of the register set for the device +- interrupts : Must contain the interrupt id for I2C event and then the + interrupt id for I2C error. +- resets: Must contain the phandle to the reset controller. +- clocks: Must contain the input clock of the I2C instance. +- A pinctrl state named "default" must be defined to set pins in mode of + operation for I2C transfer +- #address-cells = <1>; +- #size-cells = <0>; + +Optional properties : +- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, + the default 100 kHz frequency will be used. As only Normal and Fast modes + are supported, possible values are 100000 and 400000. + +Example : + + i2c@40005400 { + compatible = "st,stm32f4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc 277>; + clocks = <&rcc 0 149>; + pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>; + pinctrl-names = "default"; + }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v10 1/5] dt-bindings: Document the STM32 I2C bindings @ 2017-01-19 13:25 ` M'boumba Cedric Madianga 0 siblings, 0 replies; 27+ messages in thread From: M'boumba Cedric Madianga @ 2017-01-19 13:25 UTC (permalink / raw) To: linux-arm-kernel This patch adds documentation of device tree bindings for the STM32 I2C controller. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Acked-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/i2c/i2c-stm32.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-stm32.txt diff --git a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt new file mode 100644 index 0000000..78eaf7b --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt @@ -0,0 +1,33 @@ +* I2C controller embedded in STMicroelectronics STM32 I2C platform + +Required properties : +- compatible : Must be "st,stm32f4-i2c" +- reg : Offset and length of the register set for the device +- interrupts : Must contain the interrupt id for I2C event and then the + interrupt id for I2C error. +- resets: Must contain the phandle to the reset controller. +- clocks: Must contain the input clock of the I2C instance. +- A pinctrl state named "default" must be defined to set pins in mode of + operation for I2C transfer +- #address-cells = <1>; +- #size-cells = <0>; + +Optional properties : +- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, + the default 100 kHz frequency will be used. As only Normal and Fast modes + are supported, possible values are 100000 and 400000. + +Example : + + i2c at 40005400 { + compatible = "st,stm32f4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc 277>; + clocks = <&rcc 0 149>; + pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>; + pinctrl-names = "default"; + }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v10 1/5] dt-bindings: Document the STM32 I2C bindings 2017-01-19 13:25 ` M'boumba Cedric Madianga @ 2017-01-25 20:24 ` Wolfram Sang -1 siblings, 0 replies; 27+ messages in thread From: Wolfram Sang @ 2017-01-25 20:24 UTC (permalink / raw) To: M'boumba Cedric Madianga Cc: robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij, patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, u.kleine-koenig [-- Attachment #1: Type: text/plain, Size: 317 bytes --] On Thu, Jan 19, 2017 at 02:25:12PM +0100, M'boumba Cedric Madianga wrote: > This patch adds documentation of device tree bindings for the STM32 I2C > controller. > > Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> > Acked-by: Rob Herring <robh@kernel.org> Applied to for-next, thanks! [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v10 1/5] dt-bindings: Document the STM32 I2C bindings @ 2017-01-25 20:24 ` Wolfram Sang 0 siblings, 0 replies; 27+ messages in thread From: Wolfram Sang @ 2017-01-25 20:24 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jan 19, 2017 at 02:25:12PM +0100, M'boumba Cedric Madianga wrote: > This patch adds documentation of device tree bindings for the STM32 I2C > controller. > > Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> > Acked-by: Rob Herring <robh@kernel.org> Applied to for-next, thanks! -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 833 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170125/38224e44/attachment.sig> ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v10 2/5] i2c: Add STM32F4 I2C driver 2017-01-19 13:25 ` M'boumba Cedric Madianga @ 2017-01-19 13:25 ` M'boumba Cedric Madianga -1 siblings, 0 replies; 27+ messages in thread From: M'boumba Cedric Madianga @ 2017-01-19 13:25 UTC (permalink / raw) To: wsa, robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij, patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, u.kleine-koenig Cc: M'boumba Cedric Madianga This patch adds support for the STM32F4 I2C controller. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> --- drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-stm32f4.c | 897 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 908 insertions(+) create mode 100644 drivers/i2c/busses/i2c-stm32f4.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 0cdc844..2719208 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -886,6 +886,16 @@ config I2C_ST This driver can also be built as module. If so, the module will be called i2c-st. +config I2C_STM32F4 + tristate "STMicroelectronics STM32F4 I2C support" + depends on ARCH_STM32 || COMPILE_TEST + help + Enable this option to add support for STM32 I2C controller embedded + in STM32F4 SoCs. + + This driver can also be built as module. If so, the module + will be called i2c-stm32f4. + config I2C_STU300 tristate "ST Microelectronics DDC I2C interface" depends on MACH_U300 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 1c1bac8..a2c6ff5 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -85,6 +85,7 @@ obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o obj-$(CONFIG_I2C_ST) += i2c-st.o +obj-$(CONFIG_I2C_STM32F4) += i2c-stm32f4.o obj-$(CONFIG_I2C_STU300) += i2c-stu300.o obj-$(CONFIG_I2C_SUN6I_P2WI) += i2c-sun6i-p2wi.o obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o diff --git a/drivers/i2c/busses/i2c-stm32f4.c b/drivers/i2c/busses/i2c-stm32f4.c new file mode 100644 index 0000000..f9dd7e8 --- /dev/null +++ b/drivers/i2c/busses/i2c-stm32f4.c @@ -0,0 +1,897 @@ +/* + * Driver for STMicroelectronics STM32 I2C controller + * + * This I2C controller is described in the STM32F429/439 Soc reference manual. + * Please see below a link to the documentation: + * http://www.st.com/resource/en/reference_manual/DM00031020.pdf + * + * Copyright (C) M'boumba Cedric Madianga 2016 + * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> + * + * This driver is based on i2c-st.c + * + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/i2c.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/reset.h> + +/* STM32F4 I2C offset registers */ +#define STM32F4_I2C_CR1 0x00 +#define STM32F4_I2C_CR2 0x04 +#define STM32F4_I2C_DR 0x10 +#define STM32F4_I2C_SR1 0x14 +#define STM32F4_I2C_SR2 0x18 +#define STM32F4_I2C_CCR 0x1C +#define STM32F4_I2C_TRISE 0x20 +#define STM32F4_I2C_FLTR 0x24 + +/* STM32F4 I2C control 1*/ +#define STM32F4_I2C_CR1_POS BIT(11) +#define STM32F4_I2C_CR1_ACK BIT(10) +#define STM32F4_I2C_CR1_STOP BIT(9) +#define STM32F4_I2C_CR1_START BIT(8) +#define STM32F4_I2C_CR1_PE BIT(0) + +/* STM32F4 I2C control 2 */ +#define STM32F4_I2C_CR2_FREQ_MASK GENMASK(5, 0) +#define STM32F4_I2C_CR2_FREQ(n) ((n) & STM32F4_I2C_CR2_FREQ_MASK) +#define STM32F4_I2C_CR2_ITBUFEN BIT(10) +#define STM32F4_I2C_CR2_ITEVTEN BIT(9) +#define STM32F4_I2C_CR2_ITERREN BIT(8) +#define STM32F4_I2C_CR2_IRQ_MASK (STM32F4_I2C_CR2_ITBUFEN | \ + STM32F4_I2C_CR2_ITEVTEN | \ + STM32F4_I2C_CR2_ITERREN) + +/* STM32F4 I2C Status 1 */ +#define STM32F4_I2C_SR1_AF BIT(10) +#define STM32F4_I2C_SR1_ARLO BIT(9) +#define STM32F4_I2C_SR1_BERR BIT(8) +#define STM32F4_I2C_SR1_TXE BIT(7) +#define STM32F4_I2C_SR1_RXNE BIT(6) +#define STM32F4_I2C_SR1_BTF BIT(2) +#define STM32F4_I2C_SR1_ADDR BIT(1) +#define STM32F4_I2C_SR1_SB BIT(0) +#define STM32F4_I2C_SR1_ITEVTEN_MASK (STM32F4_I2C_SR1_BTF | \ + STM32F4_I2C_SR1_ADDR | \ + STM32F4_I2C_SR1_SB) +#define STM32F4_I2C_SR1_ITBUFEN_MASK (STM32F4_I2C_SR1_TXE | \ + STM32F4_I2C_SR1_RXNE) +#define STM32F4_I2C_SR1_ITERREN_MASK (STM32F4_I2C_SR1_AF | \ + STM32F4_I2C_SR1_ARLO | \ + STM32F4_I2C_SR1_BERR) + +/* STM32F4 I2C Status 2 */ +#define STM32F4_I2C_SR2_BUSY BIT(1) + +/* STM32F4 I2C Control Clock */ +#define STM32F4_I2C_CCR_CCR_MASK GENMASK(11, 0) +#define STM32F4_I2C_CCR_CCR(n) ((n) & STM32F4_I2C_CCR_CCR_MASK) +#define STM32F4_I2C_CCR_FS BIT(15) +#define STM32F4_I2C_CCR_DUTY BIT(14) + +/* STM32F4 I2C Trise */ +#define STM32F4_I2C_TRISE_VALUE_MASK GENMASK(5, 0) +#define STM32F4_I2C_TRISE_VALUE(n) ((n) & STM32F4_I2C_TRISE_VALUE_MASK) + +#define STM32F4_I2C_MIN_STANDARD_FREQ 2U +#define STM32F4_I2C_MIN_FAST_FREQ 6U +#define STM32F4_I2C_MAX_FREQ 46U +#define HZ_TO_MHZ 1000000 + +enum stm32f4_i2c_speed { + STM32F4_I2C_SPEED_STANDARD, /* 100 kHz */ + STM32F4_I2C_SPEED_FAST, /* 400 kHz */ + STM32F4_I2C_SPEED_END, +}; + +/** + * struct stm32f4_i2c_msg - client specific data + * @addr: 8-bit slave addr, including r/w bit + * @count: number of bytes to be transferred + * @buf: data buffer + * @result: result of the transfer + * @stop: last I2C msg to be sent, i.e. STOP to be generated + */ +struct stm32f4_i2c_msg { + u8 addr; + u32 count; + u8 *buf; + int result; + bool stop; +}; + +/** + * struct stm32f4_i2c_dev - private data of the controller + * @adap: I2C adapter for this controller + * @dev: device for this controller + * @base: virtual memory area + * @complete: completion of I2C message + * @clk: hw i2c clock + * @speed: I2C clock frequency of the controller. Standard or Fast are supported + * @parent_rate: I2C clock parent rate in MHz + * @msg: I2C transfer information + */ +struct stm32f4_i2c_dev { + struct i2c_adapter adap; + struct device *dev; + void __iomem *base; + struct completion complete; + struct clk *clk; + int speed; + int parent_rate; + struct stm32f4_i2c_msg msg; +}; + +static inline void stm32f4_i2c_set_bits(void __iomem *reg, u32 mask) +{ + writel_relaxed(readl_relaxed(reg) | mask, reg); +} + +static inline void stm32f4_i2c_clr_bits(void __iomem *reg, u32 mask) +{ + writel_relaxed(readl_relaxed(reg) & ~mask, reg); +} + +static void stm32f4_i2c_disable_irq(struct stm32f4_i2c_dev *i2c_dev) +{ + void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; + + stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_IRQ_MASK); +} + +static int stm32f4_i2c_set_periph_clk_freq(struct stm32f4_i2c_dev *i2c_dev) +{ + u32 freq; + u32 cr2 = 0; + + i2c_dev->parent_rate = clk_get_rate(i2c_dev->clk); + freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ); + + if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) { + /* + * To reach 100 kHz, the parent clk frequency should be between + * a minimum value of 2 MHz and a maximum value of 46 MHz due + * to hardware limitation + */ + if (freq < STM32F4_I2C_MIN_STANDARD_FREQ || + freq > STM32F4_I2C_MAX_FREQ) { + dev_err(i2c_dev->dev, + "bad parent clk freq for standard mode\n"); + return -EINVAL; + } + } else { + /* + * To be as close as possible to 400 kHz, the parent clk + * frequency should be between a minimum value of 6 MHz and a + * maximum value of 46 MHz due to hardware limitation + */ + if (freq < STM32F4_I2C_MIN_FAST_FREQ || + freq > STM32F4_I2C_MAX_FREQ) { + dev_err(i2c_dev->dev, + "bad parent clk freq for fast mode\n"); + return -EINVAL; + } + } + + cr2 |= STM32F4_I2C_CR2_FREQ(freq); + writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); + + return 0; +} + +static void stm32f4_i2c_set_rise_time(struct stm32f4_i2c_dev *i2c_dev) +{ + u32 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ); + u32 trise; + + /* + * These bits must be programmed with the maximum SCL rise time given in + * the I2C bus specification, incremented by 1. + * + * In standard mode, the maximum allowed SCL rise time is 1000 ns. + * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to + * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be + * programmed with 0x9. (1000 ns / 125 ns + 1) + * So, for I2C standard mode TRISE = FREQ[5:0] + 1 + * + * In fast mode, the maximum allowed SCL rise time is 300 ns. + * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to + * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be + * programmed with 0x3. (300 ns / 125 ns + 1) + * So, for I2C fast mode TRISE = FREQ[5:0] * 300 / 1000 + 1 + * + * Function stm32f4_i2c_set_periph_clk_freq made sure that parent rate + * is not higher than 46 MHz . As a result trise is at most 4 bits wide + * and so fits into the TRISE bits [5:0]. + */ + if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) + trise = freq + 1; + else + trise = freq * 3 / 10 + 1; + + writel_relaxed(STM32F4_I2C_TRISE_VALUE(trise), + i2c_dev->base + STM32F4_I2C_TRISE); +} + +static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev) +{ + u32 val; + u32 ccr = 0; + + if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) { + /* + * In standard mode: + * t_scl_high = t_scl_low = CCR * I2C parent clk period + * So to reach 100 kHz, we have: + * CCR = I2C parent rate / 100 kHz >> 1 + * + * For example with parent rate = 2 MHz: + * CCR = 2000000 / (100000 << 1) = 10 + * t_scl_high = t_scl_low = 10 * (1 / 2000000) = 5000 ns + * t_scl_high + t_scl_low = 10000 ns so 100 kHz is reached + * + * Function stm32f4_i2c_set_periph_clk_freq made sure that + * parent rate is not higher than 46 MHz . As a result val + * is at most 8 bits wide and so fits into the CCR bits [11:0]. + */ + val = i2c_dev->parent_rate / (100000 << 1); + } else { + /* + * In fast mode, we compute CCR with duty = 0 as with low + * frequencies we are not able to reach 400 kHz. + * In that case: + * t_scl_high = CCR * I2C parent clk period + * t_scl_low = 2 * CCR * I2C parent clk period + * So, CCR = I2C parent rate / (400 kHz * 3) + * + * For example with parent rate = 6 MHz: + * CCR = 6000000 / (400000 * 3) = 5 + * t_scl_high = 5 * (1 / 6000000) = 833 ns > 600 ns + * t_scl_low = 2 * 5 * (1 / 6000000) = 1667 ns > 1300 ns + * t_scl_high + t_scl_low = 2500 ns so 400 kHz is reached + * + * Function stm32f4_i2c_set_periph_clk_freq made sure that + * parent rate is not higher than 46 MHz . As a result val + * is at most 6 bits wide and so fits into the CCR bits [11:0]. + */ + val = DIV_ROUND_UP(i2c_dev->parent_rate, 400000 * 3); + + /* Select Fast mode */ + ccr |= STM32F4_I2C_CCR_FS; + } + + ccr |= STM32F4_I2C_CCR_CCR(val); + writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR); +} + +/** + * stm32f4_i2c_hw_config() - Prepare I2C block + * @i2c_dev: Controller's private data + */ +static int stm32f4_i2c_hw_config(struct stm32f4_i2c_dev *i2c_dev) +{ + int ret; + + ret = stm32f4_i2c_set_periph_clk_freq(i2c_dev); + if (ret) + return ret; + + stm32f4_i2c_set_rise_time(i2c_dev); + + stm32f4_i2c_set_speed_mode(i2c_dev); + + /* Enable I2C */ + writel_relaxed(STM32F4_I2C_CR1_PE, i2c_dev->base + STM32F4_I2C_CR1); + + return 0; +} + +static int stm32f4_i2c_wait_free_bus(struct stm32f4_i2c_dev *i2c_dev) +{ + u32 status; + int ret; + + ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F4_I2C_SR2, + status, + !(status & STM32F4_I2C_SR2_BUSY), + 10, 1000); + if (ret) { + dev_dbg(i2c_dev->dev, "bus not free\n"); + ret = -EBUSY; + } + + return ret; +} + +/** + * stm32f4_i2c_write_ byte() - Write a byte in the data register + * @i2c_dev: Controller's private data + * @byte: Data to write in the register + */ +static void stm32f4_i2c_write_byte(struct stm32f4_i2c_dev *i2c_dev, u8 byte) +{ + writel_relaxed(byte, i2c_dev->base + STM32F4_I2C_DR); +} + +/** + * stm32f4_i2c_write_msg() - Fill the data register in write mode + * @i2c_dev: Controller's private data + * + * This function fills the data register with I2C transfer buffer + */ +static void stm32f4_i2c_write_msg(struct stm32f4_i2c_dev *i2c_dev) +{ + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + + stm32f4_i2c_write_byte(i2c_dev, *msg->buf++); + msg->count--; +} + +static void stm32f4_i2c_read_msg(struct stm32f4_i2c_dev *i2c_dev) +{ + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + u32 rbuf; + + rbuf = readl_relaxed(i2c_dev->base + STM32F4_I2C_DR); + *msg->buf++ = rbuf; + msg->count--; +} + +static void stm32f4_i2c_terminate_xfer(struct stm32f4_i2c_dev *i2c_dev) +{ + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; + + stm32f4_i2c_disable_irq(i2c_dev); + + reg = i2c_dev->base + STM32F4_I2C_CR1; + if (msg->stop) + stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); + else + stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); + + complete(&i2c_dev->complete); +} + +/** + * stm32f4_i2c_handle_write() - Handle FIFO empty interrupt in case of write + * @i2c_dev: Controller's private data + */ +static void stm32f4_i2c_handle_write(struct stm32f4_i2c_dev *i2c_dev) +{ + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; + + if (msg->count) { + stm32f4_i2c_write_msg(i2c_dev); + if (!msg->count) { + /* + * Disable buffer interrupts for RX not empty and TX + * empty events + */ + stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN); + } + } else { + stm32f4_i2c_terminate_xfer(i2c_dev); + } +} + +/** + * stm32f4_i2c_handle_read() - Handle FIFO empty interrupt in case of read + * @i2c_dev: Controller's private data + * + * This function is called when a new data is received in data register + */ +static void stm32f4_i2c_handle_read(struct stm32f4_i2c_dev *i2c_dev) +{ + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; + + switch (msg->count) { + case 1: + stm32f4_i2c_disable_irq(i2c_dev); + stm32f4_i2c_read_msg(i2c_dev); + complete(&i2c_dev->complete); + break; + /* + * For 2-byte reception, 3-byte reception and for Data N-2, N-1 and N + * for N-byte reception with N > 3, we do not have to read the data + * register when RX not empty event occurs as we have to wait for byte + * transferred finished event before reading data. + * So, here we just disable buffer interrupt in order to avoid another + * system preemption due to RX not empty event. + */ + case 2: + case 3: + stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN); + break; + /* + * For N byte reception with N > 3 we directly read data register + * until N-2 data. + */ + default: + stm32f4_i2c_read_msg(i2c_dev); + } +} + +/** + * stm32f4_i2c_handle_rx_done() - Handle byte transfer finished interrupt + * in case of read + * @i2c_dev: Controller's private data + * + * This function is called when a new data is received in the shift register + * but data register has not been read yet. + */ +static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev) +{ + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + void __iomem *reg; + u32 mask; + int i; + + switch (msg->count) { + case 2: + /* + * In order to correctly send the Stop or Repeated Start + * condition on the I2C bus, the STOP/START bit has to be set + * before reading the last two bytes (data N-1 and N). + * After that, we could read the last two bytes, disable + * remaining interrupts and notify the end of xfer to the + * client + */ + reg = i2c_dev->base + STM32F4_I2C_CR1; + if (msg->stop) + stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); + else + stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); + + for (i = 2; i > 0; i--) + stm32f4_i2c_read_msg(i2c_dev); + + reg = i2c_dev->base + STM32F4_I2C_CR2; + mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN; + stm32f4_i2c_clr_bits(reg, mask); + + complete(&i2c_dev->complete); + break; + case 3: + /* + * In order to correctly generate the NACK pulse after the last + * received data byte, we have to enable NACK before reading N-2 + * data + */ + reg = i2c_dev->base + STM32F4_I2C_CR1; + stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR1_ACK); + stm32f4_i2c_read_msg(i2c_dev); + break; + default: + stm32f4_i2c_read_msg(i2c_dev); + } +} + +/** + * stm32f4_i2c_handle_rx_addr() - Handle address matched interrupt in case of + * master receiver + * @i2c_dev: Controller's private data + */ +static void stm32f4_i2c_handle_rx_addr(struct stm32f4_i2c_dev *i2c_dev) +{ + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + u32 cr1; + + switch (msg->count) { + case 0: + stm32f4_i2c_terminate_xfer(i2c_dev); + + /* Clear ADDR flag */ + readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); + break; + case 1: + /* + * Single byte reception: + * Enable NACK and reset POS (Acknowledge position). + * Then, clear ADDR flag and set STOP or RepSTART. + * In that way, the NACK and STOP or RepStart pulses will be + * sent as soon as the byte will be received in shift register + */ + cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); + cr1 &= ~(STM32F4_I2C_CR1_ACK | STM32F4_I2C_CR1_POS); + writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); + + readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); + + if (msg->stop) + cr1 |= STM32F4_I2C_CR1_STOP; + else + cr1 |= STM32F4_I2C_CR1_START; + writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); + break; + case 2: + /* + * 2-byte reception: + * Enable NACK, set POS (NACK position) and clear ADDR flag. + * In that way, NACK will be sent for the next byte which will + * be received in the shift register instead of the current + * one. + */ + cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); + cr1 &= ~STM32F4_I2C_CR1_ACK; + cr1 |= STM32F4_I2C_CR1_POS; + writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); + + readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); + break; + + default: + /* + * N-byte reception: + * Enable ACK, reset POS (ACK postion) and clear ADDR flag. + * In that way, ACK will be sent as soon as the current byte + * will be received in the shift register + */ + cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); + cr1 |= STM32F4_I2C_CR1_ACK; + cr1 &= ~STM32F4_I2C_CR1_POS; + writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); + + readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); + break; + } +} + +/** + * stm32f4_i2c_isr_event() - Interrupt routine for I2C bus event + * @irq: interrupt number + * @data: Controller's private data + */ +static irqreturn_t stm32f4_i2c_isr_event(int irq, void *data) +{ + struct stm32f4_i2c_dev *i2c_dev = data; + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + u32 possible_status = STM32F4_I2C_SR1_ITEVTEN_MASK; + u32 status, ien, event, cr2; + + cr2 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR2); + ien = cr2 & STM32F4_I2C_CR2_IRQ_MASK; + + /* Update possible_status if buffer interrupt is enabled */ + if (ien & STM32F4_I2C_CR2_ITBUFEN) + possible_status |= STM32F4_I2C_SR1_ITBUFEN_MASK; + + status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1); + event = status & possible_status; + if (!event) { + dev_dbg(i2c_dev->dev, + "spurious evt irq (status=0x%08x, ien=0x%08x)\n", + status, ien); + return IRQ_NONE; + } + + /* Start condition generated */ + if (event & STM32F4_I2C_SR1_SB) + stm32f4_i2c_write_byte(i2c_dev, msg->addr); + + /* I2C Address sent */ + if (event & STM32F4_I2C_SR1_ADDR) { + if (msg->addr & I2C_M_RD) + stm32f4_i2c_handle_rx_addr(i2c_dev); + else + readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); + + /* + * Enable buffer interrupts for RX not empty and TX empty + * events + */ + cr2 |= STM32F4_I2C_CR2_ITBUFEN; + writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); + } + + /* TX empty */ + if ((event & STM32F4_I2C_SR1_TXE) && !(msg->addr & I2C_M_RD)) + stm32f4_i2c_handle_write(i2c_dev); + + /* RX not empty */ + if ((event & STM32F4_I2C_SR1_RXNE) && (msg->addr & I2C_M_RD)) + stm32f4_i2c_handle_read(i2c_dev); + + /* + * The BTF (Byte Transfer finished) event occurs when: + * - in reception : a new byte is received in the shift register + * but the previous byte has not been read yet from data register + * - in transmission: a new byte should be sent but the data register + * has not been written yet + */ + if (event & STM32F4_I2C_SR1_BTF) { + if (msg->addr & I2C_M_RD) + stm32f4_i2c_handle_rx_done(i2c_dev); + else + stm32f4_i2c_handle_write(i2c_dev); + } + + return IRQ_HANDLED; +} + +/** + * stm32f4_i2c_isr_error() - Interrupt routine for I2C bus error + * @irq: interrupt number + * @data: Controller's private data + */ +static irqreturn_t stm32f4_i2c_isr_error(int irq, void *data) +{ + struct stm32f4_i2c_dev *i2c_dev = data; + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + void __iomem *reg; + u32 status; + + status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1); + + /* Arbitration lost */ + if (status & STM32F4_I2C_SR1_ARLO) { + status &= ~STM32F4_I2C_SR1_ARLO; + writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); + msg->result = -EAGAIN; + } + + /* + * Acknowledge failure: + * In master transmitter mode a Stop must be generated by software + */ + if (status & STM32F4_I2C_SR1_AF) { + if (!(msg->addr & I2C_M_RD)) { + reg = i2c_dev->base + STM32F4_I2C_CR1; + stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); + } + status &= ~STM32F4_I2C_SR1_AF; + writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); + msg->result = -EIO; + } + + /* Bus error */ + if (status & STM32F4_I2C_SR1_BERR) { + status &= ~STM32F4_I2C_SR1_BERR; + writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); + msg->result = -EIO; + } + + stm32f4_i2c_disable_irq(i2c_dev); + complete(&i2c_dev->complete); + + return IRQ_HANDLED; +} + +/** + * stm32f4_i2c_xfer_msg() - Transfer a single I2C message + * @i2c_dev: Controller's private data + * @msg: I2C message to transfer + * @is_first: first message of the sequence + * @is_last: last message of the sequence + */ +static int stm32f4_i2c_xfer_msg(struct stm32f4_i2c_dev *i2c_dev, + struct i2c_msg *msg, bool is_first, + bool is_last) +{ + struct stm32f4_i2c_msg *f4_msg = &i2c_dev->msg; + void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR1; + unsigned long timeout; + u32 mask; + int ret; + + f4_msg->addr = i2c_8bit_addr_from_msg(msg); + f4_msg->buf = msg->buf; + f4_msg->count = msg->len; + f4_msg->result = 0; + f4_msg->stop = is_last; + + reinit_completion(&i2c_dev->complete); + + /* Enable events and errors interrupts */ + mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN; + stm32f4_i2c_set_bits(i2c_dev->base + STM32F4_I2C_CR2, mask); + + if (is_first) { + ret = stm32f4_i2c_wait_free_bus(i2c_dev); + if (ret) + return ret; + + /* START generation */ + stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); + } + + timeout = wait_for_completion_timeout(&i2c_dev->complete, + i2c_dev->adap.timeout); + ret = f4_msg->result; + + if (!timeout) + ret = -ETIMEDOUT; + + return ret; +} + +/** + * stm32f4_i2c_xfer() - Transfer combined I2C message + * @i2c_adap: Adapter pointer to the controller + * @msgs: Pointer to data to be written. + * @num: Number of messages to be executed + */ +static int stm32f4_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], + int num) +{ + struct stm32f4_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); + int ret, i; + + ret = clk_enable(i2c_dev->clk); + if (ret) { + dev_err(i2c_dev->dev, "Failed to enable clock\n"); + return ret; + } + + for (i = 0; i < num && !ret; i++) + ret = stm32f4_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, + i == num - 1); + + clk_disable(i2c_dev->clk); + + return (ret < 0) ? ret : num; +} + +static u32 stm32f4_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static struct i2c_algorithm stm32f4_i2c_algo = { + .master_xfer = stm32f4_i2c_xfer, + .functionality = stm32f4_i2c_func, +}; + +static int stm32f4_i2c_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct stm32f4_i2c_dev *i2c_dev; + struct resource *res; + u32 irq_event, irq_error, clk_rate; + struct i2c_adapter *adap; + struct reset_control *rst; + int ret; + + i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); + if (!i2c_dev) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(i2c_dev->base)) + return PTR_ERR(i2c_dev->base); + + irq_event = irq_of_parse_and_map(np, 0); + if (!irq_event) { + dev_err(&pdev->dev, "IRQ event missing or invalid\n"); + return -EINVAL; + } + + irq_error = irq_of_parse_and_map(np, 1); + if (!irq_error) { + dev_err(&pdev->dev, "IRQ error missing or invalid\n"); + return -EINVAL; + } + + i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(i2c_dev->clk)) { + dev_err(&pdev->dev, "Error: Missing controller clock\n"); + return PTR_ERR(i2c_dev->clk); + } + ret = clk_prepare_enable(i2c_dev->clk); + if (ret) { + dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n"); + return ret; + } + + rst = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(rst)) { + dev_err(&pdev->dev, "Error: Missing controller reset\n"); + ret = PTR_ERR(rst); + goto clk_free; + } + reset_control_assert(rst); + udelay(2); + reset_control_deassert(rst); + + i2c_dev->speed = STM32F4_I2C_SPEED_STANDARD; + ret = of_property_read_u32(np, "clock-frequency", &clk_rate); + if (!ret && clk_rate >= 400000) + i2c_dev->speed = STM32F4_I2C_SPEED_FAST; + + i2c_dev->dev = &pdev->dev; + + ret = devm_request_irq(&pdev->dev, irq_event, stm32f4_i2c_isr_event, 0, + pdev->name, i2c_dev); + if (ret) { + dev_err(&pdev->dev, "Failed to request irq event %i\n", + irq_event); + goto clk_free; + } + + ret = devm_request_irq(&pdev->dev, irq_error, stm32f4_i2c_isr_error, 0, + pdev->name, i2c_dev); + if (ret) { + dev_err(&pdev->dev, "Failed to request irq error %i\n", + irq_error); + goto clk_free; + } + + ret = stm32f4_i2c_hw_config(i2c_dev); + if (ret) + goto clk_free; + + adap = &i2c_dev->adap; + i2c_set_adapdata(adap, i2c_dev); + snprintf(adap->name, sizeof(adap->name), "STM32 I2C(%pa)", &res->start); + adap->owner = THIS_MODULE; + adap->timeout = 2 * HZ; + adap->retries = 0; + adap->algo = &stm32f4_i2c_algo; + adap->dev.parent = &pdev->dev; + adap->dev.of_node = pdev->dev.of_node; + + init_completion(&i2c_dev->complete); + + ret = i2c_add_adapter(adap); + if (ret) + goto clk_free; + + platform_set_drvdata(pdev, i2c_dev); + + clk_disable(i2c_dev->clk); + + dev_info(i2c_dev->dev, "STM32F4 I2C driver registered\n"); + + return 0; + +clk_free: + clk_disable_unprepare(i2c_dev->clk); + return ret; +} + +static int stm32f4_i2c_remove(struct platform_device *pdev) +{ + struct stm32f4_i2c_dev *i2c_dev = platform_get_drvdata(pdev); + + i2c_del_adapter(&i2c_dev->adap); + + clk_unprepare(i2c_dev->clk); + + return 0; +} + +static const struct of_device_id stm32f4_i2c_match[] = { + { .compatible = "st,stm32f4-i2c", }, + {}, +}; +MODULE_DEVICE_TABLE(of, stm32f4_i2c_match); + +static struct platform_driver stm32f4_i2c_driver = { + .driver = { + .name = "stm32f4-i2c", + .of_match_table = stm32f4_i2c_match, + }, + .probe = stm32f4_i2c_probe, + .remove = stm32f4_i2c_remove, +}; + +module_platform_driver(stm32f4_i2c_driver); + +MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); +MODULE_DESCRIPTION("STMicroelectronics STM32F4 I2C driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v10 2/5] i2c: Add STM32F4 I2C driver @ 2017-01-19 13:25 ` M'boumba Cedric Madianga 0 siblings, 0 replies; 27+ messages in thread From: M'boumba Cedric Madianga @ 2017-01-19 13:25 UTC (permalink / raw) To: linux-arm-kernel This patch adds support for the STM32F4 I2C controller. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> --- drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-stm32f4.c | 897 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 908 insertions(+) create mode 100644 drivers/i2c/busses/i2c-stm32f4.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 0cdc844..2719208 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -886,6 +886,16 @@ config I2C_ST This driver can also be built as module. If so, the module will be called i2c-st. +config I2C_STM32F4 + tristate "STMicroelectronics STM32F4 I2C support" + depends on ARCH_STM32 || COMPILE_TEST + help + Enable this option to add support for STM32 I2C controller embedded + in STM32F4 SoCs. + + This driver can also be built as module. If so, the module + will be called i2c-stm32f4. + config I2C_STU300 tristate "ST Microelectronics DDC I2C interface" depends on MACH_U300 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 1c1bac8..a2c6ff5 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -85,6 +85,7 @@ obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o obj-$(CONFIG_I2C_ST) += i2c-st.o +obj-$(CONFIG_I2C_STM32F4) += i2c-stm32f4.o obj-$(CONFIG_I2C_STU300) += i2c-stu300.o obj-$(CONFIG_I2C_SUN6I_P2WI) += i2c-sun6i-p2wi.o obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o diff --git a/drivers/i2c/busses/i2c-stm32f4.c b/drivers/i2c/busses/i2c-stm32f4.c new file mode 100644 index 0000000..f9dd7e8 --- /dev/null +++ b/drivers/i2c/busses/i2c-stm32f4.c @@ -0,0 +1,897 @@ +/* + * Driver for STMicroelectronics STM32 I2C controller + * + * This I2C controller is described in the STM32F429/439 Soc reference manual. + * Please see below a link to the documentation: + * http://www.st.com/resource/en/reference_manual/DM00031020.pdf + * + * Copyright (C) M'boumba Cedric Madianga 2016 + * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> + * + * This driver is based on i2c-st.c + * + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/i2c.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/reset.h> + +/* STM32F4 I2C offset registers */ +#define STM32F4_I2C_CR1 0x00 +#define STM32F4_I2C_CR2 0x04 +#define STM32F4_I2C_DR 0x10 +#define STM32F4_I2C_SR1 0x14 +#define STM32F4_I2C_SR2 0x18 +#define STM32F4_I2C_CCR 0x1C +#define STM32F4_I2C_TRISE 0x20 +#define STM32F4_I2C_FLTR 0x24 + +/* STM32F4 I2C control 1*/ +#define STM32F4_I2C_CR1_POS BIT(11) +#define STM32F4_I2C_CR1_ACK BIT(10) +#define STM32F4_I2C_CR1_STOP BIT(9) +#define STM32F4_I2C_CR1_START BIT(8) +#define STM32F4_I2C_CR1_PE BIT(0) + +/* STM32F4 I2C control 2 */ +#define STM32F4_I2C_CR2_FREQ_MASK GENMASK(5, 0) +#define STM32F4_I2C_CR2_FREQ(n) ((n) & STM32F4_I2C_CR2_FREQ_MASK) +#define STM32F4_I2C_CR2_ITBUFEN BIT(10) +#define STM32F4_I2C_CR2_ITEVTEN BIT(9) +#define STM32F4_I2C_CR2_ITERREN BIT(8) +#define STM32F4_I2C_CR2_IRQ_MASK (STM32F4_I2C_CR2_ITBUFEN | \ + STM32F4_I2C_CR2_ITEVTEN | \ + STM32F4_I2C_CR2_ITERREN) + +/* STM32F4 I2C Status 1 */ +#define STM32F4_I2C_SR1_AF BIT(10) +#define STM32F4_I2C_SR1_ARLO BIT(9) +#define STM32F4_I2C_SR1_BERR BIT(8) +#define STM32F4_I2C_SR1_TXE BIT(7) +#define STM32F4_I2C_SR1_RXNE BIT(6) +#define STM32F4_I2C_SR1_BTF BIT(2) +#define STM32F4_I2C_SR1_ADDR BIT(1) +#define STM32F4_I2C_SR1_SB BIT(0) +#define STM32F4_I2C_SR1_ITEVTEN_MASK (STM32F4_I2C_SR1_BTF | \ + STM32F4_I2C_SR1_ADDR | \ + STM32F4_I2C_SR1_SB) +#define STM32F4_I2C_SR1_ITBUFEN_MASK (STM32F4_I2C_SR1_TXE | \ + STM32F4_I2C_SR1_RXNE) +#define STM32F4_I2C_SR1_ITERREN_MASK (STM32F4_I2C_SR1_AF | \ + STM32F4_I2C_SR1_ARLO | \ + STM32F4_I2C_SR1_BERR) + +/* STM32F4 I2C Status 2 */ +#define STM32F4_I2C_SR2_BUSY BIT(1) + +/* STM32F4 I2C Control Clock */ +#define STM32F4_I2C_CCR_CCR_MASK GENMASK(11, 0) +#define STM32F4_I2C_CCR_CCR(n) ((n) & STM32F4_I2C_CCR_CCR_MASK) +#define STM32F4_I2C_CCR_FS BIT(15) +#define STM32F4_I2C_CCR_DUTY BIT(14) + +/* STM32F4 I2C Trise */ +#define STM32F4_I2C_TRISE_VALUE_MASK GENMASK(5, 0) +#define STM32F4_I2C_TRISE_VALUE(n) ((n) & STM32F4_I2C_TRISE_VALUE_MASK) + +#define STM32F4_I2C_MIN_STANDARD_FREQ 2U +#define STM32F4_I2C_MIN_FAST_FREQ 6U +#define STM32F4_I2C_MAX_FREQ 46U +#define HZ_TO_MHZ 1000000 + +enum stm32f4_i2c_speed { + STM32F4_I2C_SPEED_STANDARD, /* 100 kHz */ + STM32F4_I2C_SPEED_FAST, /* 400 kHz */ + STM32F4_I2C_SPEED_END, +}; + +/** + * struct stm32f4_i2c_msg - client specific data + * @addr: 8-bit slave addr, including r/w bit + * @count: number of bytes to be transferred + * @buf: data buffer + * @result: result of the transfer + * @stop: last I2C msg to be sent, i.e. STOP to be generated + */ +struct stm32f4_i2c_msg { + u8 addr; + u32 count; + u8 *buf; + int result; + bool stop; +}; + +/** + * struct stm32f4_i2c_dev - private data of the controller + * @adap: I2C adapter for this controller + * @dev: device for this controller + * @base: virtual memory area + * @complete: completion of I2C message + * @clk: hw i2c clock + * @speed: I2C clock frequency of the controller. Standard or Fast are supported + * @parent_rate: I2C clock parent rate in MHz + * @msg: I2C transfer information + */ +struct stm32f4_i2c_dev { + struct i2c_adapter adap; + struct device *dev; + void __iomem *base; + struct completion complete; + struct clk *clk; + int speed; + int parent_rate; + struct stm32f4_i2c_msg msg; +}; + +static inline void stm32f4_i2c_set_bits(void __iomem *reg, u32 mask) +{ + writel_relaxed(readl_relaxed(reg) | mask, reg); +} + +static inline void stm32f4_i2c_clr_bits(void __iomem *reg, u32 mask) +{ + writel_relaxed(readl_relaxed(reg) & ~mask, reg); +} + +static void stm32f4_i2c_disable_irq(struct stm32f4_i2c_dev *i2c_dev) +{ + void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; + + stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_IRQ_MASK); +} + +static int stm32f4_i2c_set_periph_clk_freq(struct stm32f4_i2c_dev *i2c_dev) +{ + u32 freq; + u32 cr2 = 0; + + i2c_dev->parent_rate = clk_get_rate(i2c_dev->clk); + freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ); + + if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) { + /* + * To reach 100 kHz, the parent clk frequency should be between + * a minimum value of 2 MHz and a maximum value of 46 MHz due + * to hardware limitation + */ + if (freq < STM32F4_I2C_MIN_STANDARD_FREQ || + freq > STM32F4_I2C_MAX_FREQ) { + dev_err(i2c_dev->dev, + "bad parent clk freq for standard mode\n"); + return -EINVAL; + } + } else { + /* + * To be as close as possible to 400 kHz, the parent clk + * frequency should be between a minimum value of 6 MHz and a + * maximum value of 46 MHz due to hardware limitation + */ + if (freq < STM32F4_I2C_MIN_FAST_FREQ || + freq > STM32F4_I2C_MAX_FREQ) { + dev_err(i2c_dev->dev, + "bad parent clk freq for fast mode\n"); + return -EINVAL; + } + } + + cr2 |= STM32F4_I2C_CR2_FREQ(freq); + writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); + + return 0; +} + +static void stm32f4_i2c_set_rise_time(struct stm32f4_i2c_dev *i2c_dev) +{ + u32 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ); + u32 trise; + + /* + * These bits must be programmed with the maximum SCL rise time given in + * the I2C bus specification, incremented by 1. + * + * In standard mode, the maximum allowed SCL rise time is 1000 ns. + * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to + * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be + * programmed with 0x9. (1000 ns / 125 ns + 1) + * So, for I2C standard mode TRISE = FREQ[5:0] + 1 + * + * In fast mode, the maximum allowed SCL rise time is 300 ns. + * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to + * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be + * programmed with 0x3. (300 ns / 125 ns + 1) + * So, for I2C fast mode TRISE = FREQ[5:0] * 300 / 1000 + 1 + * + * Function stm32f4_i2c_set_periph_clk_freq made sure that parent rate + * is not higher than 46 MHz . As a result trise is at most 4 bits wide + * and so fits into the TRISE bits [5:0]. + */ + if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) + trise = freq + 1; + else + trise = freq * 3 / 10 + 1; + + writel_relaxed(STM32F4_I2C_TRISE_VALUE(trise), + i2c_dev->base + STM32F4_I2C_TRISE); +} + +static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev) +{ + u32 val; + u32 ccr = 0; + + if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) { + /* + * In standard mode: + * t_scl_high = t_scl_low = CCR * I2C parent clk period + * So to reach 100 kHz, we have: + * CCR = I2C parent rate / 100 kHz >> 1 + * + * For example with parent rate = 2 MHz: + * CCR = 2000000 / (100000 << 1) = 10 + * t_scl_high = t_scl_low = 10 * (1 / 2000000) = 5000 ns + * t_scl_high + t_scl_low = 10000 ns so 100 kHz is reached + * + * Function stm32f4_i2c_set_periph_clk_freq made sure that + * parent rate is not higher than 46 MHz . As a result val + * is@most 8 bits wide and so fits into the CCR bits [11:0]. + */ + val = i2c_dev->parent_rate / (100000 << 1); + } else { + /* + * In fast mode, we compute CCR with duty = 0 as with low + * frequencies we are not able to reach 400 kHz. + * In that case: + * t_scl_high = CCR * I2C parent clk period + * t_scl_low = 2 * CCR * I2C parent clk period + * So, CCR = I2C parent rate / (400 kHz * 3) + * + * For example with parent rate = 6 MHz: + * CCR = 6000000 / (400000 * 3) = 5 + * t_scl_high = 5 * (1 / 6000000) = 833 ns > 600 ns + * t_scl_low = 2 * 5 * (1 / 6000000) = 1667 ns > 1300 ns + * t_scl_high + t_scl_low = 2500 ns so 400 kHz is reached + * + * Function stm32f4_i2c_set_periph_clk_freq made sure that + * parent rate is not higher than 46 MHz . As a result val + * is at most 6 bits wide and so fits into the CCR bits [11:0]. + */ + val = DIV_ROUND_UP(i2c_dev->parent_rate, 400000 * 3); + + /* Select Fast mode */ + ccr |= STM32F4_I2C_CCR_FS; + } + + ccr |= STM32F4_I2C_CCR_CCR(val); + writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR); +} + +/** + * stm32f4_i2c_hw_config() - Prepare I2C block + * @i2c_dev: Controller's private data + */ +static int stm32f4_i2c_hw_config(struct stm32f4_i2c_dev *i2c_dev) +{ + int ret; + + ret = stm32f4_i2c_set_periph_clk_freq(i2c_dev); + if (ret) + return ret; + + stm32f4_i2c_set_rise_time(i2c_dev); + + stm32f4_i2c_set_speed_mode(i2c_dev); + + /* Enable I2C */ + writel_relaxed(STM32F4_I2C_CR1_PE, i2c_dev->base + STM32F4_I2C_CR1); + + return 0; +} + +static int stm32f4_i2c_wait_free_bus(struct stm32f4_i2c_dev *i2c_dev) +{ + u32 status; + int ret; + + ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F4_I2C_SR2, + status, + !(status & STM32F4_I2C_SR2_BUSY), + 10, 1000); + if (ret) { + dev_dbg(i2c_dev->dev, "bus not free\n"); + ret = -EBUSY; + } + + return ret; +} + +/** + * stm32f4_i2c_write_ byte() - Write a byte in the data register + * @i2c_dev: Controller's private data + * @byte: Data to write in the register + */ +static void stm32f4_i2c_write_byte(struct stm32f4_i2c_dev *i2c_dev, u8 byte) +{ + writel_relaxed(byte, i2c_dev->base + STM32F4_I2C_DR); +} + +/** + * stm32f4_i2c_write_msg() - Fill the data register in write mode + * @i2c_dev: Controller's private data + * + * This function fills the data register with I2C transfer buffer + */ +static void stm32f4_i2c_write_msg(struct stm32f4_i2c_dev *i2c_dev) +{ + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + + stm32f4_i2c_write_byte(i2c_dev, *msg->buf++); + msg->count--; +} + +static void stm32f4_i2c_read_msg(struct stm32f4_i2c_dev *i2c_dev) +{ + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + u32 rbuf; + + rbuf = readl_relaxed(i2c_dev->base + STM32F4_I2C_DR); + *msg->buf++ = rbuf; + msg->count--; +} + +static void stm32f4_i2c_terminate_xfer(struct stm32f4_i2c_dev *i2c_dev) +{ + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; + + stm32f4_i2c_disable_irq(i2c_dev); + + reg = i2c_dev->base + STM32F4_I2C_CR1; + if (msg->stop) + stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); + else + stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); + + complete(&i2c_dev->complete); +} + +/** + * stm32f4_i2c_handle_write() - Handle FIFO empty interrupt in case of write + * @i2c_dev: Controller's private data + */ +static void stm32f4_i2c_handle_write(struct stm32f4_i2c_dev *i2c_dev) +{ + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; + + if (msg->count) { + stm32f4_i2c_write_msg(i2c_dev); + if (!msg->count) { + /* + * Disable buffer interrupts for RX not empty and TX + * empty events + */ + stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN); + } + } else { + stm32f4_i2c_terminate_xfer(i2c_dev); + } +} + +/** + * stm32f4_i2c_handle_read() - Handle FIFO empty interrupt in case of read + * @i2c_dev: Controller's private data + * + * This function is called when a new data is received in data register + */ +static void stm32f4_i2c_handle_read(struct stm32f4_i2c_dev *i2c_dev) +{ + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; + + switch (msg->count) { + case 1: + stm32f4_i2c_disable_irq(i2c_dev); + stm32f4_i2c_read_msg(i2c_dev); + complete(&i2c_dev->complete); + break; + /* + * For 2-byte reception, 3-byte reception and for Data N-2, N-1 and N + * for N-byte reception with N > 3, we do not have to read the data + * register when RX not empty event occurs as we have to wait for byte + * transferred finished event before reading data. + * So, here we just disable buffer interrupt in order to avoid another + * system preemption due to RX not empty event. + */ + case 2: + case 3: + stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN); + break; + /* + * For N byte reception with N > 3 we directly read data register + * until N-2 data. + */ + default: + stm32f4_i2c_read_msg(i2c_dev); + } +} + +/** + * stm32f4_i2c_handle_rx_done() - Handle byte transfer finished interrupt + * in case of read + * @i2c_dev: Controller's private data + * + * This function is called when a new data is received in the shift register + * but data register has not been read yet. + */ +static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev) +{ + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + void __iomem *reg; + u32 mask; + int i; + + switch (msg->count) { + case 2: + /* + * In order to correctly send the Stop or Repeated Start + * condition on the I2C bus, the STOP/START bit has to be set + * before reading the last two bytes (data N-1 and N). + * After that, we could read the last two bytes, disable + * remaining interrupts and notify the end of xfer to the + * client + */ + reg = i2c_dev->base + STM32F4_I2C_CR1; + if (msg->stop) + stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); + else + stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); + + for (i = 2; i > 0; i--) + stm32f4_i2c_read_msg(i2c_dev); + + reg = i2c_dev->base + STM32F4_I2C_CR2; + mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN; + stm32f4_i2c_clr_bits(reg, mask); + + complete(&i2c_dev->complete); + break; + case 3: + /* + * In order to correctly generate the NACK pulse after the last + * received data byte, we have to enable NACK before reading N-2 + * data + */ + reg = i2c_dev->base + STM32F4_I2C_CR1; + stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR1_ACK); + stm32f4_i2c_read_msg(i2c_dev); + break; + default: + stm32f4_i2c_read_msg(i2c_dev); + } +} + +/** + * stm32f4_i2c_handle_rx_addr() - Handle address matched interrupt in case of + * master receiver + * @i2c_dev: Controller's private data + */ +static void stm32f4_i2c_handle_rx_addr(struct stm32f4_i2c_dev *i2c_dev) +{ + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + u32 cr1; + + switch (msg->count) { + case 0: + stm32f4_i2c_terminate_xfer(i2c_dev); + + /* Clear ADDR flag */ + readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); + break; + case 1: + /* + * Single byte reception: + * Enable NACK and reset POS (Acknowledge position). + * Then, clear ADDR flag and set STOP or RepSTART. + * In that way, the NACK and STOP or RepStart pulses will be + * sent as soon as the byte will be received in shift register + */ + cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); + cr1 &= ~(STM32F4_I2C_CR1_ACK | STM32F4_I2C_CR1_POS); + writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); + + readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); + + if (msg->stop) + cr1 |= STM32F4_I2C_CR1_STOP; + else + cr1 |= STM32F4_I2C_CR1_START; + writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); + break; + case 2: + /* + * 2-byte reception: + * Enable NACK, set POS (NACK position) and clear ADDR flag. + * In that way, NACK will be sent for the next byte which will + * be received in the shift register instead of the current + * one. + */ + cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); + cr1 &= ~STM32F4_I2C_CR1_ACK; + cr1 |= STM32F4_I2C_CR1_POS; + writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); + + readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); + break; + + default: + /* + * N-byte reception: + * Enable ACK, reset POS (ACK postion) and clear ADDR flag. + * In that way, ACK will be sent as soon as the current byte + * will be received in the shift register + */ + cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); + cr1 |= STM32F4_I2C_CR1_ACK; + cr1 &= ~STM32F4_I2C_CR1_POS; + writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); + + readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); + break; + } +} + +/** + * stm32f4_i2c_isr_event() - Interrupt routine for I2C bus event + * @irq: interrupt number + * @data: Controller's private data + */ +static irqreturn_t stm32f4_i2c_isr_event(int irq, void *data) +{ + struct stm32f4_i2c_dev *i2c_dev = data; + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + u32 possible_status = STM32F4_I2C_SR1_ITEVTEN_MASK; + u32 status, ien, event, cr2; + + cr2 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR2); + ien = cr2 & STM32F4_I2C_CR2_IRQ_MASK; + + /* Update possible_status if buffer interrupt is enabled */ + if (ien & STM32F4_I2C_CR2_ITBUFEN) + possible_status |= STM32F4_I2C_SR1_ITBUFEN_MASK; + + status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1); + event = status & possible_status; + if (!event) { + dev_dbg(i2c_dev->dev, + "spurious evt irq (status=0x%08x, ien=0x%08x)\n", + status, ien); + return IRQ_NONE; + } + + /* Start condition generated */ + if (event & STM32F4_I2C_SR1_SB) + stm32f4_i2c_write_byte(i2c_dev, msg->addr); + + /* I2C Address sent */ + if (event & STM32F4_I2C_SR1_ADDR) { + if (msg->addr & I2C_M_RD) + stm32f4_i2c_handle_rx_addr(i2c_dev); + else + readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); + + /* + * Enable buffer interrupts for RX not empty and TX empty + * events + */ + cr2 |= STM32F4_I2C_CR2_ITBUFEN; + writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); + } + + /* TX empty */ + if ((event & STM32F4_I2C_SR1_TXE) && !(msg->addr & I2C_M_RD)) + stm32f4_i2c_handle_write(i2c_dev); + + /* RX not empty */ + if ((event & STM32F4_I2C_SR1_RXNE) && (msg->addr & I2C_M_RD)) + stm32f4_i2c_handle_read(i2c_dev); + + /* + * The BTF (Byte Transfer finished) event occurs when: + * - in reception : a new byte is received in the shift register + * but the previous byte has not been read yet from data register + * - in transmission: a new byte should be sent but the data register + * has not been written yet + */ + if (event & STM32F4_I2C_SR1_BTF) { + if (msg->addr & I2C_M_RD) + stm32f4_i2c_handle_rx_done(i2c_dev); + else + stm32f4_i2c_handle_write(i2c_dev); + } + + return IRQ_HANDLED; +} + +/** + * stm32f4_i2c_isr_error() - Interrupt routine for I2C bus error + * @irq: interrupt number + * @data: Controller's private data + */ +static irqreturn_t stm32f4_i2c_isr_error(int irq, void *data) +{ + struct stm32f4_i2c_dev *i2c_dev = data; + struct stm32f4_i2c_msg *msg = &i2c_dev->msg; + void __iomem *reg; + u32 status; + + status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1); + + /* Arbitration lost */ + if (status & STM32F4_I2C_SR1_ARLO) { + status &= ~STM32F4_I2C_SR1_ARLO; + writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); + msg->result = -EAGAIN; + } + + /* + * Acknowledge failure: + * In master transmitter mode a Stop must be generated by software + */ + if (status & STM32F4_I2C_SR1_AF) { + if (!(msg->addr & I2C_M_RD)) { + reg = i2c_dev->base + STM32F4_I2C_CR1; + stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); + } + status &= ~STM32F4_I2C_SR1_AF; + writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); + msg->result = -EIO; + } + + /* Bus error */ + if (status & STM32F4_I2C_SR1_BERR) { + status &= ~STM32F4_I2C_SR1_BERR; + writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); + msg->result = -EIO; + } + + stm32f4_i2c_disable_irq(i2c_dev); + complete(&i2c_dev->complete); + + return IRQ_HANDLED; +} + +/** + * stm32f4_i2c_xfer_msg() - Transfer a single I2C message + * @i2c_dev: Controller's private data + * @msg: I2C message to transfer + * @is_first: first message of the sequence + * @is_last: last message of the sequence + */ +static int stm32f4_i2c_xfer_msg(struct stm32f4_i2c_dev *i2c_dev, + struct i2c_msg *msg, bool is_first, + bool is_last) +{ + struct stm32f4_i2c_msg *f4_msg = &i2c_dev->msg; + void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR1; + unsigned long timeout; + u32 mask; + int ret; + + f4_msg->addr = i2c_8bit_addr_from_msg(msg); + f4_msg->buf = msg->buf; + f4_msg->count = msg->len; + f4_msg->result = 0; + f4_msg->stop = is_last; + + reinit_completion(&i2c_dev->complete); + + /* Enable events and errors interrupts */ + mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN; + stm32f4_i2c_set_bits(i2c_dev->base + STM32F4_I2C_CR2, mask); + + if (is_first) { + ret = stm32f4_i2c_wait_free_bus(i2c_dev); + if (ret) + return ret; + + /* START generation */ + stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); + } + + timeout = wait_for_completion_timeout(&i2c_dev->complete, + i2c_dev->adap.timeout); + ret = f4_msg->result; + + if (!timeout) + ret = -ETIMEDOUT; + + return ret; +} + +/** + * stm32f4_i2c_xfer() - Transfer combined I2C message + * @i2c_adap: Adapter pointer to the controller + * @msgs: Pointer to data to be written. + * @num: Number of messages to be executed + */ +static int stm32f4_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], + int num) +{ + struct stm32f4_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); + int ret, i; + + ret = clk_enable(i2c_dev->clk); + if (ret) { + dev_err(i2c_dev->dev, "Failed to enable clock\n"); + return ret; + } + + for (i = 0; i < num && !ret; i++) + ret = stm32f4_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, + i == num - 1); + + clk_disable(i2c_dev->clk); + + return (ret < 0) ? ret : num; +} + +static u32 stm32f4_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static struct i2c_algorithm stm32f4_i2c_algo = { + .master_xfer = stm32f4_i2c_xfer, + .functionality = stm32f4_i2c_func, +}; + +static int stm32f4_i2c_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct stm32f4_i2c_dev *i2c_dev; + struct resource *res; + u32 irq_event, irq_error, clk_rate; + struct i2c_adapter *adap; + struct reset_control *rst; + int ret; + + i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); + if (!i2c_dev) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(i2c_dev->base)) + return PTR_ERR(i2c_dev->base); + + irq_event = irq_of_parse_and_map(np, 0); + if (!irq_event) { + dev_err(&pdev->dev, "IRQ event missing or invalid\n"); + return -EINVAL; + } + + irq_error = irq_of_parse_and_map(np, 1); + if (!irq_error) { + dev_err(&pdev->dev, "IRQ error missing or invalid\n"); + return -EINVAL; + } + + i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(i2c_dev->clk)) { + dev_err(&pdev->dev, "Error: Missing controller clock\n"); + return PTR_ERR(i2c_dev->clk); + } + ret = clk_prepare_enable(i2c_dev->clk); + if (ret) { + dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n"); + return ret; + } + + rst = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(rst)) { + dev_err(&pdev->dev, "Error: Missing controller reset\n"); + ret = PTR_ERR(rst); + goto clk_free; + } + reset_control_assert(rst); + udelay(2); + reset_control_deassert(rst); + + i2c_dev->speed = STM32F4_I2C_SPEED_STANDARD; + ret = of_property_read_u32(np, "clock-frequency", &clk_rate); + if (!ret && clk_rate >= 400000) + i2c_dev->speed = STM32F4_I2C_SPEED_FAST; + + i2c_dev->dev = &pdev->dev; + + ret = devm_request_irq(&pdev->dev, irq_event, stm32f4_i2c_isr_event, 0, + pdev->name, i2c_dev); + if (ret) { + dev_err(&pdev->dev, "Failed to request irq event %i\n", + irq_event); + goto clk_free; + } + + ret = devm_request_irq(&pdev->dev, irq_error, stm32f4_i2c_isr_error, 0, + pdev->name, i2c_dev); + if (ret) { + dev_err(&pdev->dev, "Failed to request irq error %i\n", + irq_error); + goto clk_free; + } + + ret = stm32f4_i2c_hw_config(i2c_dev); + if (ret) + goto clk_free; + + adap = &i2c_dev->adap; + i2c_set_adapdata(adap, i2c_dev); + snprintf(adap->name, sizeof(adap->name), "STM32 I2C(%pa)", &res->start); + adap->owner = THIS_MODULE; + adap->timeout = 2 * HZ; + adap->retries = 0; + adap->algo = &stm32f4_i2c_algo; + adap->dev.parent = &pdev->dev; + adap->dev.of_node = pdev->dev.of_node; + + init_completion(&i2c_dev->complete); + + ret = i2c_add_adapter(adap); + if (ret) + goto clk_free; + + platform_set_drvdata(pdev, i2c_dev); + + clk_disable(i2c_dev->clk); + + dev_info(i2c_dev->dev, "STM32F4 I2C driver registered\n"); + + return 0; + +clk_free: + clk_disable_unprepare(i2c_dev->clk); + return ret; +} + +static int stm32f4_i2c_remove(struct platform_device *pdev) +{ + struct stm32f4_i2c_dev *i2c_dev = platform_get_drvdata(pdev); + + i2c_del_adapter(&i2c_dev->adap); + + clk_unprepare(i2c_dev->clk); + + return 0; +} + +static const struct of_device_id stm32f4_i2c_match[] = { + { .compatible = "st,stm32f4-i2c", }, + {}, +}; +MODULE_DEVICE_TABLE(of, stm32f4_i2c_match); + +static struct platform_driver stm32f4_i2c_driver = { + .driver = { + .name = "stm32f4-i2c", + .of_match_table = stm32f4_i2c_match, + }, + .probe = stm32f4_i2c_probe, + .remove = stm32f4_i2c_remove, +}; + +module_platform_driver(stm32f4_i2c_driver); + +MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); +MODULE_DESCRIPTION("STMicroelectronics STM32F4 I2C driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v10 2/5] i2c: Add STM32F4 I2C driver 2017-01-19 13:25 ` M'boumba Cedric Madianga @ 2017-01-19 13:31 ` Uwe Kleine-König -1 siblings, 0 replies; 27+ messages in thread From: Uwe Kleine-König @ 2017-01-19 13:31 UTC (permalink / raw) To: M'boumba Cedric Madianga Cc: wsa, robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij, patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel, linux-kernel On Thu, Jan 19, 2017 at 02:25:13PM +0100, M'boumba Cedric Madianga wrote: > This patch adds support for the STM32F4 I2C controller. > > Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Thanks Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v10 2/5] i2c: Add STM32F4 I2C driver @ 2017-01-19 13:31 ` Uwe Kleine-König 0 siblings, 0 replies; 27+ messages in thread From: Uwe Kleine-König @ 2017-01-19 13:31 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jan 19, 2017 at 02:25:13PM +0100, M'boumba Cedric Madianga wrote: > This patch adds support for the STM32F4 I2C controller. > > Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Acked-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de> Thanks Uwe -- Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | http://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v10 2/5] i2c: Add STM32F4 I2C driver 2017-01-19 13:25 ` M'boumba Cedric Madianga @ 2017-01-25 20:25 ` Wolfram Sang -1 siblings, 0 replies; 27+ messages in thread From: Wolfram Sang @ 2017-01-25 20:25 UTC (permalink / raw) To: M'boumba Cedric Madianga Cc: robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij, patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, u.kleine-koenig [-- Attachment #1: Type: text/plain, Size: 346 bytes --] On Thu, Jan 19, 2017 at 02:25:13PM +0100, M'boumba Cedric Madianga wrote: > This patch adds support for the STM32F4 I2C controller. > > Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Applied to for-next with Uwe's ack (which looked more like a review to me, but well...), thanks to all involved for keeping at it! [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v10 2/5] i2c: Add STM32F4 I2C driver @ 2017-01-25 20:25 ` Wolfram Sang 0 siblings, 0 replies; 27+ messages in thread From: Wolfram Sang @ 2017-01-25 20:25 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jan 19, 2017 at 02:25:13PM +0100, M'boumba Cedric Madianga wrote: > This patch adds support for the STM32F4 I2C controller. > > Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Applied to for-next with Uwe's ack (which looked more like a review to me, but well...), thanks to all involved for keeping at it! -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 833 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170125/0f06d05f/attachment.sig> ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v10 2/5] i2c: Add STM32F4 I2C driver 2017-01-25 20:25 ` Wolfram Sang @ 2017-01-25 21:03 ` Uwe Kleine-König -1 siblings, 0 replies; 27+ messages in thread From: Uwe Kleine-König @ 2017-01-25 21:03 UTC (permalink / raw) To: Wolfram Sang Cc: M'boumba Cedric Madianga, robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij, patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel, linux-kernel Hello Wolfram, On Wed, Jan 25, 2017 at 09:25:05PM +0100, Wolfram Sang wrote: > On Thu, Jan 19, 2017 at 02:25:13PM +0100, M'boumba Cedric Madianga wrote: > > This patch adds support for the STM32F4 I2C controller. > > > > Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> > > Applied to for-next with Uwe's ack (which looked more like a review to > me, but well...), thanks to all involved for keeping at it! I thought about calling it a review, but as I didn't look in detail over the last version, I degraded it to an ack on purpose. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v10 2/5] i2c: Add STM32F4 I2C driver @ 2017-01-25 21:03 ` Uwe Kleine-König 0 siblings, 0 replies; 27+ messages in thread From: Uwe Kleine-König @ 2017-01-25 21:03 UTC (permalink / raw) To: linux-arm-kernel Hello Wolfram, On Wed, Jan 25, 2017 at 09:25:05PM +0100, Wolfram Sang wrote: > On Thu, Jan 19, 2017 at 02:25:13PM +0100, M'boumba Cedric Madianga wrote: > > This patch adds support for the STM32F4 I2C controller. > > > > Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> > > Applied to for-next with Uwe's ack (which looked more like a review to > me, but well...), thanks to all involved for keeping at it! I thought about calling it a review, but as I didn't look in detail over the last version, I degraded it to an ack on purpose. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | http://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v10 3/5] ARM: dts: stm32: Add I2C1 support for STM32F429 SoC 2017-01-19 13:25 ` M'boumba Cedric Madianga @ 2017-01-19 13:25 ` M'boumba Cedric Madianga -1 siblings, 0 replies; 27+ messages in thread From: M'boumba Cedric Madianga @ 2017-01-19 13:25 UTC (permalink / raw) To: wsa, robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij, patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, u.kleine-koenig Cc: M'boumba Cedric Madianga This patch adds I2C1 support for STM32F429 SoC Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> --- arch/arm/boot/dts/stm32f429.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index e4dae0e..5b063e9 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -48,6 +48,7 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" #include <dt-bindings/pinctrl/stm32f429-pinfunc.h> +#include <dt-bindings/mfd/stm32f4-rcc.h> / { clocks { @@ -153,6 +154,18 @@ status = "disabled"; }; + i2c1: i2c@40005400 { + compatible = "st,stm32f4-i2c"; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc STM32F4_APB1_RESET(I2C1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + usart7: serial@40007800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40007800 0x400>; @@ -355,6 +368,16 @@ slew-rate = <2>; }; }; + + i2c1_pins_b: i2c1@0 { + pins { + pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>, + <STM32F429_PB6_FUNC_I2C1_SCL>; + bias-disable; + drive-open-drain; + slew-rate = <3>; + }; + }; }; rcc: rcc@40023810 { -- 1.9.1 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v10 3/5] ARM: dts: stm32: Add I2C1 support for STM32F429 SoC @ 2017-01-19 13:25 ` M'boumba Cedric Madianga 0 siblings, 0 replies; 27+ messages in thread From: M'boumba Cedric Madianga @ 2017-01-19 13:25 UTC (permalink / raw) To: linux-arm-kernel This patch adds I2C1 support for STM32F429 SoC Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> --- arch/arm/boot/dts/stm32f429.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index e4dae0e..5b063e9 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -48,6 +48,7 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" #include <dt-bindings/pinctrl/stm32f429-pinfunc.h> +#include <dt-bindings/mfd/stm32f4-rcc.h> / { clocks { @@ -153,6 +154,18 @@ status = "disabled"; }; + i2c1: i2c at 40005400 { + compatible = "st,stm32f4-i2c"; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc STM32F4_APB1_RESET(I2C1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + usart7: serial at 40007800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40007800 0x400>; @@ -355,6 +368,16 @@ slew-rate = <2>; }; }; + + i2c1_pins_b: i2c1 at 0 { + pins { + pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>, + <STM32F429_PB6_FUNC_I2C1_SCL>; + bias-disable; + drive-open-drain; + slew-rate = <3>; + }; + }; }; rcc: rcc at 40023810 { -- 1.9.1 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v10 3/5] ARM: dts: stm32: Add I2C1 support for STM32F429 SoC 2017-01-19 13:25 ` M'boumba Cedric Madianga @ 2017-01-25 20:25 ` Wolfram Sang -1 siblings, 0 replies; 27+ messages in thread From: Wolfram Sang @ 2017-01-25 20:25 UTC (permalink / raw) To: M'boumba Cedric Madianga Cc: robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij, patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, u.kleine-koenig [-- Attachment #1: Type: text/plain, Size: 337 bytes --] On Thu, Jan 19, 2017 at 02:25:14PM +0100, M'boumba Cedric Madianga wrote: > This patch adds I2C1 support for STM32F429 SoC > > Signed-off-by: Patrice Chotard <patrice.chotard@st.com> > Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Note that patches 3-5 should go via stm-tree or arm-soc. Rather not i2c. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v10 3/5] ARM: dts: stm32: Add I2C1 support for STM32F429 SoC @ 2017-01-25 20:25 ` Wolfram Sang 0 siblings, 0 replies; 27+ messages in thread From: Wolfram Sang @ 2017-01-25 20:25 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jan 19, 2017 at 02:25:14PM +0100, M'boumba Cedric Madianga wrote: > This patch adds I2C1 support for STM32F429 SoC > > Signed-off-by: Patrice Chotard <patrice.chotard@st.com> > Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Note that patches 3-5 should go via stm-tree or arm-soc. Rather not i2c. -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 833 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170125/d76309d0/attachment-0001.sig> ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v10 3/5] ARM: dts: stm32: Add I2C1 support for STM32F429 SoC 2017-01-25 20:25 ` Wolfram Sang @ 2017-01-25 21:02 ` M'boumba Cedric Madianga -1 siblings, 0 replies; 27+ messages in thread From: M'boumba Cedric Madianga @ 2017-01-25 21:02 UTC (permalink / raw) To: Wolfram Sang Cc: Rob Herring, Maxime Coquelin, Alexandre Torgue, Linus Walleij, Patrice Chotard, Russell King, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, Uwe Kleine-König 2017-01-25 21:25 GMT+01:00 Wolfram Sang <wsa@the-dreams.de>: > On Thu, Jan 19, 2017 at 02:25:14PM +0100, M'boumba Cedric Madianga wrote: >> This patch adds I2C1 support for STM32F429 SoC >> >> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> >> Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> > > Note that patches 3-5 should go via stm-tree or arm-soc. Rather not i2c. Ok fine. These patches will be applied in STM32 git tree. Thanks ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v10 3/5] ARM: dts: stm32: Add I2C1 support for STM32F429 SoC @ 2017-01-25 21:02 ` M'boumba Cedric Madianga 0 siblings, 0 replies; 27+ messages in thread From: M'boumba Cedric Madianga @ 2017-01-25 21:02 UTC (permalink / raw) To: linux-arm-kernel 2017-01-25 21:25 GMT+01:00 Wolfram Sang <wsa@the-dreams.de>: > On Thu, Jan 19, 2017 at 02:25:14PM +0100, M'boumba Cedric Madianga wrote: >> This patch adds I2C1 support for STM32F429 SoC >> >> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> >> Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> > > Note that patches 3-5 should go via stm-tree or arm-soc. Rather not i2c. Ok fine. These patches will be applied in STM32 git tree. Thanks ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v10 4/5] ARM: dts: stm32: Add I2C1 support for STM32429 eval board 2017-01-19 13:25 ` M'boumba Cedric Madianga @ 2017-01-19 13:25 ` M'boumba Cedric Madianga -1 siblings, 0 replies; 27+ messages in thread From: M'boumba Cedric Madianga @ 2017-01-19 13:25 UTC (permalink / raw) To: wsa, robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij, patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, u.kleine-koenig Cc: M'boumba Cedric Madianga This patch adds I2C1 instance support for STM32x9I-Eval board. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> --- arch/arm/boot/dts/stm32429i-eval.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 76f7206..c943539 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -146,3 +146,9 @@ pinctrl-names = "default"; status = "okay"; }; + +&i2c1 { + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v10 4/5] ARM: dts: stm32: Add I2C1 support for STM32429 eval board @ 2017-01-19 13:25 ` M'boumba Cedric Madianga 0 siblings, 0 replies; 27+ messages in thread From: M'boumba Cedric Madianga @ 2017-01-19 13:25 UTC (permalink / raw) To: linux-arm-kernel This patch adds I2C1 instance support for STM32x9I-Eval board. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> --- arch/arm/boot/dts/stm32429i-eval.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 76f7206..c943539 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -146,3 +146,9 @@ pinctrl-names = "default"; status = "okay"; }; + +&i2c1 { + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v10 5/5] ARM: configs: stm32: Add I2C support for STM32 defconfig 2017-01-19 13:25 ` M'boumba Cedric Madianga @ 2017-01-19 13:25 ` M'boumba Cedric Madianga -1 siblings, 0 replies; 27+ messages in thread From: M'boumba Cedric Madianga @ 2017-01-19 13:25 UTC (permalink / raw) To: wsa, robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij, patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, u.kleine-koenig Cc: M'boumba Cedric Madianga This patch adds I2C support for STM32 default configuration Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> --- arch/arm/configs/stm32_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index 5a72d69..323d2a3 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -47,6 +47,9 @@ CONFIG_SERIAL_NONSTANDARD=y CONFIG_SERIAL_STM32=y CONFIG_SERIAL_STM32_CONSOLE=y # CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_STM32F4=y # CONFIG_HWMON is not set # CONFIG_USB_SUPPORT is not set CONFIG_NEW_LEDS=y -- 1.9.1 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v10 5/5] ARM: configs: stm32: Add I2C support for STM32 defconfig @ 2017-01-19 13:25 ` M'boumba Cedric Madianga 0 siblings, 0 replies; 27+ messages in thread From: M'boumba Cedric Madianga @ 2017-01-19 13:25 UTC (permalink / raw) To: linux-arm-kernel This patch adds I2C support for STM32 default configuration Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> --- arch/arm/configs/stm32_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index 5a72d69..323d2a3 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -47,6 +47,9 @@ CONFIG_SERIAL_NONSTANDARD=y CONFIG_SERIAL_STM32=y CONFIG_SERIAL_STM32_CONSOLE=y # CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_STM32F4=y # CONFIG_HWMON is not set # CONFIG_USB_SUPPORT is not set CONFIG_NEW_LEDS=y -- 1.9.1 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v10 5/5] ARM: configs: stm32: Add I2C support for STM32 defconfig 2017-01-19 13:25 ` M'boumba Cedric Madianga (?) @ 2017-04-03 14:36 ` Alexandre Torgue -1 siblings, 0 replies; 27+ messages in thread From: Alexandre Torgue @ 2017-04-03 14:36 UTC (permalink / raw) To: M'boumba Cedric Madianga, wsa, robh+dt, mcoquelin.stm32, linus.walleij, patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, u.kleine-koenig Hi, On 01/19/2017 02:25 PM, M'boumba Cedric Madianga wrote: > This patch adds I2C support for STM32 default configuration > > Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> > --- Applied on stm32-defconfig-for-v4.12 Regards Alex > arch/arm/configs/stm32_defconfig | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig > index 5a72d69..323d2a3 100644 > --- a/arch/arm/configs/stm32_defconfig > +++ b/arch/arm/configs/stm32_defconfig > @@ -47,6 +47,9 @@ CONFIG_SERIAL_NONSTANDARD=y > CONFIG_SERIAL_STM32=y > CONFIG_SERIAL_STM32_CONSOLE=y > # CONFIG_HW_RANDOM is not set > +CONFIG_I2C=y > +CONFIG_I2C_CHARDEV=y > +CONFIG_I2C_STM32F4=y > # CONFIG_HWMON is not set > # CONFIG_USB_SUPPORT is not set > CONFIG_NEW_LEDS=y > ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v10 5/5] ARM: configs: stm32: Add I2C support for STM32 defconfig @ 2017-04-03 14:36 ` Alexandre Torgue 0 siblings, 0 replies; 27+ messages in thread From: Alexandre Torgue @ 2017-04-03 14:36 UTC (permalink / raw) To: linux-arm-kernel Hi, On 01/19/2017 02:25 PM, M'boumba Cedric Madianga wrote: > This patch adds I2C support for STM32 default configuration > > Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> > --- Applied on stm32-defconfig-for-v4.12 Regards Alex > arch/arm/configs/stm32_defconfig | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig > index 5a72d69..323d2a3 100644 > --- a/arch/arm/configs/stm32_defconfig > +++ b/arch/arm/configs/stm32_defconfig > @@ -47,6 +47,9 @@ CONFIG_SERIAL_NONSTANDARD=y > CONFIG_SERIAL_STM32=y > CONFIG_SERIAL_STM32_CONSOLE=y > # CONFIG_HW_RANDOM is not set > +CONFIG_I2C=y > +CONFIG_I2C_CHARDEV=y > +CONFIG_I2C_STM32F4=y > # CONFIG_HWMON is not set > # CONFIG_USB_SUPPORT is not set > CONFIG_NEW_LEDS=y > ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v10 5/5] ARM: configs: stm32: Add I2C support for STM32 defconfig @ 2017-04-03 14:36 ` Alexandre Torgue 0 siblings, 0 replies; 27+ messages in thread From: Alexandre Torgue @ 2017-04-03 14:36 UTC (permalink / raw) To: M'boumba Cedric Madianga, wsa, robh+dt, mcoquelin.stm32, linus.walleij, patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, u.kleine-koenig Hi, On 01/19/2017 02:25 PM, M'boumba Cedric Madianga wrote: > This patch adds I2C support for STM32 default configuration > > Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> > --- Applied on stm32-defconfig-for-v4.12 Regards Alex > arch/arm/configs/stm32_defconfig | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig > index 5a72d69..323d2a3 100644 > --- a/arch/arm/configs/stm32_defconfig > +++ b/arch/arm/configs/stm32_defconfig > @@ -47,6 +47,9 @@ CONFIG_SERIAL_NONSTANDARD=y > CONFIG_SERIAL_STM32=y > CONFIG_SERIAL_STM32_CONSOLE=y > # CONFIG_HW_RANDOM is not set > +CONFIG_I2C=y > +CONFIG_I2C_CHARDEV=y > +CONFIG_I2C_STM32F4=y > # CONFIG_HWMON is not set > # CONFIG_USB_SUPPORT is not set > CONFIG_NEW_LEDS=y > ^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2017-04-03 14:36 UTC | newest] Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-01-19 13:25 [PATCH v10 0/5] Add support for the STM32F4 I2C M'boumba Cedric Madianga 2017-01-19 13:25 ` M'boumba Cedric Madianga 2017-01-19 13:25 ` [PATCH v10 1/5] dt-bindings: Document the STM32 I2C bindings M'boumba Cedric Madianga 2017-01-19 13:25 ` M'boumba Cedric Madianga 2017-01-25 20:24 ` Wolfram Sang 2017-01-25 20:24 ` Wolfram Sang 2017-01-19 13:25 ` [PATCH v10 2/5] i2c: Add STM32F4 I2C driver M'boumba Cedric Madianga 2017-01-19 13:25 ` M'boumba Cedric Madianga 2017-01-19 13:31 ` Uwe Kleine-König 2017-01-19 13:31 ` Uwe Kleine-König 2017-01-25 20:25 ` Wolfram Sang 2017-01-25 20:25 ` Wolfram Sang 2017-01-25 21:03 ` Uwe Kleine-König 2017-01-25 21:03 ` Uwe Kleine-König 2017-01-19 13:25 ` [PATCH v10 3/5] ARM: dts: stm32: Add I2C1 support for STM32F429 SoC M'boumba Cedric Madianga 2017-01-19 13:25 ` M'boumba Cedric Madianga 2017-01-25 20:25 ` Wolfram Sang 2017-01-25 20:25 ` Wolfram Sang 2017-01-25 21:02 ` M'boumba Cedric Madianga 2017-01-25 21:02 ` M'boumba Cedric Madianga 2017-01-19 13:25 ` [PATCH v10 4/5] ARM: dts: stm32: Add I2C1 support for STM32429 eval board M'boumba Cedric Madianga 2017-01-19 13:25 ` M'boumba Cedric Madianga 2017-01-19 13:25 ` [PATCH v10 5/5] ARM: configs: stm32: Add I2C support for STM32 defconfig M'boumba Cedric Madianga 2017-01-19 13:25 ` M'boumba Cedric Madianga 2017-04-03 14:36 ` Alexandre Torgue 2017-04-03 14:36 ` Alexandre Torgue 2017-04-03 14:36 ` Alexandre Torgue
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