* Re: [PATCH v2 1/2] drm_fourcc: Add new P010, P016 video format
2017-01-04 16:29 ` [PATCH v2 1/2] drm_fourcc: Add new P010, P016 video format Randy Li
@ 2017-01-04 17:02 ` Daniel Stone
2017-02-23 23:58 ` [PATCH v3 " clinton.a.taylor
` (3 subsequent siblings)
4 siblings, 0 replies; 30+ messages in thread
From: Daniel Stone @ 2017-01-04 17:02 UTC (permalink / raw)
To: Randy Li
Cc: dri-devel, Ville Syrjälä,
Li Randy, Linux Kernel Mailing List, Vetter, Daniel, mchehab,
linux-media
Hi Randy,
On 4 January 2017 at 16:29, Randy Li <ayaka@soulik.info> wrote:
> index 90d2cc8..23c8e99 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -165,6 +165,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
> + /* FIXME a pixel in Y for P010 is 10 bits */
> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2 },
It seems like P010 stores each Y component in a 16-bit value, with the
bottom 6 bits ignored. So I think cpp here should be 2.
Cheers,
Daniel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 1/2] drm_fourcc: Add new P010, P016 video format
@ 2017-01-04 17:02 ` Daniel Stone
0 siblings, 0 replies; 30+ messages in thread
From: Daniel Stone @ 2017-01-04 17:02 UTC (permalink / raw)
To: Randy Li
Cc: Li Randy, Linux Kernel Mailing List, dri-devel, Vetter, Daniel,
mchehab, linux-media
Hi Randy,
On 4 January 2017 at 16:29, Randy Li <ayaka@soulik.info> wrote:
> index 90d2cc8..23c8e99 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -165,6 +165,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
> + /* FIXME a pixel in Y for P010 is 10 bits */
> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2 },
It seems like P010 stores each Y component in a 16-bit value, with the
bottom 6 bits ignored. So I think cpp here should be 2.
Cheers,
Daniel
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 1/2] drm_fourcc: Add new P010, P016 video format
2017-01-04 17:02 ` Daniel Stone
(?)
@ 2017-01-05 2:00 ` Ayaka
2017-01-23 21:16 ` Clint Taylor
-1 siblings, 1 reply; 30+ messages in thread
From: Ayaka @ 2017-01-05 2:00 UTC (permalink / raw)
To: Daniel Stone
Cc: dri-devel, Ville Syrjälä,
Li Randy, Linux Kernel Mailing List, Vetter, Daniel, mchehab,
linux-media
從我的 iPad 傳送
> Daniel Stone <daniel@fooishbar.org> 於 2017年1月5日 上午1:02 寫道:
>
> Hi Randy,
>
>> On 4 January 2017 at 16:29, Randy Li <ayaka@soulik.info> wrote:
>> index 90d2cc8..23c8e99 100644
>> --- a/drivers/gpu/drm/drm_fourcc.c
>> +++ b/drivers/gpu/drm/drm_fourcc.c
>> @@ -165,6 +165,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
>> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
>> + /* FIXME a pixel in Y for P010 is 10 bits */
>> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2 },
>
> It seems like P010 stores each Y component in a 16-bit value, with the
> bottom 6 bits ignored. So I think cpp here should be 2.
No, the rest bits are used to store the next pixel. The P010 is just a 10 bits color depth pixel format.
>
> Cheers,
> Daniel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 1/2] drm_fourcc: Add new P010, P016 video format
2017-01-05 2:00 ` Ayaka
@ 2017-01-23 21:16 ` Clint Taylor
0 siblings, 0 replies; 30+ messages in thread
From: Clint Taylor @ 2017-01-23 21:16 UTC (permalink / raw)
To: dri-devel
On 01/04/2017 06:00 PM, Ayaka wrote:
>
>
> 從我的 iPad 傳送
>
>> Daniel Stone <daniel@fooishbar.org> 於 2017年1月5日 上午1:02 寫道:
>>
>> Hi Randy,
>>
>>> On 4 January 2017 at 16:29, Randy Li <ayaka@soulik.info> wrote:
>>> index 90d2cc8..23c8e99 100644
>>> --- a/drivers/gpu/drm/drm_fourcc.c
>>> +++ b/drivers/gpu/drm/drm_fourcc.c
>>> @@ -165,6 +165,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
>>> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>>> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>>> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
>>> + /* FIXME a pixel in Y for P010 is 10 bits */
>>> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2 },
>>
>> It seems like P010 stores each Y component in a 16-bit value, with the
>> bottom 6 bits ignored. So I think cpp here should be 2.
> No, the rest bits are used to store the next pixel. The P010 is just a 10 bits color depth pixel format.
The reviewer is correct. In P010 and P016 the memory layout is identical
as the luma and each Chroma channel are stored as words. .cpp = { 2, 4,
0 } for both P010 and P016.
-Clint
>>
>> Cheers,
>> Daniel
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 1/2] drm_fourcc: Add new P010, P016 video format
2017-01-04 16:29 ` [PATCH v2 1/2] drm_fourcc: Add new P010, P016 video format Randy Li
2017-01-04 17:02 ` Daniel Stone
@ 2017-02-23 23:58 ` clinton.a.taylor
2017-02-24 11:10 ` Ville Syrjälä
2017-02-27 17:21 ` [PATCH v4 " clinton.a.taylor
` (2 subsequent siblings)
4 siblings, 1 reply; 30+ messages in thread
From: clinton.a.taylor @ 2017-02-23 23:58 UTC (permalink / raw)
To: dri-devel; +Cc: Randy Li
From: Clint Taylor <clinton.a.taylor@intel.com>
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
channel video format. Rockchip's vop support this video format(little
endian only) as the input video format.
P012 is a planar 4:2:0 YUV 12 bits per channel
P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
channel video format.
V3: Added P012 and fixed cpp for P010
Cc: Daniel Stone <daniel@fooishbar.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/drm_fourcc.c | 4 ++++
include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 90d2cc8..5494764 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+ /* FIXME a pixel in Y for P010 is 10 bits */
+ { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index ef20abb..788dc36 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -128,6 +128,20 @@
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
+ * 2 plane YCbCr MSB aligned P0?? formats
+ * index 0 = Y plane, word array [15:6] P010
+ * index 0 = Y plane, word array [15:4] P012
+ * index 0 = Y plane, word array [15:0] P016
+ *
+ * index 1 = U [31:22], V [15:6] P010
+ * index 1 = U [31:20], V [15:4] P012
+ * index 1 = U [31:16], V [15:0] P016
+ */
+#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
+#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
+#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
--
1.7.9.5
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH v3 1/2] drm_fourcc: Add new P010, P016 video format
2017-02-23 23:58 ` [PATCH v3 " clinton.a.taylor
@ 2017-02-24 11:10 ` Ville Syrjälä
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjälä @ 2017-02-24 11:10 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Randy Li, dri-devel
On Thu, Feb 23, 2017 at 03:58:19PM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
> channel video format. Rockchip's vop support this video format(little
> endian only) as the input video format.
>
> P012 is a planar 4:2:0 YUV 12 bits per channel
>
> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
> channel video format.
>
> V3: Added P012 and fixed cpp for P010
>
> Cc: Daniel Stone <daniel@fooishbar.org>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Randy Li <ayaka@soulik.info>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/drm_fourcc.c | 4 ++++
> include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++
> 2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 90d2cc8..5494764 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
> + /* FIXME a pixel in Y for P010 is 10 bits */
> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> + { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> + { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> };
>
> unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index ef20abb..788dc36 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -128,6 +128,20 @@
> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>
> /*
> + * 2 plane YCbCr MSB aligned P0?? formats
> + * index 0 = Y plane, word array [15:6] P010
> + * index 0 = Y plane, word array [15:4] P012
> + * index 0 = Y plane, word array [15:0] P016
> + *
> + * index 1 = U [31:22], V [15:6] P010
> + * index 1 = U [31:20], V [15:4] P012
> + * index 1 = U [31:16], V [15:0] P016
We say Cb/Cr, not U/V. Also I'd like to see this explanation use the
standard notation we have in this file for describing what the bits
actually are. And we need to specify the endianness explicitly.
So something like this perhaps :)
https://lists.freedesktop.org/archives/dri-devel/2017-January/128808.html
> + */
> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
> +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
> +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
> +
> +/*
> * 3 plane YCbCr
> * index 0: Y plane, [7:0] Y
> * index 1: Cb plane, [7:0] Cb
> --
> 1.7.9.5
--
Ville Syrjälä
Intel OTC
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v4 1/2] drm_fourcc: Add new P010, P016 video format
2017-01-04 16:29 ` [PATCH v2 1/2] drm_fourcc: Add new P010, P016 video format Randy Li
2017-01-04 17:02 ` Daniel Stone
2017-02-23 23:58 ` [PATCH v3 " clinton.a.taylor
@ 2017-02-27 17:21 ` clinton.a.taylor
2017-02-27 17:41 ` Ville Syrjälä
2017-02-27 22:57 ` [PATCH v5 " clinton.a.taylor
2017-02-28 23:21 ` [PATCH v6 " clinton.a.taylor
4 siblings, 1 reply; 30+ messages in thread
From: clinton.a.taylor @ 2017-02-27 17:21 UTC (permalink / raw)
To: dri-devel; +Cc: Randy Li
From: Clint Taylor <clinton.a.taylor@intel.com>
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
channel video format. Rockchip's vop support this video format(little
endian only) as the input video format.
P016 is a planar 4:2:0 YUV 12 bits per channel
P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
channel video format.
V3: Added P012 and fixed cpp for P010
V4: format definition refined per review
Cc: Daniel Stone <daniel@fooishbar.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/drm_fourcc.c | 4 ++++
include/uapi/drm/drm_fourcc.h | 18 ++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 90d2cc8..5494764 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+ /* FIXME a pixel in Y for P010 is 10 bits */
+ { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index ef20abb..ad94464 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -128,6 +128,24 @@
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
+ * 2 plane YCbCr MSB aligned P0?? formats
+ * index 0 = Y plane, word array [15:6] P010
+ * or
+ * index 0 = Y plane, word array [15:4] P012
+ * or
+ * index 0 = Y plane, word array [15:0] P016
+ *
+ * index 1 = Cb:Cr plane, [31:22] Cb [15:6] Cr little endian P010
+ * or
+ * index 1 = Cb:Cr plane, [31:20] Cb [15:4] Cr little endian P012
+ * or
+ * index 1 = Cb:Cr plane, [31:16] Cb [15:0] Cr little endian P016
+ */
+#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cb:Cr plane 10 bits per channel */
+#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cb:Cr plane 12 bits per channel */
+#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cb:Cr plane 16 bits per channel */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
--
1.7.9.5
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH v4 1/2] drm_fourcc: Add new P010, P016 video format
2017-02-27 17:21 ` [PATCH v4 " clinton.a.taylor
@ 2017-02-27 17:41 ` Ville Syrjälä
2017-02-27 18:28 ` Clint Taylor
0 siblings, 1 reply; 30+ messages in thread
From: Ville Syrjälä @ 2017-02-27 17:41 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Randy Li, dri-devel
On Mon, Feb 27, 2017 at 09:21:09AM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
> channel video format. Rockchip's vop support this video format(little
> endian only) as the input video format.
>
> P016 is a planar 4:2:0 YUV 12 bits per channel
>
> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
> channel video format.
>
> V3: Added P012 and fixed cpp for P010
> V4: format definition refined per review
>
> Cc: Daniel Stone <daniel@fooishbar.org>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Randy Li <ayaka@soulik.info>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/drm_fourcc.c | 4 ++++
> include/uapi/drm/drm_fourcc.h | 18 ++++++++++++++++++
> 2 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 90d2cc8..5494764 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
> + /* FIXME a pixel in Y for P010 is 10 bits */
> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> + { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> + { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> };
What's this hunk doing here?
>
> unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index ef20abb..ad94464 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -128,6 +128,24 @@
> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>
> /*
> + * 2 plane YCbCr MSB aligned P0?? formats
> + * index 0 = Y plane, word array [15:6] P010
> + * or
> + * index 0 = Y plane, word array [15:4] P012
> + * or
> + * index 0 = Y plane, word array [15:0] P016
> + *
> + * index 1 = Cb:Cr plane, [31:22] Cb [15:6] Cr little endian P010
> + * or
> + * index 1 = Cb:Cr plane, [31:20] Cb [15:4] Cr little endian P012
> + * or
> + * index 1 = Cb:Cr plane, [31:16] Cb [15:0] Cr little endian P016
> + */
Still looks somewhat out of place when compared with the rest of the file.
> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cb:Cr plane 10 bits per channel */
> +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cb:Cr plane 12 bits per channel */
> +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cb:Cr plane 16 bits per channel */
> +
> +/*
> * 3 plane YCbCr
> * index 0: Y plane, [7:0] Y
> * index 1: Cb plane, [7:0] Cb
> --
> 1.7.9.5
--
Ville Syrjälä
Intel OTC
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v4 1/2] drm_fourcc: Add new P010, P016 video format
2017-02-27 17:41 ` Ville Syrjälä
@ 2017-02-27 18:28 ` Clint Taylor
2017-02-27 18:47 ` Ville Syrjälä
0 siblings, 1 reply; 30+ messages in thread
From: Clint Taylor @ 2017-02-27 18:28 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Randy Li, dri-devel
On 02/27/2017 09:41 AM, Ville Syrjälä wrote:
> On Mon, Feb 27, 2017 at 09:21:09AM -0800, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
>> channel video format. Rockchip's vop support this video format(little
>> endian only) as the input video format.
>>
>> P016 is a planar 4:2:0 YUV 12 bits per channel
>>
>> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
>> channel video format.
>>
>> V3: Added P012 and fixed cpp for P010
>> V4: format definition refined per review
>>
>> Cc: Daniel Stone <daniel@fooishbar.org>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Signed-off-by: Randy Li <ayaka@soulik.info>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> ---
>> drivers/gpu/drm/drm_fourcc.c | 4 ++++
>> include/uapi/drm/drm_fourcc.h | 18 ++++++++++++++++++
>> 2 files changed, 22 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
>> index 90d2cc8..5494764 100644
>> --- a/drivers/gpu/drm/drm_fourcc.c
>> +++ b/drivers/gpu/drm/drm_fourcc.c
>> @@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
>> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
>> + /* FIXME a pixel in Y for P010 is 10 bits */
>> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>> + { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>> + { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>> };
>
> What's this hunk doing here?
This hunk defines the memory layout definition to DRM, so framebuffers
can be checked to make sure they are large enough for the format. Can
you describe your concern here?
>
>>
>> unsigned int i;
>> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
>> index ef20abb..ad94464 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -128,6 +128,24 @@
>> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>>
>> /*
>> + * 2 plane YCbCr MSB aligned P0?? formats
>> + * index 0 = Y plane, word array [15:6] P010
>> + * or
>> + * index 0 = Y plane, word array [15:4] P012
>> + * or
>> + * index 0 = Y plane, word array [15:0] P016
>> + *
>> + * index 1 = Cb:Cr plane, [31:22] Cb [15:6] Cr little endian P010
>> + * or
>> + * index 1 = Cb:Cr plane, [31:20] Cb [15:4] Cr little endian P012
>> + * or
>> + * index 1 = Cb:Cr plane, [31:16] Cb [15:0] Cr little endian P016
>> + */
>
> Still looks somewhat out of place when compared with the rest of the file.
The other YUV entries in the file all have 8 bit definitions and are
easily grouped together. The P0?? formats change their number of bits.
The only way I see is to make the comments look like the other YUV
formats is to make each format have its own comment block describing the
layout. I feel it's better to group them together since the difference
between them (bpc) is minor.
perhaps moving the bit definitions to the defines, but then again it
won't look like the other YUV format. It will look more like the RGB
defines.
-Clint
>
>> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cb:Cr plane 10 bits per channel */
>> +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cb:Cr plane 12 bits per channel */
>> +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cb:Cr plane 16 bits per channel */
>> +
>> +/*
>> * 3 plane YCbCr
>> * index 0: Y plane, [7:0] Y
>> * index 1: Cb plane, [7:0] Cb
>> --
>> 1.7.9.5
>
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v4 1/2] drm_fourcc: Add new P010, P016 video format
2017-02-27 18:28 ` Clint Taylor
@ 2017-02-27 18:47 ` Ville Syrjälä
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjälä @ 2017-02-27 18:47 UTC (permalink / raw)
To: Clint Taylor; +Cc: Randy Li, dri-devel
On Mon, Feb 27, 2017 at 10:28:21AM -0800, Clint Taylor wrote:
> On 02/27/2017 09:41 AM, Ville Syrjälä wrote:
> > On Mon, Feb 27, 2017 at 09:21:09AM -0800, clinton.a.taylor@intel.com wrote:
> >> From: Clint Taylor <clinton.a.taylor@intel.com>
> >>
> >> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
> >> channel video format. Rockchip's vop support this video format(little
> >> endian only) as the input video format.
> >>
> >> P016 is a planar 4:2:0 YUV 12 bits per channel
> >>
> >> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
> >> channel video format.
> >>
> >> V3: Added P012 and fixed cpp for P010
> >> V4: format definition refined per review
> >>
> >> Cc: Daniel Stone <daniel@fooishbar.org>
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>
> >> Signed-off-by: Randy Li <ayaka@soulik.info>
> >> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> >> ---
> >> drivers/gpu/drm/drm_fourcc.c | 4 ++++
> >> include/uapi/drm/drm_fourcc.h | 18 ++++++++++++++++++
> >> 2 files changed, 22 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> >> index 90d2cc8..5494764 100644
> >> --- a/drivers/gpu/drm/drm_fourcc.c
> >> +++ b/drivers/gpu/drm/drm_fourcc.c
> >> @@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
> >> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> >> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> >> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
> >> + /* FIXME a pixel in Y for P010 is 10 bits */
> >> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> >> + { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> >> + { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> >> };
> >
> > What's this hunk doing here?
>
> This hunk defines the memory layout definition to DRM, so framebuffers
> can be checked to make sure they are large enough for the format. Can
> you describe your concern here?
Sorry. Just misread it hastily and thought it was something else. This
lgtm.
>
> >
> >>
> >> unsigned int i;
> >> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> >> index ef20abb..ad94464 100644
> >> --- a/include/uapi/drm/drm_fourcc.h
> >> +++ b/include/uapi/drm/drm_fourcc.h
> >> @@ -128,6 +128,24 @@
> >> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
> >>
> >> /*
> >> + * 2 plane YCbCr MSB aligned P0?? formats
> >> + * index 0 = Y plane, word array [15:6] P010
> >> + * or
> >> + * index 0 = Y plane, word array [15:4] P012
> >> + * or
> >> + * index 0 = Y plane, word array [15:0] P016
> >> + *
> >> + * index 1 = Cb:Cr plane, [31:22] Cb [15:6] Cr little endian P010
> >> + * or
> >> + * index 1 = Cb:Cr plane, [31:20] Cb [15:4] Cr little endian P012
> >> + * or
> >> + * index 1 = Cb:Cr plane, [31:16] Cb [15:0] Cr little endian P016
> >> + */
> >
> > Still looks somewhat out of place when compared with the rest of the file.
>
> The other YUV entries in the file all have 8 bit definitions and are
> easily grouped together. The P0?? formats change their number of bits.
> The only way I see is to make the comments look like the other YUV
> formats is to make each format have its own comment block describing the
> layout. I feel it's better to group them together since the difference
> between them (bpc) is minor.
>
> perhaps moving the bit definitions to the defines, but then again it
> won't look like the other YUV format. It will look more like the RGB
> defines.
I was mainly refrering to the way you specified the bits for each
component.
So to be consistent with most other things I think it
should look something like this:
"index 0 = Y plane, [15:0] Y:X 10:6 little endian"
"index 1 = Cr:Cb plane, [31:0] Cr:X:Cb:X 10:6:10:6 little endian"
That might not be the world's best notation, but consistency trumps
everything else here IMO. If someone has a good idea for a better
notation I'd like to see it. And if we change the notation for one
thing then we should change it for everything. Otherwise people
will get even more confused when reading this stuff.
>
> -Clint
>
> >
> >> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cb:Cr plane 10 bits per channel */
> >> +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cb:Cr plane 12 bits per channel */
> >> +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cb:Cr plane 16 bits per channel */
> >> +
> >> +/*
> >> * 3 plane YCbCr
> >> * index 0: Y plane, [7:0] Y
> >> * index 1: Cb plane, [7:0] Cb
> >> --
> >> 1.7.9.5
> >
--
Ville Syrjälä
Intel OTC
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v5 1/2] drm_fourcc: Add new P010, P016 video format
2017-01-04 16:29 ` [PATCH v2 1/2] drm_fourcc: Add new P010, P016 video format Randy Li
` (2 preceding siblings ...)
2017-02-27 17:21 ` [PATCH v4 " clinton.a.taylor
@ 2017-02-27 22:57 ` clinton.a.taylor
2017-02-28 10:58 ` ayaka
2017-02-28 11:56 ` Ville Syrjälä
2017-02-28 23:21 ` [PATCH v6 " clinton.a.taylor
4 siblings, 2 replies; 30+ messages in thread
From: clinton.a.taylor @ 2017-02-27 22:57 UTC (permalink / raw)
To: dri-devel; +Cc: Randy Li
From: Clint Taylor <clinton.a.taylor@intel.com>
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
channel video format. Rockchip's vop support this video format(little
endian only) as the input video format.
P016 is a planar 4:2:0 YUV 12 bits per channel
P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
channel video format.
V3: Added P012 and fixed cpp for P010
V4: format definition refined per review
V5: Format comment block for each new pixel format
Cc: Daniel Stone <daniel@fooishbar.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/drm_fourcc.c | 4 ++++
include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 90d2cc8..5494764 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+ /* FIXME a pixel in Y for P010 is 10 bits */
+ { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index ef20abb..306f979 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -128,6 +128,27 @@
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [10:6] little endian
+ * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [10:6:10:6] little endian
+ */
+#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cb:Cr plane 10 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [12:4] little endian
+ * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [12:4:12:4] little endian
+ */
+#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cb:Cr plane 12 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y little endian
+ * index 1 = Cb:Cr plane, [31:0] Cb:Cr [16:16] little endian
+ */
+#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cb:Cr plane 16 bits per channel */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] drm_fourcc: Add new P010, P016 video format
2017-02-27 22:57 ` [PATCH v5 " clinton.a.taylor
@ 2017-02-28 10:58 ` ayaka
2017-02-28 16:37 ` Clint Taylor
2017-02-28 11:56 ` Ville Syrjälä
1 sibling, 1 reply; 30+ messages in thread
From: ayaka @ 2017-02-28 10:58 UTC (permalink / raw)
To: clinton.a.taylor, dri-devel
On 02/28/2017 06:57 AM, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
> channel video format. Rockchip's vop support this video format(little
> endian only) as the input video format.
>
> P016 is a planar 4:2:0 YUV 12 bits per channel
>
> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
> channel video format.
>
> V3: Added P012 and fixed cpp for P010
> V4: format definition refined per review
> V5: Format comment block for each new pixel format
>
> Cc: Daniel Stone <daniel@fooishbar.org>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Randy Li <ayaka@soulik.info>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/drm_fourcc.c | 4 ++++
> include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
> 2 files changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 90d2cc8..5494764 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
> + /* FIXME a pixel in Y for P010 is 10 bits */
You may remove this line, I misunderstand the P010 that time.
What I want is adding a new pixel format never be defined before, may it
should be called P010_PACK
or something else.
> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> + { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> + { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> };
>
> unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index ef20abb..306f979 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -128,6 +128,27 @@
> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>
> /*
> + * 2 plane YCbCr MSB aligned
> + * index 0 = Y plane, [15:0] Y:x [10:6] little endian
> + * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [10:6:10:6] little endian
> + */
> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cb:Cr plane 10 bits per channel */
> +
> +/*
> + * 2 plane YCbCr MSB aligned
> + * index 0 = Y plane, [15:0] Y:x [12:4] little endian
> + * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [12:4:12:4] little endian
> + */
> +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cb:Cr plane 12 bits per channel */
> +
> +/*
> + * 2 plane YCbCr MSB aligned
> + * index 0 = Y plane, [15:0] Y little endian
> + * index 1 = Cb:Cr plane, [31:0] Cb:Cr [16:16] little endian
> + */
> +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cb:Cr plane 16 bits per channel */
> +
> +/*
> * 3 plane YCbCr
> * index 0: Y plane, [7:0] Y
> * index 1: Cb plane, [7:0] Cb
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] drm_fourcc: Add new P010, P016 video format
2017-02-28 10:58 ` ayaka
@ 2017-02-28 16:37 ` Clint Taylor
0 siblings, 0 replies; 30+ messages in thread
From: Clint Taylor @ 2017-02-28 16:37 UTC (permalink / raw)
To: ayaka, dri-devel
On 02/28/2017 02:58 AM, ayaka wrote:
>
>
> On 02/28/2017 06:57 AM, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
>> channel video format. Rockchip's vop support this video format(little
>> endian only) as the input video format.
>>
>> P016 is a planar 4:2:0 YUV 12 bits per channel
>>
>> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
>> channel video format.
>>
>> V3: Added P012 and fixed cpp for P010
>> V4: format definition refined per review
>> V5: Format comment block for each new pixel format
>>
>> Cc: Daniel Stone <daniel@fooishbar.org>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Signed-off-by: Randy Li <ayaka@soulik.info>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> ---
>> drivers/gpu/drm/drm_fourcc.c | 4 ++++
>> include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
>> 2 files changed, 25 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
>> index 90d2cc8..5494764 100644
>> --- a/drivers/gpu/drm/drm_fourcc.c
>> +++ b/drivers/gpu/drm/drm_fourcc.c
>> @@ -165,6 +165,10 @@ const struct drm_format_info
>> *__drm_format_info(u32 format)
>> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes
>> = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes
>> = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes
>> = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
>> + /* FIXME a pixel in Y for P010 is 10 bits */
> You may remove this line, I misunderstand the P010 that time.
That will look better. Thanks.
> What I want is adding a new pixel format never be defined before, may it
> should be called P010_PACK
We could probably add the PACK variants as DRM_FORMAT_P010V
> or something else.
>> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes
>> = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>> + { .format = DRM_FORMAT_P012, .depth = 0, .num_planes
>> = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>> + { .format = DRM_FORMAT_P016, .depth = 0, .num_planes
>> = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>> };
>> unsigned int i;
>> diff --git a/include/uapi/drm/drm_fourcc.h
>> b/include/uapi/drm/drm_fourcc.h
>> index ef20abb..306f979 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -128,6 +128,27 @@
>> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /*
>> non-subsampled Cb:Cr plane */
>> /*
>> + * 2 plane YCbCr MSB aligned
>> + * index 0 = Y plane, [15:0] Y:x [10:6] little endian
>> + * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [10:6:10:6] little endian
>> + */
>> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2
>> subsampled Cb:Cr plane 10 bits per channel */
>> +
>> +/*
>> + * 2 plane YCbCr MSB aligned
>> + * index 0 = Y plane, [15:0] Y:x [12:4] little endian
>> + * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [12:4:12:4] little endian
>> + */
>> +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2
>> subsampled Cb:Cr plane 12 bits per channel */
>> +
>> +/*
>> + * 2 plane YCbCr MSB aligned
>> + * index 0 = Y plane, [15:0] Y little endian
>> + * index 1 = Cb:Cr plane, [31:0] Cb:Cr [16:16] little endian
>> + */
>> +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2
>> subsampled Cb:Cr plane 16 bits per channel */
>> +
>> +/*
>> * 3 plane YCbCr
>> * index 0: Y plane, [7:0] Y
>> * index 1: Cb plane, [7:0] Cb
>
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] drm_fourcc: Add new P010, P016 video format
2017-02-27 22:57 ` [PATCH v5 " clinton.a.taylor
2017-02-28 10:58 ` ayaka
@ 2017-02-28 11:56 ` Ville Syrjälä
2017-02-28 16:08 ` Clint Taylor
1 sibling, 1 reply; 30+ messages in thread
From: Ville Syrjälä @ 2017-02-28 11:56 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Randy Li, dri-devel
On Mon, Feb 27, 2017 at 02:57:58PM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
> channel video format. Rockchip's vop support this video format(little
> endian only) as the input video format.
>
> P016 is a planar 4:2:0 YUV 12 bits per channel
>
> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
> channel video format.
>
> V3: Added P012 and fixed cpp for P010
> V4: format definition refined per review
> V5: Format comment block for each new pixel format
>
> Cc: Daniel Stone <daniel@fooishbar.org>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Randy Li <ayaka@soulik.info>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/drm_fourcc.c | 4 ++++
> include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
> 2 files changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 90d2cc8..5494764 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
> + /* FIXME a pixel in Y for P010 is 10 bits */
> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> + { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> + { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> };
>
> unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index ef20abb..306f979 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -128,6 +128,27 @@
> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>
> /*
> + * 2 plane YCbCr MSB aligned
> + * index 0 = Y plane, [15:0] Y:x [10:6] little endian
> + * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [10:6:10:6] little endian
> + */
Your Cb and Cr look swapped (unless my memory is playing tricks on me).
> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cb:Cr plane 10 bits per channel */
> +
> +/*
> + * 2 plane YCbCr MSB aligned
> + * index 0 = Y plane, [15:0] Y:x [12:4] little endian
> + * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [12:4:12:4] little endian
> + */
> +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cb:Cr plane 12 bits per channel */
> +
> +/*
> + * 2 plane YCbCr MSB aligned
> + * index 0 = Y plane, [15:0] Y little endian
> + * index 1 = Cb:Cr plane, [31:0] Cb:Cr [16:16] little endian
> + */
> +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cb:Cr plane 16 bits per channel */
> +
> +/*
> * 3 plane YCbCr
> * index 0: Y plane, [7:0] Y
> * index 1: Cb plane, [7:0] Cb
> --
> 1.7.9.5
--
Ville Syrjälä
Intel OTC
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] drm_fourcc: Add new P010, P016 video format
2017-02-28 11:56 ` Ville Syrjälä
@ 2017-02-28 16:08 ` Clint Taylor
2017-02-28 16:22 ` Ville Syrjälä
0 siblings, 1 reply; 30+ messages in thread
From: Clint Taylor @ 2017-02-28 16:08 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Randy Li, dri-devel
On 02/28/2017 03:56 AM, Ville Syrjälä wrote:
> On Mon, Feb 27, 2017 at 02:57:58PM -0800, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
>> channel video format. Rockchip's vop support this video format(little
>> endian only) as the input video format.
>>
>> P016 is a planar 4:2:0 YUV 12 bits per channel
>>
>> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
>> channel video format.
>>
>> V3: Added P012 and fixed cpp for P010
>> V4: format definition refined per review
>> V5: Format comment block for each new pixel format
>>
>> Cc: Daniel Stone <daniel@fooishbar.org>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Signed-off-by: Randy Li <ayaka@soulik.info>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> ---
>> drivers/gpu/drm/drm_fourcc.c | 4 ++++
>> include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
>> 2 files changed, 25 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
>> index 90d2cc8..5494764 100644
>> --- a/drivers/gpu/drm/drm_fourcc.c
>> +++ b/drivers/gpu/drm/drm_fourcc.c
>> @@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
>> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
>> + /* FIXME a pixel in Y for P010 is 10 bits */
>> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>> + { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>> + { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>> };
>>
>> unsigned int i;
>> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
>> index ef20abb..306f979 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -128,6 +128,27 @@
>> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>>
>> /*
>> + * 2 plane YCbCr MSB aligned
>> + * index 0 = Y plane, [15:0] Y:x [10:6] little endian
>> + * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [10:6:10:6] little endian
>> + */
>
> Your Cb and Cr look swapped (unless my memory is playing tricks on me).
This is the information I have:
Y U V
YUV 4:2:0 8 bpc - NV12 7:0 15:8 7:0
YUV 4:2:0 10 bpc - P010 15:6 31:22 15:6
YUV 4:2:0 12 bpc - P012 15:4 31:20 15:4
YUV 4:2:0 16 bpc - P016 15:0 31:16 15:0
-clint
>
>> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cb:Cr plane 10 bits per channel */
>> +
>> +/*
>> + * 2 plane YCbCr MSB aligned
>> + * index 0 = Y plane, [15:0] Y:x [12:4] little endian
>> + * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [12:4:12:4] little endian
>> + */
>> +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cb:Cr plane 12 bits per channel */
>> +
>> +/*
>> + * 2 plane YCbCr MSB aligned
>> + * index 0 = Y plane, [15:0] Y little endian
>> + * index 1 = Cb:Cr plane, [31:0] Cb:Cr [16:16] little endian
>> + */
>> +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cb:Cr plane 16 bits per channel */
>> +
>> +/*
>> * 3 plane YCbCr
>> * index 0: Y plane, [7:0] Y
>> * index 1: Cb plane, [7:0] Cb
>> --
>> 1.7.9.5
>
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] drm_fourcc: Add new P010, P016 video format
2017-02-28 16:08 ` Clint Taylor
@ 2017-02-28 16:22 ` Ville Syrjälä
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjälä @ 2017-02-28 16:22 UTC (permalink / raw)
To: Clint Taylor; +Cc: Randy Li, dri-devel
On Tue, Feb 28, 2017 at 08:08:55AM -0800, Clint Taylor wrote:
> On 02/28/2017 03:56 AM, Ville Syrjälä wrote:
> > On Mon, Feb 27, 2017 at 02:57:58PM -0800, clinton.a.taylor@intel.com wrote:
> >> From: Clint Taylor <clinton.a.taylor@intel.com>
> >>
> >> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
> >> channel video format. Rockchip's vop support this video format(little
> >> endian only) as the input video format.
> >>
> >> P016 is a planar 4:2:0 YUV 12 bits per channel
> >>
> >> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
> >> channel video format.
> >>
> >> V3: Added P012 and fixed cpp for P010
> >> V4: format definition refined per review
> >> V5: Format comment block for each new pixel format
> >>
> >> Cc: Daniel Stone <daniel@fooishbar.org>
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>
> >> Signed-off-by: Randy Li <ayaka@soulik.info>
> >> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> >> ---
> >> drivers/gpu/drm/drm_fourcc.c | 4 ++++
> >> include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
> >> 2 files changed, 25 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> >> index 90d2cc8..5494764 100644
> >> --- a/drivers/gpu/drm/drm_fourcc.c
> >> +++ b/drivers/gpu/drm/drm_fourcc.c
> >> @@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
> >> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> >> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> >> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
> >> + /* FIXME a pixel in Y for P010 is 10 bits */
> >> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> >> + { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> >> + { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> >> };
> >>
> >> unsigned int i;
> >> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> >> index ef20abb..306f979 100644
> >> --- a/include/uapi/drm/drm_fourcc.h
> >> +++ b/include/uapi/drm/drm_fourcc.h
> >> @@ -128,6 +128,27 @@
> >> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
> >>
> >> /*
> >> + * 2 plane YCbCr MSB aligned
> >> + * index 0 = Y plane, [15:0] Y:x [10:6] little endian
> >> + * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [10:6:10:6] little endian
> >> + */
> >
> > Your Cb and Cr look swapped (unless my memory is playing tricks on me).
>
> This is the information I have:
> Y U V
> YUV 4:2:0 8 bpc - NV12 7:0 15:8 7:0
> YUV 4:2:0 10 bpc - P010 15:6 31:22 15:6
> YUV 4:2:0 12 bpc - P012 15:4 31:20 15:4
> YUV 4:2:0 16 bpc - P016 15:0 31:16 15:0
I don't think those match the MS docs
https://msdn.microsoft.com/en-us/library/windows/desktop/bb970578%28v=vs.85%29.aspx
>
> -clint
>
> >
> >> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cb:Cr plane 10 bits per channel */
> >> +
> >> +/*
> >> + * 2 plane YCbCr MSB aligned
> >> + * index 0 = Y plane, [15:0] Y:x [12:4] little endian
> >> + * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [12:4:12:4] little endian
> >> + */
> >> +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cb:Cr plane 12 bits per channel */
> >> +
> >> +/*
> >> + * 2 plane YCbCr MSB aligned
> >> + * index 0 = Y plane, [15:0] Y little endian
> >> + * index 1 = Cb:Cr plane, [31:0] Cb:Cr [16:16] little endian
> >> + */
> >> +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cb:Cr plane 16 bits per channel */
> >> +
> >> +/*
> >> * 3 plane YCbCr
> >> * index 0: Y plane, [7:0] Y
> >> * index 1: Cb plane, [7:0] Cb
> >> --
> >> 1.7.9.5
> >
--
Ville Syrjälä
Intel OTC
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v6 1/2] drm_fourcc: Add new P010, P016 video format
2017-01-04 16:29 ` [PATCH v2 1/2] drm_fourcc: Add new P010, P016 video format Randy Li
` (3 preceding siblings ...)
2017-02-27 22:57 ` [PATCH v5 " clinton.a.taylor
@ 2017-02-28 23:21 ` clinton.a.taylor
2017-10-12 11:56 ` Tapani Pälli
4 siblings, 1 reply; 30+ messages in thread
From: clinton.a.taylor @ 2017-02-28 23:21 UTC (permalink / raw)
To: dri-devel; +Cc: Randy Li
From: Clint Taylor <clinton.a.taylor@intel.com>
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
channel video format. Rockchip's vop support this video format(little
endian only) as the input video format.
P016 is a planar 4:2:0 YUV 12 bits per channel
P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
channel video format.
V3: Added P012 and fixed cpp for P010
V4: format definition refined per review
V5: Format comment block for each new pixel format
V6: reversed Cb/Cr order in comments
Cc: Daniel Stone <daniel@fooishbar.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 90d2cc8..3e0fd58 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -165,6 +165,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index ef20abb..762646d 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -128,6 +128,27 @@
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [10:6] little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
+ */
+#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [12:4] little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
+ */
+#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
+ */
+#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH v6 1/2] drm_fourcc: Add new P010, P016 video format
2017-02-28 23:21 ` [PATCH v6 " clinton.a.taylor
@ 2017-10-12 11:56 ` Tapani Pälli
2017-10-17 11:43 ` ayaka
0 siblings, 1 reply; 30+ messages in thread
From: Tapani Pälli @ 2017-10-12 11:56 UTC (permalink / raw)
To: clinton.a.taylor, dri-devel; +Cc: Randy Li
Is this one going to land soon? The discussion was a bit hard to read
but it looks like in the end consensus was that everything looks good in
this patch.
Thanks;
On 03/01/2017 01:21 AM, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
> channel video format. Rockchip's vop support this video format(little
> endian only) as the input video format.
>
> P016 is a planar 4:2:0 YUV 12 bits per channel
>
> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
> channel video format.
>
> V3: Added P012 and fixed cpp for P010
> V4: format definition refined per review
> V5: Format comment block for each new pixel format
> V6: reversed Cb/Cr order in comments
>
> Cc: Daniel Stone <daniel@fooishbar.org>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Randy Li <ayaka@soulik.info>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/drm_fourcc.c | 3 +++
> include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 90d2cc8..3e0fd58 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -165,6 +165,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> + { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> + { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> };
>
> unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index ef20abb..762646d 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -128,6 +128,27 @@
> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>
> /*
> + * 2 plane YCbCr MSB aligned
> + * index 0 = Y plane, [15:0] Y:x [10:6] little endian
> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
> + */
> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
> +
> +/*
> + * 2 plane YCbCr MSB aligned
> + * index 0 = Y plane, [15:0] Y:x [12:4] little endian
> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
> + */
> +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
> +
> +/*
> + * 2 plane YCbCr MSB aligned
> + * index 0 = Y plane, [15:0] Y little endian
> + * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
> + */
> +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
> +
> +/*
> * 3 plane YCbCr
> * index 0: Y plane, [7:0] Y
> * index 1: Cb plane, [7:0] Cb
>
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v6 1/2] drm_fourcc: Add new P010, P016 video format
2017-10-12 11:56 ` Tapani Pälli
@ 2017-10-17 11:43 ` ayaka
2017-10-24 6:30 ` Tapani Pälli
0 siblings, 1 reply; 30+ messages in thread
From: ayaka @ 2017-10-17 11:43 UTC (permalink / raw)
To: Tapani Pälli; +Cc: dri-devel
On 10/12/2017 07:56 PM, Tapani Pälli wrote:
> Is this one going to land soon? The discussion was a bit hard to read
> but it looks like in the end consensus was that everything looks good
> in this patch.
I am very sorry, I am too busy with the other dma problem in rockchip.
The main problem is that none of the driver have used those format.
Although the rockchip vop supports 10 bit pixel format but not the p010.
>
> Thanks;
>
>
> On 03/01/2017 01:21 AM, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
>> channel video format. Rockchip's vop support this video format(little
>> endian only) as the input video format.
>>
>> P016 is a planar 4:2:0 YUV 12 bits per channel
>>
>> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
>> channel video format.
>>
>> V3: Added P012 and fixed cpp for P010
>> V4: format definition refined per review
>> V5: Format comment block for each new pixel format
>> V6: reversed Cb/Cr order in comments
>>
>> Cc: Daniel Stone <daniel@fooishbar.org>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Signed-off-by: Randy Li <ayaka@soulik.info>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> ---
>> drivers/gpu/drm/drm_fourcc.c | 3 +++
>> include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
>> 2 files changed, 24 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
>> index 90d2cc8..3e0fd58 100644
>> --- a/drivers/gpu/drm/drm_fourcc.c
>> +++ b/drivers/gpu/drm/drm_fourcc.c
>> @@ -165,6 +165,9 @@ const struct drm_format_info
>> *__drm_format_info(u32 format)
>> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes
>> = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes
>> = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes
>> = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
>> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes
>> = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>> + { .format = DRM_FORMAT_P012, .depth = 0, .num_planes
>> = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>> + { .format = DRM_FORMAT_P016, .depth = 0, .num_planes
>> = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>> };
>> unsigned int i;
>> diff --git a/include/uapi/drm/drm_fourcc.h
>> b/include/uapi/drm/drm_fourcc.h
>> index ef20abb..762646d 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -128,6 +128,27 @@
>> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /*
>> non-subsampled Cb:Cr plane */
>> /*
>> + * 2 plane YCbCr MSB aligned
>> + * index 0 = Y plane, [15:0] Y:x [10:6] little endian
>> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
>> + */
>> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /*
>> 2x2 subsampled Cr:Cb plane 10 bits per channel */
>> +
>> +/*
>> + * 2 plane YCbCr MSB aligned
>> + * index 0 = Y plane, [15:0] Y:x [12:4] little endian
>> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
>> + */
>> +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /*
>> 2x2 subsampled Cr:Cb plane 12 bits per channel */
>> +
>> +/*
>> + * 2 plane YCbCr MSB aligned
>> + * index 0 = Y plane, [15:0] Y little endian
>> + * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
>> + */
>> +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /*
>> 2x2 subsampled Cr:Cb plane 16 bits per channel */
>> +
>> +/*
>> * 3 plane YCbCr
>> * index 0: Y plane, [7:0] Y
>> * index 1: Cb plane, [7:0] Cb
>>
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* Re: [PATCH v6 1/2] drm_fourcc: Add new P010, P016 video format
2017-10-17 11:43 ` ayaka
@ 2017-10-24 6:30 ` Tapani Pälli
0 siblings, 0 replies; 30+ messages in thread
From: Tapani Pälli @ 2017-10-24 6:30 UTC (permalink / raw)
To: ayaka; +Cc: dri-devel
On 10/17/2017 02:43 PM, ayaka wrote:
>
>
> On 10/12/2017 07:56 PM, Tapani Pälli wrote:
>> Is this one going to land soon? The discussion was a bit hard to read
>> but it looks like in the end consensus was that everything looks good
>> in this patch.
> I am very sorry, I am too busy with the other dma problem in rockchip.
> The main problem is that none of the driver have used those format.
> Although the rockchip vop supports 10 bit pixel format but not the p010.
OK no worries, I thought these formats are already used by some driver.
>>
>> Thanks;
>>
>>
>> On 03/01/2017 01:21 AM, clinton.a.taylor@intel.com wrote:
>>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>>
>>> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
>>> channel video format. Rockchip's vop support this video format(little
>>> endian only) as the input video format.
>>>
>>> P016 is a planar 4:2:0 YUV 12 bits per channel
>>>
>>> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
>>> channel video format.
>>>
>>> V3: Added P012 and fixed cpp for P010
>>> V4: format definition refined per review
>>> V5: Format comment block for each new pixel format
>>> V6: reversed Cb/Cr order in comments
>>>
>>> Cc: Daniel Stone <daniel@fooishbar.org>
>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> Signed-off-by: Randy Li <ayaka@soulik.info>
>>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>>> ---
>>> drivers/gpu/drm/drm_fourcc.c | 3 +++
>>> include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
>>> 2 files changed, 24 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
>>> index 90d2cc8..3e0fd58 100644
>>> --- a/drivers/gpu/drm/drm_fourcc.c
>>> +++ b/drivers/gpu/drm/drm_fourcc.c
>>> @@ -165,6 +165,9 @@ const struct drm_format_info
>>> *__drm_format_info(u32 format)
>>> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes
>>> = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>>> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes
>>> = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>>> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes
>>> = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
>>> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes
>>> = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>>> + { .format = DRM_FORMAT_P012, .depth = 0, .num_planes
>>> = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>>> + { .format = DRM_FORMAT_P016, .depth = 0, .num_planes
>>> = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>>> };
>>> unsigned int i;
>>> diff --git a/include/uapi/drm/drm_fourcc.h
>>> b/include/uapi/drm/drm_fourcc.h
>>> index ef20abb..762646d 100644
>>> --- a/include/uapi/drm/drm_fourcc.h
>>> +++ b/include/uapi/drm/drm_fourcc.h
>>> @@ -128,6 +128,27 @@
>>> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /*
>>> non-subsampled Cb:Cr plane */
>>> /*
>>> + * 2 plane YCbCr MSB aligned
>>> + * index 0 = Y plane, [15:0] Y:x [10:6] little endian
>>> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
>>> + */
>>> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /*
>>> 2x2 subsampled Cr:Cb plane 10 bits per channel */
>>> +
>>> +/*
>>> + * 2 plane YCbCr MSB aligned
>>> + * index 0 = Y plane, [15:0] Y:x [12:4] little endian
>>> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
>>> + */
>>> +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /*
>>> 2x2 subsampled Cr:Cb plane 12 bits per channel */
>>> +
>>> +/*
>>> + * 2 plane YCbCr MSB aligned
>>> + * index 0 = Y plane, [15:0] Y little endian
>>> + * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
>>> + */
>>> +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /*
>>> 2x2 subsampled Cr:Cb plane 16 bits per channel */
>>> +
>>> +/*
>>> * 3 plane YCbCr
>>> * index 0: Y plane, [7:0] Y
>>> * index 1: Cb plane, [7:0] Cb
>>>
>
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