[PATCH v5 0/4] Altera Partial Reconfiguration IP

[PATCH v5 0/4] Altera Partial Reconfiguration IP

[matthew.gerlach]

From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

This set of patches implements a fpga-mgr driver for the Altera Partial
Reconfiguration IP.  The driver depends on a patch from Alan Tull that
adds a config complete timeout.  The driver code itself is divided into
core functions and functions to implement a platform driver. It is
expected that drivers for other buses like PCIe would also use the core
functions or possibly instantiate a platform driver.

Alan Tull (1):
  fpga: add config complete timeout

Matthew Gerlach (3):
  fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.
  fpga dt: bindings for Altera Partial Reconfiguration IP.
  fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.

 .../devicetree/bindings/fpga/altera-pr-ip.txt      |  12 ++
 drivers/fpga/Kconfig                               |  12 ++
 drivers/fpga/Makefile                              |   2 +
 drivers/fpga/altera-pr-ip-core-plat.c              |  65 ++++++
 drivers/fpga/altera-pr-ip-core.c                   | 217 +++++++++++++++++++++
 drivers/fpga/altera-pr-ip-core.h                   |  29 +++
 drivers/fpga/fpga-region.c                         |   3 +
 include/linux/fpga/fpga-mgr.h                      |   3 +
 8 files changed, 343 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
 create mode 100644 drivers/fpga/altera-pr-ip-core-plat.c
 create mode 100644 drivers/fpga/altera-pr-ip-core.c
 create mode 100644 drivers/fpga/altera-pr-ip-core.h

-- 
2.7.4

[PATCH v5 0/4] Altera Partial Reconfiguration IP

[matthew.gerlach-VuQAYsv1563Yd54FQh9/CA]

From: Matthew Gerlach <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>

This set of patches implements a fpga-mgr driver for the Altera Partial
Reconfiguration IP.  The driver depends on a patch from Alan Tull that
adds a config complete timeout.  The driver code itself is divided into
core functions and functions to implement a platform driver. It is
expected that drivers for other buses like PCIe would also use the core
functions or possibly instantiate a platform driver.

Alan Tull (1):
  fpga: add config complete timeout

Matthew Gerlach (3):
  fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.
  fpga dt: bindings for Altera Partial Reconfiguration IP.
  fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.

 .../devicetree/bindings/fpga/altera-pr-ip.txt      |  12 ++
 drivers/fpga/Kconfig                               |  12 ++
 drivers/fpga/Makefile                              |   2 +
 drivers/fpga/altera-pr-ip-core-plat.c              |  65 ++++++
 drivers/fpga/altera-pr-ip-core.c                   | 217 +++++++++++++++++++++
 drivers/fpga/altera-pr-ip-core.h                   |  29 +++
 drivers/fpga/fpga-region.c                         |   3 +
 include/linux/fpga/fpga-mgr.h                      |   3 +
 8 files changed, 343 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
 create mode 100644 drivers/fpga/altera-pr-ip-core-plat.c
 create mode 100644 drivers/fpga/altera-pr-ip-core.c
 create mode 100644 drivers/fpga/altera-pr-ip-core.h

-- 
2.7.4

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[PATCH v5 1/4] fpga: add config complete timeout

[matthew.gerlach]

From: Alan Tull <atull@opensource.altera.com>

Adding timeout for maximum allowed time for FPGA to go to
operating mode after a FPGA region has been programmed.

Signed-off-by: Alan Tull <atull@opensource.altera.com>
---
 drivers/fpga/fpga-region.c    | 3 +++
 include/linux/fpga/fpga-mgr.h | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
index 3222fdb..28401cb 100644
--- a/drivers/fpga/fpga-region.c
+++ b/drivers/fpga/fpga-region.c
@@ -381,6 +381,9 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
 	of_property_read_u32(nd->overlay, "region-freeze-timeout-us",
 			     &info->disable_timeout_us);
 
+	of_property_read_u32(nd->overlay, "config-complete-timeout-us",
+			     &info->config_complete_timeout_us);
+
 	/* If FPGA was externally programmed, don't specify firmware */
 	if ((info->flags & FPGA_MGR_EXTERNAL_CONFIG) && firmware_name) {
 		pr_err("error: specified firmware and external-fpga-config");
diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index 57beb5d..fd3f083 100644
--- a/include/linux/fpga/fpga-mgr.h
+++ b/include/linux/fpga/fpga-mgr.h
@@ -76,11 +76,14 @@ enum fpga_mgr_states {
  * @flags: boolean flags as defined above
  * @enable_timeout_us: maximum time to enable traffic through bridge (uSec)
  * @disable_timeout_us: maximum time to disable traffic through bridge (uSec)
+ * @config_complete_timeout_us: maximum time for FPGA to switch to operating
+ *	   status in the write_complete op.
  */
 struct fpga_image_info {
 	u32 flags;
 	u32 enable_timeout_us;
 	u32 disable_timeout_us;
+	u32 config_complete_timeout_us;
 };
 
 /**
-- 
2.7.4

[PATCH v5 1/4] fpga: add config complete timeout

[matthew.gerlach-VuQAYsv1563Yd54FQh9/CA]

From: Alan Tull <atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

Adding timeout for maximum allowed time for FPGA to go to
operating mode after a FPGA region has been programmed.

Signed-off-by: Alan Tull <atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
---
 drivers/fpga/fpga-region.c    | 3 +++
 include/linux/fpga/fpga-mgr.h | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
index 3222fdb..28401cb 100644
--- a/drivers/fpga/fpga-region.c
+++ b/drivers/fpga/fpga-region.c
@@ -381,6 +381,9 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
 	of_property_read_u32(nd->overlay, "region-freeze-timeout-us",
 			     &info->disable_timeout_us);
 
+	of_property_read_u32(nd->overlay, "config-complete-timeout-us",
+			     &info->config_complete_timeout_us);
+
 	/* If FPGA was externally programmed, don't specify firmware */
 	if ((info->flags & FPGA_MGR_EXTERNAL_CONFIG) && firmware_name) {
 		pr_err("error: specified firmware and external-fpga-config");
diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index 57beb5d..fd3f083 100644
--- a/include/linux/fpga/fpga-mgr.h
+++ b/include/linux/fpga/fpga-mgr.h
@@ -76,11 +76,14 @@ enum fpga_mgr_states {
  * @flags: boolean flags as defined above
  * @enable_timeout_us: maximum time to enable traffic through bridge (uSec)
  * @disable_timeout_us: maximum time to disable traffic through bridge (uSec)
+ * @config_complete_timeout_us: maximum time for FPGA to switch to operating
+ *	   status in the write_complete op.
  */
 struct fpga_image_info {
 	u32 flags;
 	u32 enable_timeout_us;
 	u32 disable_timeout_us;
+	u32 config_complete_timeout_us;
 };
 
 /**
-- 
2.7.4

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[PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[matthew.gerlach]

From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component.  It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v5:
    Fix comment as suggested by Rob Herring <robh@kernel.org>
v4:
    v3 patch set mistakenly sent out labeled as v4
v3:
    s/alt_pr_probe/alt_pr_register/
    s/alt_pr_remove/alt_pr_unregister/
---
 drivers/fpga/Kconfig             |   5 +
 drivers/fpga/Makefile            |   1 +
 drivers/fpga/altera-pr-ip-core.c | 217 +++++++++++++++++++++++++++++++++++++++
 drivers/fpga/altera-pr-ip-core.h |  29 ++++++
 4 files changed, 252 insertions(+)
 create mode 100644 drivers/fpga/altera-pr-ip-core.c
 create mode 100644 drivers/fpga/altera-pr-ip-core.h

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index ce861a2..a46c173 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -63,6 +63,11 @@ config ALTERA_FREEZE_BRIDGE
 	  isolate one region of the FPGA from the busses while that
 	  region is being reprogrammed.
 
+config ALTERA_PR_IP_CORE
+        tristate "Altera Partial Reconfiguration IP Core"
+        help
+          Core driver support for Altera Partial Reconfiguration IP component
+
 endif # FPGA
 
 endmenu
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 8df07bc..82693d2 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_FPGA)			+= fpga-mgr.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
+obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
 
 # FPGA Bridge Drivers
 obj-$(CONFIG_FPGA_BRIDGE)		+= fpga-bridge.o
diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera-pr-ip-core.c
new file mode 100644
index 0000000..738d7d1
--- /dev/null
+++ b/drivers/fpga/altera-pr-ip-core.c
@@ -0,0 +1,217 @@
+/*
+ * Driver for Altera Partial Reconfiguration IP Core
+ *
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
+ *  by Alan Tull <atull@opensource.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "altera-pr-ip-core.h"
+#include <linux/delay.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/module.h>
+
+#define ALT_PR_DATA_OFST		0x00
+#define ALT_PR_CSR_OFST			0x04
+
+#define ALT_PR_CSR_PR_START		BIT(0)
+#define ALT_PR_CSR_STATUS_SFT		2
+#define ALT_PR_CSR_STATUS_MSK		(7 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_NRESET	(0 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_PR_ERR	(1 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_CRC_ERR	(2 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_BAD_BITS	(3 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_PR_IN_PROG	(4 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_PR_SUCCESS	(5 << ALT_PR_CSR_STATUS_SFT)
+
+struct alt_pr_priv {
+	void __iomem *reg_base;
+};
+
+static enum fpga_mgr_states alt_pr_fpga_state(struct fpga_manager *mgr)
+{
+	struct alt_pr_priv *priv = mgr->priv;
+	const char *err = "unknown";
+	enum fpga_mgr_states ret = FPGA_MGR_STATE_UNKNOWN;
+	u32 val;
+
+	val = readl(priv->reg_base + ALT_PR_CSR_OFST);
+
+	val &= ALT_PR_CSR_STATUS_MSK;
+
+	switch (val) {
+	case ALT_PR_CSR_STATUS_NRESET:
+		return FPGA_MGR_STATE_RESET;
+
+	case ALT_PR_CSR_STATUS_PR_ERR:
+		err = "pr error";
+		ret = FPGA_MGR_STATE_WRITE_ERR;
+		break;
+
+	case ALT_PR_CSR_STATUS_CRC_ERR:
+		err = "crc error";
+		ret = FPGA_MGR_STATE_WRITE_ERR;
+		break;
+
+	case ALT_PR_CSR_STATUS_BAD_BITS:
+		err = "bad bits";
+		ret = FPGA_MGR_STATE_WRITE_ERR;
+		break;
+
+	case ALT_PR_CSR_STATUS_PR_IN_PROG:
+		return FPGA_MGR_STATE_WRITE;
+
+	case ALT_PR_CSR_STATUS_PR_SUCCESS:
+		return FPGA_MGR_STATE_OPERATING;
+
+	default:
+		break;
+	}
+
+	dev_err(&mgr->dev, "encountered error code %d (%s) in %s()\n",
+		val, err, __func__);
+	return ret;
+}
+
+static int alt_pr_fpga_write_init(struct fpga_manager *mgr,
+				  struct fpga_image_info *info,
+				  const char *buf, size_t count)
+{
+	struct alt_pr_priv *priv = mgr->priv;
+	u32 val;
+
+	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+		pr_err("%s Partial Reconfiguration flag not set\n", __func__);
+		return -EINVAL;
+	}
+
+	val = readl(priv->reg_base + ALT_PR_CSR_OFST);
+
+	if (val & ALT_PR_CSR_PR_START) {
+		pr_err("%s Partial Reconfiguration already started\n",
+		       __func__);
+		return -EINVAL;
+	}
+
+	writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST);
+
+	return 0;
+}
+
+static int alt_pr_fpga_write(struct fpga_manager *mgr, const char *buf,
+			     size_t count)
+{
+	struct alt_pr_priv *priv = mgr->priv;
+	u32 *buffer_32 = (u32 *)buf;
+	size_t i = 0;
+
+	if (count <= 0)
+		return -EINVAL;
+
+	/* Write out the complete 32-bit chunks */
+	while (count >= sizeof(u32)) {
+		writel(buffer_32[i++], priv->reg_base);
+		count -= sizeof(u32);
+	}
+
+	/* Write out remaining non 32-bit chunks */
+	switch (count) {
+	case 3:
+		writel(buffer_32[i++] & 0x00ffffff, priv->reg_base);
+		break;
+	case 2:
+		writel(buffer_32[i++] & 0x0000ffff, priv->reg_base);
+		break;
+	case 1:
+		writel(buffer_32[i++] & 0x000000ff, priv->reg_base);
+		break;
+	case 0:
+		break;
+	default:
+		/* This will never happen */
+		return -EFAULT;
+	}
+
+	if (alt_pr_fpga_state(mgr) == FPGA_MGR_STATE_WRITE_ERR)
+		return -EIO;
+
+	return 0;
+}
+
+static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
+				      struct fpga_image_info *info)
+{
+	u32 i;
+
+	for (i = 0; i < info->config_complete_timeout_us; i++) {
+		switch (alt_pr_fpga_state(mgr)) {
+		case FPGA_MGR_STATE_WRITE_ERR:
+			return -EIO;
+
+		case FPGA_MGR_STATE_OPERATING:
+			dev_info(&mgr->dev,
+				 "successful partial reconfiguration\n");
+			return 0;
+
+		default:
+			break;
+		}
+		udelay(1);
+	}
+	dev_err(&mgr->dev, "timed out waiting for write to complete\n");
+	return -ETIMEDOUT;
+}
+
+static const struct fpga_manager_ops alt_pr_ops = {
+	.state = alt_pr_fpga_state,
+	.write_init = alt_pr_fpga_write_init,
+	.write = alt_pr_fpga_write,
+	.write_complete = alt_pr_fpga_write_complete,
+};
+
+int alt_pr_register(struct device *dev, void __iomem *reg_base)
+{
+	struct alt_pr_priv *priv;
+	u32 val;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->reg_base = reg_base;
+
+	val = readl(priv->reg_base + ALT_PR_CSR_OFST);
+
+	dev_dbg(dev, "%s status=%d start=%d\n", __func__,
+		(val & ALT_PR_CSR_STATUS_MSK) >> ALT_PR_CSR_STATUS_SFT,
+		(int)(val & ALT_PR_CSR_PR_START));
+
+	return fpga_mgr_register(dev, dev_name(dev), &alt_pr_ops, priv);
+}
+EXPORT_SYMBOL_GPL(alt_pr_register);
+
+int alt_pr_unregister(struct device *dev)
+{
+	dev_dbg(dev, "%s\n", __func__);
+
+	fpga_mgr_unregister(dev);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(alt_pr_unregister);
+
+MODULE_AUTHOR("Matthew Gerlach <matthew.gerlach@linux.intel.com>");
+MODULE_DESCRIPTION("Altera Partial Reconfiguration IP Core");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/fpga/altera-pr-ip-core.h b/drivers/fpga/altera-pr-ip-core.h
new file mode 100644
index 0000000..3810a90
--- /dev/null
+++ b/drivers/fpga/altera-pr-ip-core.h
@@ -0,0 +1,29 @@
+/*
+ * Driver for Altera Partial Reconfiguration IP Core
+ *
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
+ *  by Alan Tull <atull@opensource.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ALT_PR_IP_CORE_H
+#define _ALT_PR_IP_CORE_H
+#include <linux/io.h>
+
+int alt_pr_register(struct device *dev, void __iomem *reg_base);
+int alt_pr_unregister(struct device *dev);
+
+#endif /* _ALT_PR_IP_CORE_H */
-- 
2.7.4

[PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[matthew.gerlach-VuQAYsv1563Yd54FQh9/CA]

From: Matthew Gerlach <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>

Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component.  It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.

Signed-off-by: Matthew Gerlach <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
---
v5:
    Fix comment as suggested by Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
v4:
    v3 patch set mistakenly sent out labeled as v4
v3:
    s/alt_pr_probe/alt_pr_register/
    s/alt_pr_remove/alt_pr_unregister/
---
 drivers/fpga/Kconfig             |   5 +
 drivers/fpga/Makefile            |   1 +
 drivers/fpga/altera-pr-ip-core.c | 217 +++++++++++++++++++++++++++++++++++++++
 drivers/fpga/altera-pr-ip-core.h |  29 ++++++
 4 files changed, 252 insertions(+)
 create mode 100644 drivers/fpga/altera-pr-ip-core.c
 create mode 100644 drivers/fpga/altera-pr-ip-core.h

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index ce861a2..a46c173 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -63,6 +63,11 @@ config ALTERA_FREEZE_BRIDGE
 	  isolate one region of the FPGA from the busses while that
 	  region is being reprogrammed.
 
+config ALTERA_PR_IP_CORE
+        tristate "Altera Partial Reconfiguration IP Core"
+        help
+          Core driver support for Altera Partial Reconfiguration IP component
+
 endif # FPGA
 
 endmenu
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 8df07bc..82693d2 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_FPGA)			+= fpga-mgr.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
+obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
 
 # FPGA Bridge Drivers
 obj-$(CONFIG_FPGA_BRIDGE)		+= fpga-bridge.o
diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera-pr-ip-core.c
new file mode 100644
index 0000000..738d7d1
--- /dev/null
+++ b/drivers/fpga/altera-pr-ip-core.c
@@ -0,0 +1,217 @@
+/*
+ * Driver for Altera Partial Reconfiguration IP Core
+ *
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
+ *  by Alan Tull <atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "altera-pr-ip-core.h"
+#include <linux/delay.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/module.h>
+
+#define ALT_PR_DATA_OFST		0x00
+#define ALT_PR_CSR_OFST			0x04
+
+#define ALT_PR_CSR_PR_START		BIT(0)
+#define ALT_PR_CSR_STATUS_SFT		2
+#define ALT_PR_CSR_STATUS_MSK		(7 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_NRESET	(0 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_PR_ERR	(1 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_CRC_ERR	(2 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_BAD_BITS	(3 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_PR_IN_PROG	(4 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_PR_SUCCESS	(5 << ALT_PR_CSR_STATUS_SFT)
+
+struct alt_pr_priv {
+	void __iomem *reg_base;
+};
+
+static enum fpga_mgr_states alt_pr_fpga_state(struct fpga_manager *mgr)
+{
+	struct alt_pr_priv *priv = mgr->priv;
+	const char *err = "unknown";
+	enum fpga_mgr_states ret = FPGA_MGR_STATE_UNKNOWN;
+	u32 val;
+
+	val = readl(priv->reg_base + ALT_PR_CSR_OFST);
+
+	val &= ALT_PR_CSR_STATUS_MSK;
+
+	switch (val) {
+	case ALT_PR_CSR_STATUS_NRESET:
+		return FPGA_MGR_STATE_RESET;
+
+	case ALT_PR_CSR_STATUS_PR_ERR:
+		err = "pr error";
+		ret = FPGA_MGR_STATE_WRITE_ERR;
+		break;
+
+	case ALT_PR_CSR_STATUS_CRC_ERR:
+		err = "crc error";
+		ret = FPGA_MGR_STATE_WRITE_ERR;
+		break;
+
+	case ALT_PR_CSR_STATUS_BAD_BITS:
+		err = "bad bits";
+		ret = FPGA_MGR_STATE_WRITE_ERR;
+		break;
+
+	case ALT_PR_CSR_STATUS_PR_IN_PROG:
+		return FPGA_MGR_STATE_WRITE;
+
+	case ALT_PR_CSR_STATUS_PR_SUCCESS:
+		return FPGA_MGR_STATE_OPERATING;
+
+	default:
+		break;
+	}
+
+	dev_err(&mgr->dev, "encountered error code %d (%s) in %s()\n",
+		val, err, __func__);
+	return ret;
+}
+
+static int alt_pr_fpga_write_init(struct fpga_manager *mgr,
+				  struct fpga_image_info *info,
+				  const char *buf, size_t count)
+{
+	struct alt_pr_priv *priv = mgr->priv;
+	u32 val;
+
+	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+		pr_err("%s Partial Reconfiguration flag not set\n", __func__);
+		return -EINVAL;
+	}
+
+	val = readl(priv->reg_base + ALT_PR_CSR_OFST);
+
+	if (val & ALT_PR_CSR_PR_START) {
+		pr_err("%s Partial Reconfiguration already started\n",
+		       __func__);
+		return -EINVAL;
+	}
+
+	writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST);
+
+	return 0;
+}
+
+static int alt_pr_fpga_write(struct fpga_manager *mgr, const char *buf,
+			     size_t count)
+{
+	struct alt_pr_priv *priv = mgr->priv;
+	u32 *buffer_32 = (u32 *)buf;
+	size_t i = 0;
+
+	if (count <= 0)
+		return -EINVAL;
+
+	/* Write out the complete 32-bit chunks */
+	while (count >= sizeof(u32)) {
+		writel(buffer_32[i++], priv->reg_base);
+		count -= sizeof(u32);
+	}
+
+	/* Write out remaining non 32-bit chunks */
+	switch (count) {
+	case 3:
+		writel(buffer_32[i++] & 0x00ffffff, priv->reg_base);
+		break;
+	case 2:
+		writel(buffer_32[i++] & 0x0000ffff, priv->reg_base);
+		break;
+	case 1:
+		writel(buffer_32[i++] & 0x000000ff, priv->reg_base);
+		break;
+	case 0:
+		break;
+	default:
+		/* This will never happen */
+		return -EFAULT;
+	}
+
+	if (alt_pr_fpga_state(mgr) == FPGA_MGR_STATE_WRITE_ERR)
+		return -EIO;
+
+	return 0;
+}
+
+static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
+				      struct fpga_image_info *info)
+{
+	u32 i;
+
+	for (i = 0; i < info->config_complete_timeout_us; i++) {
+		switch (alt_pr_fpga_state(mgr)) {
+		case FPGA_MGR_STATE_WRITE_ERR:
+			return -EIO;
+
+		case FPGA_MGR_STATE_OPERATING:
+			dev_info(&mgr->dev,
+				 "successful partial reconfiguration\n");
+			return 0;
+
+		default:
+			break;
+		}
+		udelay(1);
+	}
+	dev_err(&mgr->dev, "timed out waiting for write to complete\n");
+	return -ETIMEDOUT;
+}
+
+static const struct fpga_manager_ops alt_pr_ops = {
+	.state = alt_pr_fpga_state,
+	.write_init = alt_pr_fpga_write_init,
+	.write = alt_pr_fpga_write,
+	.write_complete = alt_pr_fpga_write_complete,
+};
+
+int alt_pr_register(struct device *dev, void __iomem *reg_base)
+{
+	struct alt_pr_priv *priv;
+	u32 val;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->reg_base = reg_base;
+
+	val = readl(priv->reg_base + ALT_PR_CSR_OFST);
+
+	dev_dbg(dev, "%s status=%d start=%d\n", __func__,
+		(val & ALT_PR_CSR_STATUS_MSK) >> ALT_PR_CSR_STATUS_SFT,
+		(int)(val & ALT_PR_CSR_PR_START));
+
+	return fpga_mgr_register(dev, dev_name(dev), &alt_pr_ops, priv);
+}
+EXPORT_SYMBOL_GPL(alt_pr_register);
+
+int alt_pr_unregister(struct device *dev)
+{
+	dev_dbg(dev, "%s\n", __func__);
+
+	fpga_mgr_unregister(dev);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(alt_pr_unregister);
+
+MODULE_AUTHOR("Matthew Gerlach <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>");
+MODULE_DESCRIPTION("Altera Partial Reconfiguration IP Core");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/fpga/altera-pr-ip-core.h b/drivers/fpga/altera-pr-ip-core.h
new file mode 100644
index 0000000..3810a90
--- /dev/null
+++ b/drivers/fpga/altera-pr-ip-core.h
@@ -0,0 +1,29 @@
+/*
+ * Driver for Altera Partial Reconfiguration IP Core
+ *
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
+ *  by Alan Tull <atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ALT_PR_IP_CORE_H
+#define _ALT_PR_IP_CORE_H
+#include <linux/io.h>
+
+int alt_pr_register(struct device *dev, void __iomem *reg_base);
+int alt_pr_unregister(struct device *dev);
+
+#endif /* _ALT_PR_IP_CORE_H */
-- 
2.7.4

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[PATCH v5 3/4] fpga dt: bindings for Altera Partial Reconfiguration IP.

[matthew.gerlach]

From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

Device Tree bindings for Altera Partial Reconfiguration IP.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v5:
    fix comment as suggested by Rob Herring <robh@kernel.org>
    added Acked-by: Rob Herring <robh@kernel.org>
v4: v3 patch set mistakenly sent out labeled as v4
v3: s/altr,pr-ip/altr,a10-pr-ip/
v2: s/Reconfiguraion/Reconfiguration/
---
 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt

diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
new file mode 100644
index 0000000..52a294c
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
@@ -0,0 +1,12 @@
+Altera Arria10 Partial Reconfiguration IP
+
+Required properties:
+- compatible : should contain "altr,a10-pr-ip"
+- reg        : base address and size for memory mapped io.
+
+Example:
+
+	fpga_mgr: fpga-mgr@ff20c000 {
+		compatible = "altr,a10-pr-ip";
+		reg = <0xff20c000 0x10>;
+	};
-- 
2.7.4

[PATCH v5 3/4] fpga dt: bindings for Altera Partial Reconfiguration IP.

[matthew.gerlach-VuQAYsv1563Yd54FQh9/CA]

From: Matthew Gerlach <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>

Device Tree bindings for Altera Partial Reconfiguration IP.

Signed-off-by: Matthew Gerlach <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
v5:
    fix comment as suggested by Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
    added Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
v4: v3 patch set mistakenly sent out labeled as v4
v3: s/altr,pr-ip/altr,a10-pr-ip/
v2: s/Reconfiguraion/Reconfiguration/
---
 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt

diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
new file mode 100644
index 0000000..52a294c
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
@@ -0,0 +1,12 @@
+Altera Arria10 Partial Reconfiguration IP
+
+Required properties:
+- compatible : should contain "altr,a10-pr-ip"
+- reg        : base address and size for memory mapped io.
+
+Example:
+
+	fpga_mgr: fpga-mgr@ff20c000 {
+		compatible = "altr,a10-pr-ip";
+		reg = <0xff20c000 0x10>;
+	};
-- 
2.7.4

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[PATCH v5 4/4] fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.

[matthew.gerlach]

From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

This adds a platform bus driver for a fpga-mgr driver
that uses the Altera Partial Reconfiguration IP component.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v5: fix comment as suggested by Rob Herring <robh@kernel.org>
v4: v3 patch set mistakenly sent out labeled as v4
v3:
    s/altr,pr-ip/altr,a10-pr-ip/
    s/alt_pr_probe/alt_pr_register/
    s/alt_pr_remove/alt_pr_unregister/
    fix error found by kbuild robot with more precise Kconfig depends

v2: s/altr,pr-ip-core/altr,pr-ip/
---
 drivers/fpga/Kconfig                  |  7 ++++
 drivers/fpga/Makefile                 |  1 +
 drivers/fpga/altera-pr-ip-core-plat.c | 65 +++++++++++++++++++++++++++++++++++
 3 files changed, 73 insertions(+)
 create mode 100644 drivers/fpga/altera-pr-ip-core-plat.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index a46c173..0c51427 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -68,6 +68,13 @@ config ALTERA_PR_IP_CORE
         help
           Core driver support for Altera Partial Reconfiguration IP component
 
+config ALTERA_PR_IP_CORE_PLAT
+	tristate "Platform support of Altera Partial Reconfiguration IP Core"
+	depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
+	help
+	  Platform driver support for Altera Partial Reconfiguration IP
+	  component
+
 endif # FPGA
 
 endmenu
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 82693d2..5b8ae2b 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
+obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
 
 # FPGA Bridge Drivers
 obj-$(CONFIG_FPGA_BRIDGE)		+= fpga-bridge.o
diff --git a/drivers/fpga/altera-pr-ip-core-plat.c b/drivers/fpga/altera-pr-ip-core-plat.c
new file mode 100644
index 0000000..cff189a
--- /dev/null
+++ b/drivers/fpga/altera-pr-ip-core-plat.c
@@ -0,0 +1,65 @@
+/*
+ * Driver for Altera Partial Reconfiguration IP Core
+ *
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
+ *  by Alan Tull <atull@opensource.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "altera-pr-ip-core.h"
+#include <linux/module.h>
+#include <linux/of_device.h>
+
+static int alt_pr_platform_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	void __iomem *reg_base;
+	struct resource *res;
+
+	/* First mmio base is for register access */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	reg_base = devm_ioremap_resource(dev, res);
+
+	if (IS_ERR(reg_base))
+		return PTR_ERR(reg_base);
+
+	return alt_pr_register(dev, reg_base);
+}
+
+static int alt_pr_platform_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+
+	return alt_pr_unregister(dev);
+}
+
+static const struct of_device_id alt_pr_of_match[] = {
+	{ .compatible = "altr,a10-pr-ip", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, alt_pr_of_match);
+
+static struct platform_driver alt_pr_platform_driver = {
+	.probe = alt_pr_platform_probe,
+	.remove = alt_pr_platform_remove,
+	.driver = {
+		.name	= "alt_a10_pr_ip",
+		.of_match_table = alt_pr_of_match,
+	},
+};
+
+module_platform_driver(alt_pr_platform_driver);
-- 
2.7.4

[PATCH v5 4/4] fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.

[matthew.gerlach-VuQAYsv1563Yd54FQh9/CA]

From: Matthew Gerlach <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>

This adds a platform bus driver for a fpga-mgr driver
that uses the Altera Partial Reconfiguration IP component.

Signed-off-by: Matthew Gerlach <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
---
v5: fix comment as suggested by Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
v4: v3 patch set mistakenly sent out labeled as v4
v3:
    s/altr,pr-ip/altr,a10-pr-ip/
    s/alt_pr_probe/alt_pr_register/
    s/alt_pr_remove/alt_pr_unregister/
    fix error found by kbuild robot with more precise Kconfig depends

v2: s/altr,pr-ip-core/altr,pr-ip/
---
 drivers/fpga/Kconfig                  |  7 ++++
 drivers/fpga/Makefile                 |  1 +
 drivers/fpga/altera-pr-ip-core-plat.c | 65 +++++++++++++++++++++++++++++++++++
 3 files changed, 73 insertions(+)
 create mode 100644 drivers/fpga/altera-pr-ip-core-plat.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index a46c173..0c51427 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -68,6 +68,13 @@ config ALTERA_PR_IP_CORE
         help
           Core driver support for Altera Partial Reconfiguration IP component
 
+config ALTERA_PR_IP_CORE_PLAT
+	tristate "Platform support of Altera Partial Reconfiguration IP Core"
+	depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
+	help
+	  Platform driver support for Altera Partial Reconfiguration IP
+	  component
+
 endif # FPGA
 
 endmenu
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 82693d2..5b8ae2b 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
+obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
 
 # FPGA Bridge Drivers
 obj-$(CONFIG_FPGA_BRIDGE)		+= fpga-bridge.o
diff --git a/drivers/fpga/altera-pr-ip-core-plat.c b/drivers/fpga/altera-pr-ip-core-plat.c
new file mode 100644
index 0000000..cff189a
--- /dev/null
+++ b/drivers/fpga/altera-pr-ip-core-plat.c
@@ -0,0 +1,65 @@
+/*
+ * Driver for Altera Partial Reconfiguration IP Core
+ *
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
+ *  by Alan Tull <atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "altera-pr-ip-core.h"
+#include <linux/module.h>
+#include <linux/of_device.h>
+
+static int alt_pr_platform_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	void __iomem *reg_base;
+	struct resource *res;
+
+	/* First mmio base is for register access */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	reg_base = devm_ioremap_resource(dev, res);
+
+	if (IS_ERR(reg_base))
+		return PTR_ERR(reg_base);
+
+	return alt_pr_register(dev, reg_base);
+}
+
+static int alt_pr_platform_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+
+	return alt_pr_unregister(dev);
+}
+
+static const struct of_device_id alt_pr_of_match[] = {
+	{ .compatible = "altr,a10-pr-ip", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, alt_pr_of_match);
+
+static struct platform_driver alt_pr_platform_driver = {
+	.probe = alt_pr_platform_probe,
+	.remove = alt_pr_platform_remove,
+	.driver = {
+		.name	= "alt_a10_pr_ip",
+		.of_match_table = alt_pr_of_match,
+	},
+};
+
+module_platform_driver(alt_pr_platform_driver);
-- 
2.7.4

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Re: [PATCH v5 0/4] Altera Partial Reconfiguration IP

[Moritz Fischer]

Hi Matthew,

On Fri, Mar 10, 2017 at 11:40 AM,  <matthew.gerlach@linux.intel.com> wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
> This set of patches implements a fpga-mgr driver for the Altera Partial
> Reconfiguration IP.  The driver depends on a patch from Alan Tull that
> adds a config complete timeout.  The driver code itself is divided into
> core functions and functions to implement a platform driver. It is
> expected that drivers for other buses like PCIe would also use the core
> functions or possibly instantiate a platform driver.
>
> Alan Tull (1):
>   fpga: add config complete timeout
>
> Matthew Gerlach (3):
>   fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.
>   fpga dt: bindings for Altera Partial Reconfiguration IP.

I think in general dt bindings should go in first in a series. Doesn't
checkpatch
complain about this?

>   fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.
>
>  .../devicetree/bindings/fpga/altera-pr-ip.txt      |  12 ++
>  drivers/fpga/Kconfig                               |  12 ++
>  drivers/fpga/Makefile                              |   2 +
>  drivers/fpga/altera-pr-ip-core-plat.c              |  65 ++++++
>  drivers/fpga/altera-pr-ip-core.c                   | 217 +++++++++++++++++++++
>  drivers/fpga/altera-pr-ip-core.h                   |  29 +++
>  drivers/fpga/fpga-region.c                         |   3 +
>  include/linux/fpga/fpga-mgr.h                      |   3 +
>  8 files changed, 343 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
>  create mode 100644 drivers/fpga/altera-pr-ip-core-plat.c
>  create mode 100644 drivers/fpga/altera-pr-ip-core.c
>  create mode 100644 drivers/fpga/altera-pr-ip-core.h

Cheers,
Moritz

Re: [PATCH v5 0/4] Altera Partial Reconfiguration IP

[Moritz Fischer]

Hi Matthew,

On Fri, Mar 10, 2017 at 11:40 AM,  <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> wrote:
> From: Matthew Gerlach <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
>
> This set of patches implements a fpga-mgr driver for the Altera Partial
> Reconfiguration IP.  The driver depends on a patch from Alan Tull that
> adds a config complete timeout.  The driver code itself is divided into
> core functions and functions to implement a platform driver. It is
> expected that drivers for other buses like PCIe would also use the core
> functions or possibly instantiate a platform driver.
>
> Alan Tull (1):
>   fpga: add config complete timeout
>
> Matthew Gerlach (3):
>   fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.
>   fpga dt: bindings for Altera Partial Reconfiguration IP.

I think in general dt bindings should go in first in a series. Doesn't
checkpatch
complain about this?

>   fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.
>
>  .../devicetree/bindings/fpga/altera-pr-ip.txt      |  12 ++
>  drivers/fpga/Kconfig                               |  12 ++
>  drivers/fpga/Makefile                              |   2 +
>  drivers/fpga/altera-pr-ip-core-plat.c              |  65 ++++++
>  drivers/fpga/altera-pr-ip-core.c                   | 217 +++++++++++++++++++++
>  drivers/fpga/altera-pr-ip-core.h                   |  29 +++
>  drivers/fpga/fpga-region.c                         |   3 +
>  include/linux/fpga/fpga-mgr.h                      |   3 +
>  8 files changed, 343 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
>  create mode 100644 drivers/fpga/altera-pr-ip-core-plat.c
>  create mode 100644 drivers/fpga/altera-pr-ip-core.c
>  create mode 100644 drivers/fpga/altera-pr-ip-core.h

Cheers,
Moritz
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Re: [PATCH v5 1/4] fpga: add config complete timeout

[Moritz Fischer]

On Fri, Mar 10, 2017 at 11:40 AM,  <matthew.gerlach@linux.intel.com> wrote:
> From: Alan Tull <atull@opensource.altera.com>
>
> Adding timeout for maximum allowed time for FPGA to go to
> operating mode after a FPGA region has been programmed.
>
> Signed-off-by: Alan Tull <atull@opensource.altera.com>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
>  drivers/fpga/fpga-region.c    | 3 +++
>  include/linux/fpga/fpga-mgr.h | 3 +++
>  2 files changed, 6 insertions(+)
>
> diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
> index 3222fdb..28401cb 100644
> --- a/drivers/fpga/fpga-region.c
> +++ b/drivers/fpga/fpga-region.c
> @@ -381,6 +381,9 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
>         of_property_read_u32(nd->overlay, "region-freeze-timeout-us",
>                              &info->disable_timeout_us);
>
> +       of_property_read_u32(nd->overlay, "config-complete-timeout-us",
> +                            &info->config_complete_timeout_us);
> +
>         /* If FPGA was externally programmed, don't specify firmware */
>         if ((info->flags & FPGA_MGR_EXTERNAL_CONFIG) && firmware_name) {
>                 pr_err("error: specified firmware and external-fpga-config");
> diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
> index 57beb5d..fd3f083 100644
> --- a/include/linux/fpga/fpga-mgr.h
> +++ b/include/linux/fpga/fpga-mgr.h
> @@ -76,11 +76,14 @@ enum fpga_mgr_states {
>   * @flags: boolean flags as defined above
>   * @enable_timeout_us: maximum time to enable traffic through bridge (uSec)
>   * @disable_timeout_us: maximum time to disable traffic through bridge (uSec)
> + * @config_complete_timeout_us: maximum time for FPGA to switch to operating
> + *        status in the write_complete op.
>   */
>  struct fpga_image_info {
>         u32 flags;
>         u32 enable_timeout_us;
>         u32 disable_timeout_us;
> +       u32 config_complete_timeout_us;
>  };
>
>  /**
> --
> 2.7.4
>

Re: [PATCH v5 1/4] fpga: add config complete timeout

[Moritz Fischer]

On Fri, Mar 10, 2017 at 11:40 AM,  <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> wrote:
> From: Alan Tull <atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>
> Adding timeout for maximum allowed time for FPGA to go to
> operating mode after a FPGA region has been programmed.
>
> Signed-off-by: Alan Tull <atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
Acked-by: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
>  drivers/fpga/fpga-region.c    | 3 +++
>  include/linux/fpga/fpga-mgr.h | 3 +++
>  2 files changed, 6 insertions(+)
>
> diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
> index 3222fdb..28401cb 100644
> --- a/drivers/fpga/fpga-region.c
> +++ b/drivers/fpga/fpga-region.c
> @@ -381,6 +381,9 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
>         of_property_read_u32(nd->overlay, "region-freeze-timeout-us",
>                              &info->disable_timeout_us);
>
> +       of_property_read_u32(nd->overlay, "config-complete-timeout-us",
> +                            &info->config_complete_timeout_us);
> +
>         /* If FPGA was externally programmed, don't specify firmware */
>         if ((info->flags & FPGA_MGR_EXTERNAL_CONFIG) && firmware_name) {
>                 pr_err("error: specified firmware and external-fpga-config");
> diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
> index 57beb5d..fd3f083 100644
> --- a/include/linux/fpga/fpga-mgr.h
> +++ b/include/linux/fpga/fpga-mgr.h
> @@ -76,11 +76,14 @@ enum fpga_mgr_states {
>   * @flags: boolean flags as defined above
>   * @enable_timeout_us: maximum time to enable traffic through bridge (uSec)
>   * @disable_timeout_us: maximum time to disable traffic through bridge (uSec)
> + * @config_complete_timeout_us: maximum time for FPGA to switch to operating
> + *        status in the write_complete op.
>   */
>  struct fpga_image_info {
>         u32 flags;
>         u32 enable_timeout_us;
>         u32 disable_timeout_us;
> +       u32 config_complete_timeout_us;
>  };
>
>  /**
> --
> 2.7.4
>
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Re: [PATCH v5 3/4] fpga dt: bindings for Altera Partial Reconfiguration IP.

[Moritz Fischer]

On Fri, Mar 10, 2017 at 11:40 AM,  <matthew.gerlach@linux.intel.com> wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
> Device Tree bindings for Altera Partial Reconfiguration IP.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> v5:
>     fix comment as suggested by Rob Herring <robh@kernel.org>
>     added Acked-by: Rob Herring <robh@kernel.org>
> v4: v3 patch set mistakenly sent out labeled as v4
> v3: s/altr,pr-ip/altr,a10-pr-ip/
> v2: s/Reconfiguraion/Reconfiguration/
> ---
>  Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
> new file mode 100644
> index 0000000..52a294c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
> @@ -0,0 +1,12 @@
> +Altera Arria10 Partial Reconfiguration IP
> +
> +Required properties:
> +- compatible : should contain "altr,a10-pr-ip"
> +- reg        : base address and size for memory mapped io.
> +
> +Example:
> +
> +       fpga_mgr: fpga-mgr@ff20c000 {
> +               compatible = "altr,a10-pr-ip";
> +               reg = <0xff20c000 0x10>;
> +       };
> --
> 2.7.4
>

Re: [PATCH v5 3/4] fpga dt: bindings for Altera Partial Reconfiguration IP.

[Moritz Fischer]

On Fri, Mar 10, 2017 at 11:40 AM,  <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> wrote:
> From: Matthew Gerlach <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
>
> Device Tree bindings for Altera Partial Reconfiguration IP.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Acked-by: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
> v5:
>     fix comment as suggested by Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>     added Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> v4: v3 patch set mistakenly sent out labeled as v4
> v3: s/altr,pr-ip/altr,a10-pr-ip/
> v2: s/Reconfiguraion/Reconfiguration/
> ---
>  Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
> new file mode 100644
> index 0000000..52a294c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
> @@ -0,0 +1,12 @@
> +Altera Arria10 Partial Reconfiguration IP
> +
> +Required properties:
> +- compatible : should contain "altr,a10-pr-ip"
> +- reg        : base address and size for memory mapped io.
> +
> +Example:
> +
> +       fpga_mgr: fpga-mgr@ff20c000 {
> +               compatible = "altr,a10-pr-ip";
> +               reg = <0xff20c000 0x10>;
> +       };
> --
> 2.7.4
>
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Re: [PATCH v5 4/4] fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.

[Moritz Fischer]

On Fri, Mar 10, 2017 at 11:40 AM,  <matthew.gerlach@linux.intel.com> wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
> This adds a platform bus driver for a fpga-mgr driver
> that uses the Altera Partial Reconfiguration IP component.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
> ---
> v5: fix comment as suggested by Rob Herring <robh@kernel.org>
> v4: v3 patch set mistakenly sent out labeled as v4
> v3:
>     s/altr,pr-ip/altr,a10-pr-ip/
>     s/alt_pr_probe/alt_pr_register/
>     s/alt_pr_remove/alt_pr_unregister/
>     fix error found by kbuild robot with more precise Kconfig depends
>
> v2: s/altr,pr-ip-core/altr,pr-ip/
> ---
>  drivers/fpga/Kconfig                  |  7 ++++
>  drivers/fpga/Makefile                 |  1 +
>  drivers/fpga/altera-pr-ip-core-plat.c | 65 +++++++++++++++++++++++++++++++++++
>  3 files changed, 73 insertions(+)
>  create mode 100644 drivers/fpga/altera-pr-ip-core-plat.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index a46c173..0c51427 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -68,6 +68,13 @@ config ALTERA_PR_IP_CORE
>          help
>            Core driver support for Altera Partial Reconfiguration IP component
>
> +config ALTERA_PR_IP_CORE_PLAT
> +       tristate "Platform support of Altera Partial Reconfiguration IP Core"
> +       depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
> +       help
> +         Platform driver support for Altera Partial Reconfiguration IP
> +         component
> +
>  endif # FPGA
>
>  endmenu
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 82693d2..5b8ae2b 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA)                += socfpga.o
>  obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)     += socfpga-a10.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
>  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> +obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
>
>  # FPGA Bridge Drivers
>  obj-$(CONFIG_FPGA_BRIDGE)              += fpga-bridge.o
> diff --git a/drivers/fpga/altera-pr-ip-core-plat.c b/drivers/fpga/altera-pr-ip-core-plat.c
> new file mode 100644
> index 0000000..cff189a
> --- /dev/null
> +++ b/drivers/fpga/altera-pr-ip-core-plat.c
> @@ -0,0 +1,65 @@
> +/*
> + * Driver for Altera Partial Reconfiguration IP Core
> + *
> + * Copyright (C) 2016-2017 Intel Corporation
> + *
> + * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
> + *  by Alan Tull <atull@opensource.altera.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "altera-pr-ip-core.h"
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +
> +static int alt_pr_platform_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       void __iomem *reg_base;
> +       struct resource *res;
> +
> +       /* First mmio base is for register access */
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> +       reg_base = devm_ioremap_resource(dev, res);
> +
> +       if (IS_ERR(reg_base))
> +               return PTR_ERR(reg_base);
> +
> +       return alt_pr_register(dev, reg_base);
> +}
> +
> +static int alt_pr_platform_remove(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +
> +       return alt_pr_unregister(dev);
> +}
> +
> +static const struct of_device_id alt_pr_of_match[] = {
> +       { .compatible = "altr,a10-pr-ip", },
> +       {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, alt_pr_of_match);
> +
> +static struct platform_driver alt_pr_platform_driver = {
> +       .probe = alt_pr_platform_probe,
> +       .remove = alt_pr_platform_remove,
> +       .driver = {
> +               .name   = "alt_a10_pr_ip",
> +               .of_match_table = alt_pr_of_match,
> +       },
> +};
> +
> +module_platform_driver(alt_pr_platform_driver);
> --
> 2.7.4
>

Thanks,
Moritz Fischer

Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[Moritz Fischer]

On Fri, Mar 10, 2017 at 11:40 AM,  <matthew.gerlach@linux.intel.com> wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
> Adding the core functions necessary for a fpga-mgr driver
> for the Altera Partial IP component.  It is intended for
> these functions to be used by the various bus implementations
> like the platform bus or the PCIe bus.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
> ---
> v5:
>     Fix comment as suggested by Rob Herring <robh@kernel.org>
> v4:
>     v3 patch set mistakenly sent out labeled as v4
> v3:
>     s/alt_pr_probe/alt_pr_register/
>     s/alt_pr_remove/alt_pr_unregister/
> ---
>  drivers/fpga/Kconfig             |   5 +
>  drivers/fpga/Makefile            |   1 +
>  drivers/fpga/altera-pr-ip-core.c | 217 +++++++++++++++++++++++++++++++++++++++
>  drivers/fpga/altera-pr-ip-core.h |  29 ++++++
>  4 files changed, 252 insertions(+)
>  create mode 100644 drivers/fpga/altera-pr-ip-core.c
>  create mode 100644 drivers/fpga/altera-pr-ip-core.h
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index ce861a2..a46c173 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -63,6 +63,11 @@ config ALTERA_FREEZE_BRIDGE
>           isolate one region of the FPGA from the busses while that
>           region is being reprogrammed.
>
> +config ALTERA_PR_IP_CORE
> +        tristate "Altera Partial Reconfiguration IP Core"
> +        help
> +          Core driver support for Altera Partial Reconfiguration IP component
> +
>  endif # FPGA
>
>  endmenu
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 8df07bc..82693d2 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -9,6 +9,7 @@ obj-$(CONFIG_FPGA)                      += fpga-mgr.o
>  obj-$(CONFIG_FPGA_MGR_SOCFPGA)         += socfpga.o
>  obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)     += socfpga-a10.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> +obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
>
>  # FPGA Bridge Drivers
>  obj-$(CONFIG_FPGA_BRIDGE)              += fpga-bridge.o
> diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera-pr-ip-core.c
> new file mode 100644
> index 0000000..738d7d1
> --- /dev/null
> +++ b/drivers/fpga/altera-pr-ip-core.c
> @@ -0,0 +1,217 @@
> +/*
> + * Driver for Altera Partial Reconfiguration IP Core
> + *
> + * Copyright (C) 2016-2017 Intel Corporation
> + *
> + * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
> + *  by Alan Tull <atull@opensource.altera.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "altera-pr-ip-core.h"
> +#include <linux/delay.h>
> +#include <linux/fpga/fpga-mgr.h>
> +#include <linux/module.h>
> +
> +#define ALT_PR_DATA_OFST               0x00
> +#define ALT_PR_CSR_OFST                        0x04
> +
> +#define ALT_PR_CSR_PR_START            BIT(0)
> +#define ALT_PR_CSR_STATUS_SFT          2
> +#define ALT_PR_CSR_STATUS_MSK          (7 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_NRESET       (0 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_PR_ERR       (1 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_CRC_ERR      (2 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_BAD_BITS     (3 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_PR_IN_PROG   (4 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_PR_SUCCESS   (5 << ALT_PR_CSR_STATUS_SFT)
> +
> +struct alt_pr_priv {
> +       void __iomem *reg_base;
> +};
> +
> +static enum fpga_mgr_states alt_pr_fpga_state(struct fpga_manager *mgr)
> +{
> +       struct alt_pr_priv *priv = mgr->priv;
> +       const char *err = "unknown";
> +       enum fpga_mgr_states ret = FPGA_MGR_STATE_UNKNOWN;
> +       u32 val;
> +
> +       val = readl(priv->reg_base + ALT_PR_CSR_OFST);
> +
> +       val &= ALT_PR_CSR_STATUS_MSK;
> +
> +       switch (val) {
> +       case ALT_PR_CSR_STATUS_NRESET:
> +               return FPGA_MGR_STATE_RESET;
> +
> +       case ALT_PR_CSR_STATUS_PR_ERR:
> +               err = "pr error";
> +               ret = FPGA_MGR_STATE_WRITE_ERR;
> +               break;
> +
> +       case ALT_PR_CSR_STATUS_CRC_ERR:
> +               err = "crc error";
> +               ret = FPGA_MGR_STATE_WRITE_ERR;
> +               break;
> +
> +       case ALT_PR_CSR_STATUS_BAD_BITS:
> +               err = "bad bits";
> +               ret = FPGA_MGR_STATE_WRITE_ERR;
> +               break;
> +
> +       case ALT_PR_CSR_STATUS_PR_IN_PROG:
> +               return FPGA_MGR_STATE_WRITE;
> +
> +       case ALT_PR_CSR_STATUS_PR_SUCCESS:
> +               return FPGA_MGR_STATE_OPERATING;
> +
> +       default:
> +               break;
> +       }
> +
> +       dev_err(&mgr->dev, "encountered error code %d (%s) in %s()\n",
> +               val, err, __func__);
> +       return ret;
> +}
> +
> +static int alt_pr_fpga_write_init(struct fpga_manager *mgr,
> +                                 struct fpga_image_info *info,
> +                                 const char *buf, size_t count)
> +{
> +       struct alt_pr_priv *priv = mgr->priv;
> +       u32 val;
> +
> +       if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
> +               pr_err("%s Partial Reconfiguration flag not set\n", __func__);
> +               return -EINVAL;
> +       }
> +
> +       val = readl(priv->reg_base + ALT_PR_CSR_OFST);
> +
> +       if (val & ALT_PR_CSR_PR_START) {
> +               pr_err("%s Partial Reconfiguration already started\n",
> +                      __func__);
> +               return -EINVAL;
> +       }
> +
> +       writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST);
> +
> +       return 0;
> +}
> +
> +static int alt_pr_fpga_write(struct fpga_manager *mgr, const char *buf,
> +                            size_t count)
> +{
> +       struct alt_pr_priv *priv = mgr->priv;
> +       u32 *buffer_32 = (u32 *)buf;
> +       size_t i = 0;
> +
> +       if (count <= 0)
> +               return -EINVAL;
> +
> +       /* Write out the complete 32-bit chunks */
> +       while (count >= sizeof(u32)) {
> +               writel(buffer_32[i++], priv->reg_base);
> +               count -= sizeof(u32);
> +       }
> +
> +       /* Write out remaining non 32-bit chunks */
> +       switch (count) {
> +       case 3:
> +               writel(buffer_32[i++] & 0x00ffffff, priv->reg_base);
> +               break;
> +       case 2:
> +               writel(buffer_32[i++] & 0x0000ffff, priv->reg_base);
> +               break;
> +       case 1:
> +               writel(buffer_32[i++] & 0x000000ff, priv->reg_base);
> +               break;
> +       case 0:
> +               break;
> +       default:
> +               /* This will never happen */
> +               return -EFAULT;
> +       }
> +
> +       if (alt_pr_fpga_state(mgr) == FPGA_MGR_STATE_WRITE_ERR)
> +               return -EIO;
> +
> +       return 0;
> +}
> +
> +static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
> +                                     struct fpga_image_info *info)
> +{
> +       u32 i;
> +
> +       for (i = 0; i < info->config_complete_timeout_us; i++) {
> +               switch (alt_pr_fpga_state(mgr)) {
> +               case FPGA_MGR_STATE_WRITE_ERR:
> +                       return -EIO;
> +
> +               case FPGA_MGR_STATE_OPERATING:
> +                       dev_info(&mgr->dev,
> +                                "successful partial reconfiguration\n");
> +                       return 0;
> +
> +               default:
> +                       break;
> +               }
> +               udelay(1);
> +       }
> +       dev_err(&mgr->dev, "timed out waiting for write to complete\n");
> +       return -ETIMEDOUT;
> +}
> +
> +static const struct fpga_manager_ops alt_pr_ops = {
> +       .state = alt_pr_fpga_state,
> +       .write_init = alt_pr_fpga_write_init,
> +       .write = alt_pr_fpga_write,
> +       .write_complete = alt_pr_fpga_write_complete,
> +};
> +
> +int alt_pr_register(struct device *dev, void __iomem *reg_base)
> +{
> +       struct alt_pr_priv *priv;
> +       u32 val;
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->reg_base = reg_base;
> +
> +       val = readl(priv->reg_base + ALT_PR_CSR_OFST);
> +
> +       dev_dbg(dev, "%s status=%d start=%d\n", __func__,
> +               (val & ALT_PR_CSR_STATUS_MSK) >> ALT_PR_CSR_STATUS_SFT,
> +               (int)(val & ALT_PR_CSR_PR_START));
> +
> +       return fpga_mgr_register(dev, dev_name(dev), &alt_pr_ops, priv);
> +}
> +EXPORT_SYMBOL_GPL(alt_pr_register);
> +
> +int alt_pr_unregister(struct device *dev)
> +{
> +       dev_dbg(dev, "%s\n", __func__);
> +
> +       fpga_mgr_unregister(dev);
> +
> +       return 0;
> +}
> +EXPORT_SYMBOL_GPL(alt_pr_unregister);
> +
> +MODULE_AUTHOR("Matthew Gerlach <matthew.gerlach@linux.intel.com>");
> +MODULE_DESCRIPTION("Altera Partial Reconfiguration IP Core");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/fpga/altera-pr-ip-core.h b/drivers/fpga/altera-pr-ip-core.h
> new file mode 100644
> index 0000000..3810a90
> --- /dev/null
> +++ b/drivers/fpga/altera-pr-ip-core.h
> @@ -0,0 +1,29 @@
> +/*
> + * Driver for Altera Partial Reconfiguration IP Core
> + *
> + * Copyright (C) 2016 Intel Corporation
> + *
> + * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
> + *  by Alan Tull <atull@opensource.altera.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef _ALT_PR_IP_CORE_H
> +#define _ALT_PR_IP_CORE_H
> +#include <linux/io.h>
> +
> +int alt_pr_register(struct device *dev, void __iomem *reg_base);
> +int alt_pr_unregister(struct device *dev);
> +
> +#endif /* _ALT_PR_IP_CORE_H */
> --
> 2.7.4
>

Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[Moritz Fischer]

On Fri, Mar 10, 2017 at 11:40 AM,  <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> wrote:
> From: Matthew Gerlach <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
>
> Adding the core functions necessary for a fpga-mgr driver
> for the Altera Partial IP component.  It is intended for
> these functions to be used by the various bus implementations
> like the platform bus or the PCIe bus.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Reviewed-by: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
> v5:
>     Fix comment as suggested by Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> v4:
>     v3 patch set mistakenly sent out labeled as v4
> v3:
>     s/alt_pr_probe/alt_pr_register/
>     s/alt_pr_remove/alt_pr_unregister/
> ---
>  drivers/fpga/Kconfig             |   5 +
>  drivers/fpga/Makefile            |   1 +
>  drivers/fpga/altera-pr-ip-core.c | 217 +++++++++++++++++++++++++++++++++++++++
>  drivers/fpga/altera-pr-ip-core.h |  29 ++++++
>  4 files changed, 252 insertions(+)
>  create mode 100644 drivers/fpga/altera-pr-ip-core.c
>  create mode 100644 drivers/fpga/altera-pr-ip-core.h
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index ce861a2..a46c173 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -63,6 +63,11 @@ config ALTERA_FREEZE_BRIDGE
>           isolate one region of the FPGA from the busses while that
>           region is being reprogrammed.
>
> +config ALTERA_PR_IP_CORE
> +        tristate "Altera Partial Reconfiguration IP Core"
> +        help
> +          Core driver support for Altera Partial Reconfiguration IP component
> +
>  endif # FPGA
>
>  endmenu
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 8df07bc..82693d2 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -9,6 +9,7 @@ obj-$(CONFIG_FPGA)                      += fpga-mgr.o
>  obj-$(CONFIG_FPGA_MGR_SOCFPGA)         += socfpga.o
>  obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)     += socfpga-a10.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> +obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
>
>  # FPGA Bridge Drivers
>  obj-$(CONFIG_FPGA_BRIDGE)              += fpga-bridge.o
> diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera-pr-ip-core.c
> new file mode 100644
> index 0000000..738d7d1
> --- /dev/null
> +++ b/drivers/fpga/altera-pr-ip-core.c
> @@ -0,0 +1,217 @@
> +/*
> + * Driver for Altera Partial Reconfiguration IP Core
> + *
> + * Copyright (C) 2016-2017 Intel Corporation
> + *
> + * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
> + *  by Alan Tull <atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "altera-pr-ip-core.h"
> +#include <linux/delay.h>
> +#include <linux/fpga/fpga-mgr.h>
> +#include <linux/module.h>
> +
> +#define ALT_PR_DATA_OFST               0x00
> +#define ALT_PR_CSR_OFST                        0x04
> +
> +#define ALT_PR_CSR_PR_START            BIT(0)
> +#define ALT_PR_CSR_STATUS_SFT          2
> +#define ALT_PR_CSR_STATUS_MSK          (7 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_NRESET       (0 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_PR_ERR       (1 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_CRC_ERR      (2 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_BAD_BITS     (3 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_PR_IN_PROG   (4 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_PR_SUCCESS   (5 << ALT_PR_CSR_STATUS_SFT)
> +
> +struct alt_pr_priv {
> +       void __iomem *reg_base;
> +};
> +
> +static enum fpga_mgr_states alt_pr_fpga_state(struct fpga_manager *mgr)
> +{
> +       struct alt_pr_priv *priv = mgr->priv;
> +       const char *err = "unknown";
> +       enum fpga_mgr_states ret = FPGA_MGR_STATE_UNKNOWN;
> +       u32 val;
> +
> +       val = readl(priv->reg_base + ALT_PR_CSR_OFST);
> +
> +       val &= ALT_PR_CSR_STATUS_MSK;
> +
> +       switch (val) {
> +       case ALT_PR_CSR_STATUS_NRESET:
> +               return FPGA_MGR_STATE_RESET;
> +
> +       case ALT_PR_CSR_STATUS_PR_ERR:
> +               err = "pr error";
> +               ret = FPGA_MGR_STATE_WRITE_ERR;
> +               break;
> +
> +       case ALT_PR_CSR_STATUS_CRC_ERR:
> +               err = "crc error";
> +               ret = FPGA_MGR_STATE_WRITE_ERR;
> +               break;
> +
> +       case ALT_PR_CSR_STATUS_BAD_BITS:
> +               err = "bad bits";
> +               ret = FPGA_MGR_STATE_WRITE_ERR;
> +               break;
> +
> +       case ALT_PR_CSR_STATUS_PR_IN_PROG:
> +               return FPGA_MGR_STATE_WRITE;
> +
> +       case ALT_PR_CSR_STATUS_PR_SUCCESS:
> +               return FPGA_MGR_STATE_OPERATING;
> +
> +       default:
> +               break;
> +       }
> +
> +       dev_err(&mgr->dev, "encountered error code %d (%s) in %s()\n",
> +               val, err, __func__);
> +       return ret;
> +}
> +
> +static int alt_pr_fpga_write_init(struct fpga_manager *mgr,
> +                                 struct fpga_image_info *info,
> +                                 const char *buf, size_t count)
> +{
> +       struct alt_pr_priv *priv = mgr->priv;
> +       u32 val;
> +
> +       if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
> +               pr_err("%s Partial Reconfiguration flag not set\n", __func__);
> +               return -EINVAL;
> +       }
> +
> +       val = readl(priv->reg_base + ALT_PR_CSR_OFST);
> +
> +       if (val & ALT_PR_CSR_PR_START) {
> +               pr_err("%s Partial Reconfiguration already started\n",
> +                      __func__);
> +               return -EINVAL;
> +       }
> +
> +       writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST);
> +
> +       return 0;
> +}
> +
> +static int alt_pr_fpga_write(struct fpga_manager *mgr, const char *buf,
> +                            size_t count)
> +{
> +       struct alt_pr_priv *priv = mgr->priv;
> +       u32 *buffer_32 = (u32 *)buf;
> +       size_t i = 0;
> +
> +       if (count <= 0)
> +               return -EINVAL;
> +
> +       /* Write out the complete 32-bit chunks */
> +       while (count >= sizeof(u32)) {
> +               writel(buffer_32[i++], priv->reg_base);
> +               count -= sizeof(u32);
> +       }
> +
> +       /* Write out remaining non 32-bit chunks */
> +       switch (count) {
> +       case 3:
> +               writel(buffer_32[i++] & 0x00ffffff, priv->reg_base);
> +               break;
> +       case 2:
> +               writel(buffer_32[i++] & 0x0000ffff, priv->reg_base);
> +               break;
> +       case 1:
> +               writel(buffer_32[i++] & 0x000000ff, priv->reg_base);
> +               break;
> +       case 0:
> +               break;
> +       default:
> +               /* This will never happen */
> +               return -EFAULT;
> +       }
> +
> +       if (alt_pr_fpga_state(mgr) == FPGA_MGR_STATE_WRITE_ERR)
> +               return -EIO;
> +
> +       return 0;
> +}
> +
> +static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
> +                                     struct fpga_image_info *info)
> +{
> +       u32 i;
> +
> +       for (i = 0; i < info->config_complete_timeout_us; i++) {
> +               switch (alt_pr_fpga_state(mgr)) {
> +               case FPGA_MGR_STATE_WRITE_ERR:
> +                       return -EIO;
> +
> +               case FPGA_MGR_STATE_OPERATING:
> +                       dev_info(&mgr->dev,
> +                                "successful partial reconfiguration\n");
> +                       return 0;
> +
> +               default:
> +                       break;
> +               }
> +               udelay(1);
> +       }
> +       dev_err(&mgr->dev, "timed out waiting for write to complete\n");
> +       return -ETIMEDOUT;
> +}
> +
> +static const struct fpga_manager_ops alt_pr_ops = {
> +       .state = alt_pr_fpga_state,
> +       .write_init = alt_pr_fpga_write_init,
> +       .write = alt_pr_fpga_write,
> +       .write_complete = alt_pr_fpga_write_complete,
> +};
> +
> +int alt_pr_register(struct device *dev, void __iomem *reg_base)
> +{
> +       struct alt_pr_priv *priv;
> +       u32 val;
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->reg_base = reg_base;
> +
> +       val = readl(priv->reg_base + ALT_PR_CSR_OFST);
> +
> +       dev_dbg(dev, "%s status=%d start=%d\n", __func__,
> +               (val & ALT_PR_CSR_STATUS_MSK) >> ALT_PR_CSR_STATUS_SFT,
> +               (int)(val & ALT_PR_CSR_PR_START));
> +
> +       return fpga_mgr_register(dev, dev_name(dev), &alt_pr_ops, priv);
> +}
> +EXPORT_SYMBOL_GPL(alt_pr_register);
> +
> +int alt_pr_unregister(struct device *dev)
> +{
> +       dev_dbg(dev, "%s\n", __func__);
> +
> +       fpga_mgr_unregister(dev);
> +
> +       return 0;
> +}
> +EXPORT_SYMBOL_GPL(alt_pr_unregister);
> +
> +MODULE_AUTHOR("Matthew Gerlach <matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>");
> +MODULE_DESCRIPTION("Altera Partial Reconfiguration IP Core");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/fpga/altera-pr-ip-core.h b/drivers/fpga/altera-pr-ip-core.h
> new file mode 100644
> index 0000000..3810a90
> --- /dev/null
> +++ b/drivers/fpga/altera-pr-ip-core.h
> @@ -0,0 +1,29 @@
> +/*
> + * Driver for Altera Partial Reconfiguration IP Core
> + *
> + * Copyright (C) 2016 Intel Corporation
> + *
> + * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
> + *  by Alan Tull <atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef _ALT_PR_IP_CORE_H
> +#define _ALT_PR_IP_CORE_H
> +#include <linux/io.h>
> +
> +int alt_pr_register(struct device *dev, void __iomem *reg_base);
> +int alt_pr_unregister(struct device *dev);
> +
> +#endif /* _ALT_PR_IP_CORE_H */
> --
> 2.7.4
>
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Re: [PATCH v5 4/4] fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.

[Anatolij Gustschin]

Hi Matthew,

On Fri, 10 Mar 2017 11:40:27 -0800
matthew.gerlach@linux.intel.com matthew.gerlach@linux.intel.com wrote:

...
>+#include "altera-pr-ip-core.h"

Shouldn't we put this header to include/linux? Compiling the
out-of-tree modules using alt_pr_register/alt_pr_unregister
will not work if this header is in drivers/fpga.

...
>+
>+module_platform_driver(alt_pr_platform_driver);

Please add MODULE_LICENSE("GPL v2") here. Otherwise, when built as
a module it cannot be loaded because the alt_pr register/unregister
functions are exported as GPL only. Also please add module author
and description.

Thanks,

Anatolij

Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[Anatolij Gustschin]

Hi Matthew,

thanks for the patches. Please see some comments below.

On Fri, 10 Mar 2017 11:40:25 -0800
matthew.gerlach@linux.intel.com matthew.gerlach@linux.intel.com wrote:

...
>+	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
>+		pr_err("%s Partial Reconfiguration flag not set\n", __func__);

please use dev_err() here.

...
>+	if (val & ALT_PR_CSR_PR_START) {
>+		pr_err("%s Partial Reconfiguration already started\n",

dev_err(), too.

...
>+static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
>+				      struct fpga_image_info *info)
>+{
>+	u32 i;
>+
>+	for (i = 0; i < info->config_complete_timeout_us; i++) {
>+		switch (alt_pr_fpga_state(mgr)) {
>+		case FPGA_MGR_STATE_WRITE_ERR:
>+			return -EIO;
>+
>+		case FPGA_MGR_STATE_OPERATING:
>+			dev_info(&mgr->dev,
>+				 "successful partial reconfiguration\n");
>+			return 0;
>+
>+		default:
>+			break;
>+		}
>+		udelay(1);
>+	}
>+	dev_err(&mgr->dev, "timed out waiting for write to complete\n");
>+	return -ETIMEDOUT;
>+}

we will always get timed out error if info->config_complete_timeout_us
is zero. Can we change to
	u32 i = 0;
	...
	do {
		...
	} while (info->config_complete_timeout_us > i++);
?

...
>diff --git a/drivers/fpga/altera-pr-ip-core.h b/drivers/fpga/altera-pr-ip-core.h
>new file mode 100644
>index 0000000..3810a90
>--- /dev/null
>+++ b/drivers/fpga/altera-pr-ip-core.h

Should we move this header to include/linux/? We can use register/
unregister functions in other drivers (PCIe) outside drivers/fpga
then.

Thanks,

Anatolij

Re: [PATCH v5 4/4] fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.

[matthew.gerlach]

On Sat, 18 Mar 2017, Anatolij Gustschin wrote:

> Hi Matthew,
>

Hi Anatolij,

Thanks for all the feedback.  I will create another patch set 
incorporating your suggestions.


> On Fri, 10 Mar 2017 11:40:27 -0800
> matthew.gerlach@linux.intel.com matthew.gerlach@linux.intel.com wrote:
>
> ...
>> +#include "altera-pr-ip-core.h"
>
> Shouldn't we put this header to include/linux? Compiling the
> out-of-tree modules using alt_pr_register/alt_pr_unregister
> will not work if this header is in drivers/fpga.

I was not sure if someone would want to access these functions outside of 
drivers/fpga.  I think it does make sense to move it to 
include/linux/fpga.

>
> ...
>> +
>> +module_platform_driver(alt_pr_platform_driver);
>
> Please add MODULE_LICENSE("GPL v2") here. Otherwise, when built as
> a module it cannot be loaded because the alt_pr register/unregister
> functions are exported as GPL only. Also please add module author
> and description.
>

Got it. Thanks!

> Thanks,
>
> Anatolij
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>

Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[matthew.gerlach]

On Sat, 18 Mar 2017, Anatolij Gustschin wrote:

> Hi Matthew,
>

Hi Anatolij,

More good feedback.  See below.


> thanks for the patches. Please see some comments below.
>
> On Fri, 10 Mar 2017 11:40:25 -0800
> matthew.gerlach@linux.intel.com matthew.gerlach@linux.intel.com wrote:
>
> ...
>> +	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
>> +		pr_err("%s Partial Reconfiguration flag not set\n", __func__);
>
> please use dev_err() here.
>
> ...
>> +	if (val & ALT_PR_CSR_PR_START) {
>> +		pr_err("%s Partial Reconfiguration already started\n",
>
> dev_err(), too.

Good catch on both of these pr_err().  dev_err() would be better.
>
> ...
>> +static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
>> +				      struct fpga_image_info *info)
>> +{
>> +	u32 i;
>> +
>> +	for (i = 0; i < info->config_complete_timeout_us; i++) {
>> +		switch (alt_pr_fpga_state(mgr)) {
>> +		case FPGA_MGR_STATE_WRITE_ERR:
>> +			return -EIO;
>> +
>> +		case FPGA_MGR_STATE_OPERATING:
>> +			dev_info(&mgr->dev,
>> +				 "successful partial reconfiguration\n");
>> +			return 0;
>> +
>> +		default:
>> +			break;
>> +		}
>> +		udelay(1);
>> +	}
>> +	dev_err(&mgr->dev, "timed out waiting for write to complete\n");
>> +	return -ETIMEDOUT;
>> +}
>
> we will always get timed out error if info->config_complete_timeout_us
> is zero. Can we change to
> 	u32 i = 0;
> 	...
> 	do {
> 		...
> 	} while (info->config_complete_timeout_us > i++);
> ?

This seems more than reasonable to me.

>
> ...
>> diff --git a/drivers/fpga/altera-pr-ip-core.h b/drivers/fpga/altera-pr-ip-core.h
>> new file mode 100644
>> index 0000000..3810a90
>> --- /dev/null
>> +++ b/drivers/fpga/altera-pr-ip-core.h
>
> Should we move this header to include/linux/? We can use register/
> unregister functions in other drivers (PCIe) outside drivers/fpga
> then.
>
> Thanks,
>
> Anatolij
>

Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[matthew.gerlach-VuQAYsv1563Yd54FQh9/CA]

On Sat, 18 Mar 2017, Anatolij Gustschin wrote:

> Hi Matthew,
>

Hi Anatolij,

More good feedback.  See below.


> thanks for the patches. Please see some comments below.
>
> On Fri, 10 Mar 2017 11:40:25 -0800
> matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org wrote:
>
> ...
>> +	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
>> +		pr_err("%s Partial Reconfiguration flag not set\n", __func__);
>
> please use dev_err() here.
>
> ...
>> +	if (val & ALT_PR_CSR_PR_START) {
>> +		pr_err("%s Partial Reconfiguration already started\n",
>
> dev_err(), too.

Good catch on both of these pr_err().  dev_err() would be better.
>
> ...
>> +static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
>> +				      struct fpga_image_info *info)
>> +{
>> +	u32 i;
>> +
>> +	for (i = 0; i < info->config_complete_timeout_us; i++) {
>> +		switch (alt_pr_fpga_state(mgr)) {
>> +		case FPGA_MGR_STATE_WRITE_ERR:
>> +			return -EIO;
>> +
>> +		case FPGA_MGR_STATE_OPERATING:
>> +			dev_info(&mgr->dev,
>> +				 "successful partial reconfiguration\n");
>> +			return 0;
>> +
>> +		default:
>> +			break;
>> +		}
>> +		udelay(1);
>> +	}
>> +	dev_err(&mgr->dev, "timed out waiting for write to complete\n");
>> +	return -ETIMEDOUT;
>> +}
>
> we will always get timed out error if info->config_complete_timeout_us
> is zero. Can we change to
> 	u32 i = 0;
> 	...
> 	do {
> 		...
> 	} while (info->config_complete_timeout_us > i++);
> ?

This seems more than reasonable to me.

>
> ...
>> diff --git a/drivers/fpga/altera-pr-ip-core.h b/drivers/fpga/altera-pr-ip-core.h
>> new file mode 100644
>> index 0000000..3810a90
>> --- /dev/null
>> +++ b/drivers/fpga/altera-pr-ip-core.h
>
> Should we move this header to include/linux/? We can use register/
> unregister functions in other drivers (PCIe) outside drivers/fpga
> then.
>
> Thanks,
>
> Anatolij
>
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Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[Anatolij Gustschin]

Hi Matthew,

On Fri, 10 Mar 2017 11:40:25 -0800
matthew.gerlach@linux.intel.com matthew.gerlach@linux.intel.com wrote:
...
>+int alt_pr_unregister(struct device *dev)
>+{
>+	dev_dbg(dev, "%s\n", __func__);
>+
>+	fpga_mgr_unregister(dev);
>+
>+	return 0;
>+}
>+EXPORT_SYMBOL_GPL(alt_pr_unregister);

Can we also add a function for registering a PCIe device with
PR IP here? Something like:

/**
 * alt_pr_pcie_register - register PCIe device with PR-IP core
 * @pci_dev:    PCI device with PR-IP
 * @bar:        PR-IP BAR number
 * @pr_offset:  offset of the PR-IP core registers
 *
 * Return: 0 on success, negative error code otherwise.
 *
 * To unregister the PCIe device, use alt_pr_unregister(&pdev->dev).
 */
int alt_pr_pcie_register(struct pci_dev *pdev, int bar, int pr_offset)
{
        void __iomem *base;
        int ret;

        if (!pci_is_enabled(pdev)) {
                ret = pci_enable_device(pdev);
                if (ret < 0) {
                        dev_err(&pdev->dev, "can't enable device: %d\n", ret);
                        return ret;
                }
        }

        base = devm_ioremap_resource(&pdev->dev, &pdev->resource[bar]);
        if (IS_ERR(base)) {
                dev_warn(&pdev->dev, "mapping PR-IP BAR failed\n");
                return -ENOMEM;
        }

        return alt_pr_register(&pdev->dev, base + pr_offset);
}
EXPORT_SYMBOL_GPL(alt_pr_pcie_register);

Thanks,
Anatolij

Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[Anatolij Gustschin]

Hi Matthew,

On Fri, 10 Mar 2017 11:40:25 -0800
matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org wrote:
...
>+int alt_pr_unregister(struct device *dev)
>+{
>+	dev_dbg(dev, "%s\n", __func__);
>+
>+	fpga_mgr_unregister(dev);
>+
>+	return 0;
>+}
>+EXPORT_SYMBOL_GPL(alt_pr_unregister);

Can we also add a function for registering a PCIe device with
PR IP here? Something like:

/**
 * alt_pr_pcie_register - register PCIe device with PR-IP core
 * @pci_dev:    PCI device with PR-IP
 * @bar:        PR-IP BAR number
 * @pr_offset:  offset of the PR-IP core registers
 *
 * Return: 0 on success, negative error code otherwise.
 *
 * To unregister the PCIe device, use alt_pr_unregister(&pdev->dev).
 */
int alt_pr_pcie_register(struct pci_dev *pdev, int bar, int pr_offset)
{
        void __iomem *base;
        int ret;

        if (!pci_is_enabled(pdev)) {
                ret = pci_enable_device(pdev);
                if (ret < 0) {
                        dev_err(&pdev->dev, "can't enable device: %d\n", ret);
                        return ret;
                }
        }

        base = devm_ioremap_resource(&pdev->dev, &pdev->resource[bar]);
        if (IS_ERR(base)) {
                dev_warn(&pdev->dev, "mapping PR-IP BAR failed\n");
                return -ENOMEM;
        }

        return alt_pr_register(&pdev->dev, base + pr_offset);
}
EXPORT_SYMBOL_GPL(alt_pr_pcie_register);

Thanks,
Anatolij
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Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[matthew.gerlach]

On Tue, 21 Mar 2017, Anatolij Gustschin wrote:

> Hi Matthew,

Hi Anatolij,

>
> On Fri, 10 Mar 2017 11:40:25 -0800
> matthew.gerlach@linux.intel.com matthew.gerlach@linux.intel.com wrote:
> ...
>> +int alt_pr_unregister(struct device *dev)
>> +{
>> +	dev_dbg(dev, "%s\n", __func__);
>> +
>> +	fpga_mgr_unregister(dev);
>> +
>> +	return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(alt_pr_unregister);
>
> Can we also add a function for registering a PCIe device with
> PR IP here? Something like:

If we have an alt_pr_pcie_register function, we will need the 
corresponding alt_pr_pcie_unregister function.  Both of these functions 
should go into their own file like alt_pr_platform_probe() and 
alt_pr_platform_remove().

>
> /**
> * alt_pr_pcie_register - register PCIe device with PR-IP core
> * @pci_dev:    PCI device with PR-IP
> * @bar:        PR-IP BAR number
> * @pr_offset:  offset of the PR-IP core registers
> *
> * Return: 0 on success, negative error code otherwise.
> *
> * To unregister the PCIe device, use alt_pr_unregister(&pdev->dev).
> */
> int alt_pr_pcie_register(struct pci_dev *pdev, int bar, int pr_offset)
> {
>        void __iomem *base;
>        int ret;
>
>        if (!pci_is_enabled(pdev)) {
>                ret = pci_enable_device(pdev);
>                if (ret < 0) {
>                        dev_err(&pdev->dev, "can't enable device: %d\n", ret);
>                        return ret;
>                }
>        }
>
>        base = devm_ioremap_resource(&pdev->dev, &pdev->resource[bar]);

Does this remap the whole bar?  If it does, what happens if other 
components are also connected to the bar?  How do those corresponding 
drivers get access to the mapped memory?


>        if (IS_ERR(base)) {
>                dev_warn(&pdev->dev, "mapping PR-IP BAR failed\n");
>                return -ENOMEM;
>        }
>
>        return alt_pr_register(&pdev->dev, base + pr_offset);
> }
> EXPORT_SYMBOL_GPL(alt_pr_pcie_register);
>
> Thanks,
> Anatolij
> --
> To unsubscribe from this list: send the line "unsubscribe linux-fpga" in
> the body of a message to majordomo@vger.kernel.org
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>

Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[matthew.gerlach-VuQAYsv1563Yd54FQh9/CA]

On Tue, 21 Mar 2017, Anatolij Gustschin wrote:

> Hi Matthew,

Hi Anatolij,

>
> On Fri, 10 Mar 2017 11:40:25 -0800
> matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org wrote:
> ...
>> +int alt_pr_unregister(struct device *dev)
>> +{
>> +	dev_dbg(dev, "%s\n", __func__);
>> +
>> +	fpga_mgr_unregister(dev);
>> +
>> +	return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(alt_pr_unregister);
>
> Can we also add a function for registering a PCIe device with
> PR IP here? Something like:

If we have an alt_pr_pcie_register function, we will need the 
corresponding alt_pr_pcie_unregister function.  Both of these functions 
should go into their own file like alt_pr_platform_probe() and 
alt_pr_platform_remove().

>
> /**
> * alt_pr_pcie_register - register PCIe device with PR-IP core
> * @pci_dev:    PCI device with PR-IP
> * @bar:        PR-IP BAR number
> * @pr_offset:  offset of the PR-IP core registers
> *
> * Return: 0 on success, negative error code otherwise.
> *
> * To unregister the PCIe device, use alt_pr_unregister(&pdev->dev).
> */
> int alt_pr_pcie_register(struct pci_dev *pdev, int bar, int pr_offset)
> {
>        void __iomem *base;
>        int ret;
>
>        if (!pci_is_enabled(pdev)) {
>                ret = pci_enable_device(pdev);
>                if (ret < 0) {
>                        dev_err(&pdev->dev, "can't enable device: %d\n", ret);
>                        return ret;
>                }
>        }
>
>        base = devm_ioremap_resource(&pdev->dev, &pdev->resource[bar]);

Does this remap the whole bar?  If it does, what happens if other 
components are also connected to the bar?  How do those corresponding 
drivers get access to the mapped memory?


>        if (IS_ERR(base)) {
>                dev_warn(&pdev->dev, "mapping PR-IP BAR failed\n");
>                return -ENOMEM;
>        }
>
>        return alt_pr_register(&pdev->dev, base + pr_offset);
> }
> EXPORT_SYMBOL_GPL(alt_pr_pcie_register);
>
> Thanks,
> Anatolij
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Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[Anatolij Gustschin]

Hi Matthew,

On Wed, 22 Mar 2017 09:08:18 -0700 (PDT)
matthew.gerlach@linux.intel.com matthew.gerlach@linux.intel.com wrote:
...
>> Can we also add a function for registering a PCIe device with
>> PR IP here? Something like:  
>
>If we have an alt_pr_pcie_register function, we will need the 
>corresponding alt_pr_pcie_unregister function.  Both of these functions 
>should go into their own file like alt_pr_platform_probe() and 
>alt_pr_platform_remove().

Okay, thanks.

>> /**
>> * alt_pr_pcie_register - register PCIe device with PR-IP core
>> * @pci_dev:    PCI device with PR-IP
>> * @bar:        PR-IP BAR number
>> * @pr_offset:  offset of the PR-IP core registers
>> *
>> * Return: 0 on success, negative error code otherwise.
>> *
>> * To unregister the PCIe device, use alt_pr_unregister(&pdev->dev).
>> */
>> int alt_pr_pcie_register(struct pci_dev *pdev, int bar, int pr_offset)
>> {
>>        void __iomem *base;
>>        int ret;
>>
>>        if (!pci_is_enabled(pdev)) {
>>                ret = pci_enable_device(pdev);
>>                if (ret < 0) {
>>                        dev_err(&pdev->dev, "can't enable device: %d\n", ret);
>>                        return ret;
>>                }
>>        }
>>
>>        base = devm_ioremap_resource(&pdev->dev, &pdev->resource[bar]);  
>
>Does this remap the whole bar?  If it does, what happens if other 
>components are also connected to the bar?  How do those corresponding 
>drivers get access to the mapped memory?

yes, it remaps the whole bar. I do not know the details of the PR IP,
my assumption was that PR IP it is only one component in the bar.
Then I could use devm_ioremap() instead. Thanks for the hint!

Anatolij