From: Stafford Horne <shorne@gmail.com> To: Richard Henderson <rth@twiddle.net> Cc: QEMU Development <qemu-devel@nongnu.org>, Openrisc <openrisc@lists.librecores.org> Subject: Re: [Qemu-devel] [PATCH RFC] target/openrisc: Support non-busy idle state using PMR SPR Date: Tue, 25 Apr 2017 23:18:27 +0900 [thread overview] Message-ID: <20170425141827.GA2724@lianli.shorne-pla.net> (raw) In-Reply-To: <f6a7d386-80a9-0cc3-e1ec-1b2058aa5bf9@twiddle.net> On Tue, Apr 25, 2017 at 12:11:00PM +0200, Richard Henderson wrote: > On 04/23/2017 11:54 PM, Stafford Horne wrote: > > The OpenRISC architecture has the Power Management Register (PMR) > > special purpose register to manage cpu power states. The interesting > > modes are: > > > > * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt > > * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt > > * Suspend Model (SUME) - Stop cpu and all units - wake on reset > > > > The linux kernel will set DME when idle. > > And SUME would be, essentially, poweroff? Perhaps at least for the purposes > of QEMU; on real hardware one could press a button to assert reset and > reboot. Yes, that is what I am thinking, but I could add this later, after some reviews with other OpenRISC folks. > > Also, I don't know if its due to this patch of an issue with the timer > > interrupts. After applying this patch the timer interrupts do not trigger > > until a keypress is make. i.e. something like this... > > > > $ sleep 5 > > <hangs forever until a key is pressed> > ... > > + cpu_restore_state(cs, GETPC() + 4); > > This isn't correct. You want > > cpu_restore_state(cs, GETPC()); > cs->env.pc += 4; > > So what's happening is that you're re-executing the MTSPR and going back to > sleep again. Which probably explains the hang. I have changed to the above, but I think its essentially the same. It resumes after the MTSPR in both cases. I fixed this now though, you should see another patch. The issue is the timer events get ignored once the cpu is in halt state, I added a qemu_cpu_kick() call in the timer hardware to wake up the cpu on timer interrupts. Not sure if thats the best way to do it, but it works 100% now. -Stafford
WARNING: multiple messages have this Message-ID (diff)
From: Stafford Horne <shorne@gmail.com> To: openrisc@lists.librecores.org Subject: [OpenRISC] [PATCH RFC] target/openrisc: Support non-busy idle state using PMR SPR Date: Tue, 25 Apr 2017 23:18:27 +0900 [thread overview] Message-ID: <20170425141827.GA2724@lianli.shorne-pla.net> (raw) In-Reply-To: <f6a7d386-80a9-0cc3-e1ec-1b2058aa5bf9@twiddle.net> On Tue, Apr 25, 2017 at 12:11:00PM +0200, Richard Henderson wrote: > On 04/23/2017 11:54 PM, Stafford Horne wrote: > > The OpenRISC architecture has the Power Management Register (PMR) > > special purpose register to manage cpu power states. The interesting > > modes are: > > > > * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt > > * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt > > * Suspend Model (SUME) - Stop cpu and all units - wake on reset > > > > The linux kernel will set DME when idle. > > And SUME would be, essentially, poweroff? Perhaps at least for the purposes > of QEMU; on real hardware one could press a button to assert reset and > reboot. Yes, that is what I am thinking, but I could add this later, after some reviews with other OpenRISC folks. > > Also, I don't know if its due to this patch of an issue with the timer > > interrupts. After applying this patch the timer interrupts do not trigger > > until a keypress is make. i.e. something like this... > > > > $ sleep 5 > > <hangs forever until a key is pressed> > ... > > + cpu_restore_state(cs, GETPC() + 4); > > This isn't correct. You want > > cpu_restore_state(cs, GETPC()); > cs->env.pc += 4; > > So what's happening is that you're re-executing the MTSPR and going back to > sleep again. Which probably explains the hang. I have changed to the above, but I think its essentially the same. It resumes after the MTSPR in both cases. I fixed this now though, you should see another patch. The issue is the timer events get ignored once the cpu is in halt state, I added a qemu_cpu_kick() call in the timer hardware to wake up the cpu on timer interrupts. Not sure if thats the best way to do it, but it works 100% now. -Stafford
next prev parent reply other threads:[~2017-04-25 14:18 UTC|newest] Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-04-16 23:23 [Qemu-devel] [PATCH 0/7] Openrisc misc features / fixes Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-16 23:23 ` [Qemu-devel] [PATCH 1/7] target/openrisc: Fixes for memory debugging Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-18 7:47 ` [Qemu-devel] " Richard Henderson 2017-04-18 7:47 ` [OpenRISC] " Richard Henderson 2017-04-18 14:18 ` Stafford Horne 2017-04-18 14:18 ` [OpenRISC] " Stafford Horne 2017-04-18 15:00 ` Richard Henderson 2017-04-18 15:00 ` [OpenRISC] " Richard Henderson 2017-04-19 20:06 ` Stafford Horne 2017-04-19 20:06 ` [OpenRISC] " Stafford Horne 2017-04-16 23:23 ` [Qemu-devel] [PATCH 2/7] target/openrisc: add shutdown logic Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-18 7:52 ` [Qemu-devel] " Richard Henderson 2017-04-18 7:52 ` [OpenRISC] " Richard Henderson 2017-04-18 14:20 ` Stafford Horne 2017-04-18 14:20 ` [OpenRISC] " Stafford Horne 2017-04-22 10:09 ` Stafford Horne 2017-04-22 10:09 ` [OpenRISC] " Stafford Horne 2017-04-22 15:25 ` Richard Henderson 2017-04-22 15:25 ` [OpenRISC] " Richard Henderson 2017-04-23 21:28 ` [OpenRISC] [PATCH PMR] target/openrisc: Support non-busy idle state using PMR SPR Stafford Horne 2017-04-23 21:54 ` [Qemu-devel] [PATCH RFC] " Stafford Horne 2017-04-23 21:54 ` [OpenRISC] " Stafford Horne 2017-04-25 10:11 ` [Qemu-devel] " Richard Henderson 2017-04-25 10:11 ` [OpenRISC] " Richard Henderson 2017-04-25 14:10 ` [Qemu-devel] [PATCH RFC v2] " Stafford Horne 2017-04-25 14:10 ` [OpenRISC] " Stafford Horne 2017-04-25 14:18 ` Stafford Horne [this message] 2017-04-25 14:18 ` [OpenRISC] [PATCH RFC] " Stafford Horne 2017-04-25 14:51 ` [Qemu-devel] " Richard Henderson 2017-04-25 14:51 ` [OpenRISC] " Richard Henderson 2022-04-27 17:44 ` [Qemu-devel] [PATCH 2/7] target/openrisc: add shutdown logic Jason A. Donenfeld 2022-04-27 17:44 ` [OpenRISC] " Jason A. Donenfeld 2022-04-27 18:47 ` Peter Maydell 2022-04-27 18:47 ` [OpenRISC] " Peter Maydell 2022-04-27 21:48 ` Stafford Horne 2022-04-27 21:48 ` [OpenRISC] " Stafford Horne 2022-04-28 0:04 ` Jason A. Donenfeld 2022-04-28 0:04 ` [OpenRISC] " Jason A. Donenfeld 2022-04-28 11:16 ` Jason A. Donenfeld 2022-04-28 11:16 ` [OpenRISC] " Jason A. Donenfeld 2022-04-28 11:47 ` Stafford Horne 2022-04-28 11:47 ` [OpenRISC] " Stafford Horne 2022-04-28 9:19 ` Peter Maydell 2022-04-28 9:19 ` [OpenRISC] " Peter Maydell 2017-04-16 23:23 ` [Qemu-devel] [PATCH 3/7] target/openrisc: add numcores and coreid support Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-18 8:01 ` [Qemu-devel] " Richard Henderson 2017-04-18 8:01 ` [OpenRISC] " Richard Henderson 2017-04-16 23:23 ` [Qemu-devel] [PATCH 4/7] target/openrisc: implement shadow registers Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-18 8:11 ` [Qemu-devel] " Richard Henderson 2017-04-18 8:11 ` [OpenRISC] " Richard Henderson 2017-04-18 14:26 ` Stafford Horne 2017-04-18 14:26 ` [OpenRISC] " Stafford Horne 2017-04-16 23:23 ` [Qemu-devel] [PATCH 5/7] migration: Add VMSTATE_UINTTL_2DARRAY() Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-16 23:23 ` [Qemu-devel] [PATCH 6/7] migration: Add VMSTATE_STRUCT_2DARRAY() Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-16 23:23 ` [Qemu-devel] [PATCH 7/7] target/openrisc: Implement full vmstate serialization Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-18 8:14 ` [Qemu-devel] " Richard Henderson 2017-04-18 8:14 ` [OpenRISC] " Richard Henderson 2017-04-18 14:27 ` Stafford Horne 2017-04-18 14:27 ` [OpenRISC] " Stafford Horne 2017-04-16 23:33 ` [Qemu-devel] [PATCH 0/7] Openrisc misc features / fixes no-reply 2017-04-16 23:33 ` [OpenRISC] " no-reply
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