From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Michel Dänzer" <michel@daenzer.net>
Cc: Daniel Vetter <daniel.vetter@intel.com>,
dri-devel@lists.freedesktop.org,
Gerd Hoffmann <kraxel@redhat.com>,
amd-gfx@lists.freedesktop.org,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/6] drm: fourcc byteorder: add bigendian support to drm_mode_legacy_fb_format
Date: Wed, 26 Apr 2017 17:30:40 +0300 [thread overview]
Message-ID: <20170426143040.GW30290@intel.com> (raw)
In-Reply-To: <b306654e-ae14-99f5-d129-8fc1fb8cc05d@daenzer.net>
On Wed, Apr 26, 2017 at 11:00:09AM +0900, Michel Dänzer wrote:
> On 25/04/17 06:52 PM, Ville Syrjälä wrote:
> > On Tue, Apr 25, 2017 at 12:18:52PM +0900, Michel Dänzer wrote:
> >> On 24/04/17 03:25 PM, Gerd Hoffmann wrote:
> >>> +#ifdef __BIG_ENDIAN
> >>> + switch (bpp) {
> >>> + case 8:
> >>> + fmt = DRM_FORMAT_C8;
> >>> + break;
> >>> + case 24:
> >>> + fmt = DRM_FORMAT_BGR888;
> >>> + break;
> >>
> >> BTW, endianness as a concept cannot apply to 8 or 24 bpp formats.
> >
> > To 8bpp no, but it can easily apply to 24bpp.
>
> Any byte swapping rips apart the bytes of a 24bpp pixel, so those
> formats only make sense as straight array formats.
In my book little endian just means "lsb is stored in the lowest
memory address". The fact that your CPU/GPU can't do 3 byte swaps
is not relevant for that definition IMO.
--
Ville Syrjälä
Intel OTC
WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
To: "Michel Dänzer" <michel-otUistvHUpPR7s880joybQ@public.gmane.org>
Cc: Daniel Vetter
<daniel.vetter-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Gerd Hoffmann <kraxel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
open list <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: Re: [PATCH 3/6] drm: fourcc byteorder: add bigendian support to drm_mode_legacy_fb_format
Date: Wed, 26 Apr 2017 17:30:40 +0300 [thread overview]
Message-ID: <20170426143040.GW30290@intel.com> (raw)
In-Reply-To: <b306654e-ae14-99f5-d129-8fc1fb8cc05d-otUistvHUpPR7s880joybQ@public.gmane.org>
On Wed, Apr 26, 2017 at 11:00:09AM +0900, Michel Dänzer wrote:
> On 25/04/17 06:52 PM, Ville Syrjälä wrote:
> > On Tue, Apr 25, 2017 at 12:18:52PM +0900, Michel Dänzer wrote:
> >> On 24/04/17 03:25 PM, Gerd Hoffmann wrote:
> >>> +#ifdef __BIG_ENDIAN
> >>> + switch (bpp) {
> >>> + case 8:
> >>> + fmt = DRM_FORMAT_C8;
> >>> + break;
> >>> + case 24:
> >>> + fmt = DRM_FORMAT_BGR888;
> >>> + break;
> >>
> >> BTW, endianness as a concept cannot apply to 8 or 24 bpp formats.
> >
> > To 8bpp no, but it can easily apply to 24bpp.
>
> Any byte swapping rips apart the bytes of a 24bpp pixel, so those
> formats only make sense as straight array formats.
In my book little endian just means "lsb is stored in the lowest
memory address". The fact that your CPU/GPU can't do 3 byte swaps
is not relevant for that definition IMO.
--
Ville Syrjälä
Intel OTC
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
next prev parent reply other threads:[~2017-04-26 14:30 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-24 6:25 [PATCH 0/6] drm: tackle byteorder issues, take two Gerd Hoffmann
2017-04-24 6:25 ` [PATCH 1/6] drm: fourcc byteorder: drop DRM_FORMAT_BIG_ENDIAN Gerd Hoffmann
2017-04-24 6:25 ` Gerd Hoffmann
2017-04-24 6:25 ` [PATCH 2/6] drm: fourcc byteorder: add DRM_FORMAT_CPU_* Gerd Hoffmann
2017-04-24 6:25 ` Gerd Hoffmann
2017-04-24 6:25 ` [PATCH 3/6] drm: fourcc byteorder: add bigendian support to drm_mode_legacy_fb_format Gerd Hoffmann
2017-04-24 6:25 ` Gerd Hoffmann
2017-04-25 3:18 ` Michel Dänzer
2017-04-25 3:18 ` Michel Dänzer
2017-04-25 9:52 ` Ville Syrjälä
2017-04-26 2:00 ` Michel Dänzer
2017-04-26 2:00 ` Michel Dänzer
2017-04-26 14:30 ` Ville Syrjälä [this message]
2017-04-26 14:30 ` Ville Syrjälä
2017-04-26 5:53 ` Gerd Hoffmann
2017-04-26 5:53 ` Gerd Hoffmann
2017-04-26 9:21 ` Michel Dänzer
2017-04-26 9:21 ` Michel Dänzer
2017-04-26 12:11 ` Gerd Hoffmann
2017-04-26 12:11 ` Gerd Hoffmann
2017-04-27 0:52 ` Michel Dänzer
2017-04-27 0:52 ` Michel Dänzer
2017-04-27 6:45 ` Gerd Hoffmann
2017-04-27 6:45 ` Gerd Hoffmann
2017-04-27 7:02 ` Michel Dänzer
2017-04-28 10:02 ` Gerd Hoffmann
2017-04-28 10:02 ` Gerd Hoffmann
2017-04-26 13:28 ` Eric Engestrom
2017-04-26 13:28 ` Eric Engestrom
2017-04-26 13:57 ` Gerd Hoffmann
2017-04-26 13:57 ` Gerd Hoffmann
2017-04-24 6:25 ` [PATCH 4/6] drm: fourcc byteorder: adapt bochs-drm to drm_mode_legacy_fb_format update Gerd Hoffmann
2017-04-24 6:25 ` Gerd Hoffmann
2017-04-24 6:25 ` Gerd Hoffmann
2017-04-24 6:25 ` [PATCH 5/6] drm: fourcc byteorder: adapt virtio " Gerd Hoffmann
2017-04-24 6:25 ` Gerd Hoffmann
2017-04-24 6:25 ` Gerd Hoffmann
2017-04-24 6:25 ` [PATCH 6/6] drm: fourcc byteorder: virtio restrict to XRGB8888 Gerd Hoffmann
2017-04-24 6:25 ` Gerd Hoffmann
[not found] ` <20170424062532.26722-1-kraxel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2017-04-24 7:03 ` [PATCH 0/6] drm: tackle byteorder issues, take two Michel Dänzer
[not found] ` <484f319e-c2b7-adc8-4ecf-537803cc2eee-otUistvHUpPR7s880joybQ@public.gmane.org>
2017-04-24 7:36 ` Gerd Hoffmann
2017-04-24 7:54 ` Michel Dänzer
[not found] ` <f6555947-598f-0dfe-b15d-cda291778e8e-otUistvHUpPR7s880joybQ@public.gmane.org>
2017-04-24 14:26 ` Ville Syrjälä
2017-04-24 17:06 ` Daniel Stone
[not found] ` <20170424142603.GX30290-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-04-24 17:28 ` Ville Syrjälä
2017-04-25 0:49 ` Michel Dänzer
[not found] ` <65ba8ab7-d647-4b9e-1e8c-aa6e9b1ff996-otUistvHUpPR7s880joybQ@public.gmane.org>
2017-04-25 9:50 ` Ville Syrjälä
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