From: Marc Zyngier <marc.zyngier@arm.com> To: Christoffer Dall <christoffer.dall@linaro.org> Cc: kvm@vger.kernel.org, David Daney <david.daney@cavium.com>, Catalin Marinas <catalin.marinas@arm.com>, Robert Richter <rrichter@cavium.com>, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: [PATCH 25/31] arm64: Add workaround for Cavium Thunder erratum 30115 Date: Wed, 3 May 2017 11:46:00 +0100 [thread overview] Message-ID: <20170503104606.19342-26-marc.zyngier@arm.com> (raw) In-Reply-To: <20170503104606.19342-1-marc.zyngier@arm.com> From: David Daney <david.daney@cavium.com> Some Cavium Thunder CPUs suffer a problem where a KVM guest may inadvertently cause the host kernel to quit receiving interrupts. Use the Group-0/1 trapping in order to deal with it. [maz]: Adapted patch to the Group-0/1 trapping, reworked commit log Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 11 +++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/kernel/cpu_errata.c | 21 +++++++++++++++++++++ virt/kvm/arm/vgic/vgic-v3.c | 7 +++++++ 5 files changed, 42 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 10f2dddbf449..f5f93dca54b7 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -62,6 +62,7 @@ stable kernels. | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | | Cavium | ThunderX SMMUv2 | #27704 | N/A | +| Cavium | ThunderX Core | #30115 | CAVIUM_ERRATUM_30115 | | | | | | | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | | | | | | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 3dcd7ec69bca..0950b21e4d17 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -480,6 +480,17 @@ config CAVIUM_ERRATUM_27456 If unsure, say Y. +config CAVIUM_ERRATUM_30115 + bool "Cavium erratum 30115: Guest may disable interrupts in host" + default y + help + On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through + 1.2, and T83 Pass 1.0, KVM guest execution may disable + interrupts in host. Trapping GICv3 group-1 accesses sidesteps + the issue. + + If unsure, say Y. + config QCOM_FALKOR_ERRATUM_1003 bool "Falkor E1003: Incorrect translation due to ASID change" default y diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index b3aab8a17868..8d2272c6822c 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -38,7 +38,8 @@ #define ARM64_WORKAROUND_REPEAT_TLBI 17 #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18 #define ARM64_WORKAROUND_858921 19 +#define ARM64_WORKAROUND_CAVIUM_30115 20 -#define ARM64_NCAPS 20 +#define ARM64_NCAPS 21 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 2ed2a7657711..0e27f86ee709 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -133,6 +133,27 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00), }, #endif +#ifdef CONFIG_CAVIUM_ERRATUM_30115 + { + /* Cavium ThunderX, T88 pass 1.x - 2.2 */ + .desc = "Cavium erratum 30115", + .capability = ARM64_WORKAROUND_CAVIUM_30115, + MIDR_RANGE(MIDR_THUNDERX, 0x00, + (1 << MIDR_VARIANT_SHIFT) | 2), + }, + { + /* Cavium ThunderX, T81 pass 1.0 - 1.2 */ + .desc = "Cavium erratum 30115", + .capability = ARM64_WORKAROUND_CAVIUM_30115, + MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02), + }, + { + /* Cavium ThunderX, T83 pass 1.0 */ + .desc = "Cavium erratum 30115", + .capability = ARM64_WORKAROUND_CAVIUM_30115, + MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00), + }, +#endif { .desc = "Mismatched cache line size", .capability = ARM64_MISMATCHED_CACHE_LINE_SIZE, diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c index 7c82c586d44a..445e86c8b00c 100644 --- a/virt/kvm/arm/vgic/vgic-v3.c +++ b/virt/kvm/arm/vgic/vgic-v3.c @@ -390,6 +390,13 @@ int vgic_v3_probe(const struct gic_kvm_info *info) if (kvm_vgic_global_state.vcpu_base == 0) kvm_info("disabling GICv2 emulation\n"); +#ifdef CONFIG_ARM64 + if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) { + group0_trap = true; + group1_trap = true; + } +#endif + if (group0_trap || group1_trap) { kvm_info("GICv3 sysreg trapping enabled (reduced performance)\n"); static_branch_enable(&vgic_v3_cpuif_trap); -- 2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 25/31] arm64: Add workaround for Cavium Thunder erratum 30115 Date: Wed, 3 May 2017 11:46:00 +0100 [thread overview] Message-ID: <20170503104606.19342-26-marc.zyngier@arm.com> (raw) In-Reply-To: <20170503104606.19342-1-marc.zyngier@arm.com> From: David Daney <david.daney@cavium.com> Some Cavium Thunder CPUs suffer a problem where a KVM guest may inadvertently cause the host kernel to quit receiving interrupts. Use the Group-0/1 trapping in order to deal with it. [maz]: Adapted patch to the Group-0/1 trapping, reworked commit log Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 11 +++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/kernel/cpu_errata.c | 21 +++++++++++++++++++++ virt/kvm/arm/vgic/vgic-v3.c | 7 +++++++ 5 files changed, 42 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 10f2dddbf449..f5f93dca54b7 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -62,6 +62,7 @@ stable kernels. | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | | Cavium | ThunderX SMMUv2 | #27704 | N/A | +| Cavium | ThunderX Core | #30115 | CAVIUM_ERRATUM_30115 | | | | | | | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | | | | | | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 3dcd7ec69bca..0950b21e4d17 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -480,6 +480,17 @@ config CAVIUM_ERRATUM_27456 If unsure, say Y. +config CAVIUM_ERRATUM_30115 + bool "Cavium erratum 30115: Guest may disable interrupts in host" + default y + help + On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through + 1.2, and T83 Pass 1.0, KVM guest execution may disable + interrupts in host. Trapping GICv3 group-1 accesses sidesteps + the issue. + + If unsure, say Y. + config QCOM_FALKOR_ERRATUM_1003 bool "Falkor E1003: Incorrect translation due to ASID change" default y diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index b3aab8a17868..8d2272c6822c 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -38,7 +38,8 @@ #define ARM64_WORKAROUND_REPEAT_TLBI 17 #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18 #define ARM64_WORKAROUND_858921 19 +#define ARM64_WORKAROUND_CAVIUM_30115 20 -#define ARM64_NCAPS 20 +#define ARM64_NCAPS 21 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 2ed2a7657711..0e27f86ee709 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -133,6 +133,27 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00), }, #endif +#ifdef CONFIG_CAVIUM_ERRATUM_30115 + { + /* Cavium ThunderX, T88 pass 1.x - 2.2 */ + .desc = "Cavium erratum 30115", + .capability = ARM64_WORKAROUND_CAVIUM_30115, + MIDR_RANGE(MIDR_THUNDERX, 0x00, + (1 << MIDR_VARIANT_SHIFT) | 2), + }, + { + /* Cavium ThunderX, T81 pass 1.0 - 1.2 */ + .desc = "Cavium erratum 30115", + .capability = ARM64_WORKAROUND_CAVIUM_30115, + MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02), + }, + { + /* Cavium ThunderX, T83 pass 1.0 */ + .desc = "Cavium erratum 30115", + .capability = ARM64_WORKAROUND_CAVIUM_30115, + MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00), + }, +#endif { .desc = "Mismatched cache line size", .capability = ARM64_MISMATCHED_CACHE_LINE_SIZE, diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c index 7c82c586d44a..445e86c8b00c 100644 --- a/virt/kvm/arm/vgic/vgic-v3.c +++ b/virt/kvm/arm/vgic/vgic-v3.c @@ -390,6 +390,13 @@ int vgic_v3_probe(const struct gic_kvm_info *info) if (kvm_vgic_global_state.vcpu_base == 0) kvm_info("disabling GICv2 emulation\n"); +#ifdef CONFIG_ARM64 + if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) { + group0_trap = true; + group1_trap = true; + } +#endif + if (group0_trap || group1_trap) { kvm_info("GICv3 sysreg trapping enabled (reduced performance)\n"); static_branch_enable(&vgic_v3_cpuif_trap); -- 2.11.0
next prev parent reply other threads:[~2017-05-03 10:46 UTC|newest] Thread overview: 162+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-05-03 10:45 [PATCH 00/31] arm64: KVM: Mediate access to GICv3 sysregs at EL2 Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-03 10:45 ` [PATCH 01/31] arm64: KVM: Fix decoding of Rt/Rt2 when trapping AArch32 CP accesses Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-03 10:45 ` [PATCH 02/31] arm64: KVM: Do not use stack-protector to compile EL2 code Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-03 10:45 ` [PATCH 03/31] arm: KVM: Do not use stack-protector to compile HYP code Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-03 10:45 ` [PATCH 04/31] KVM: arm/arm64: vgic-v2: Do not use Active+Pending state for a HW interrupt Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-03 10:45 ` [PATCH 05/31] KVM: arm/arm64: vgic-v3: " Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-03 10:45 ` [PATCH 06/31] KVM: arm/arm64: vgic-v3: Use PREbits to infer the number of ICH_APxRn_EL2 registers Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-03 10:45 ` [PATCH 07/31] KVM: arm/arm64: vgic-v3: Add accessors for the " Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-03 15:32 ` Mark Rutland 2017-05-03 15:32 ` Mark Rutland 2017-05-03 15:58 ` Marc Zyngier 2017-05-03 15:58 ` Marc Zyngier 2017-05-30 16:17 ` Marc Zyngier 2017-05-30 16:17 ` Marc Zyngier 2017-05-30 16:42 ` Mark Rutland 2017-05-30 16:42 ` Mark Rutland 2017-05-17 9:54 ` Auger Eric 2017-05-17 9:54 ` Auger Eric 2017-05-22 18:52 ` Marc Zyngier 2017-05-22 18:52 ` Marc Zyngier 2017-05-22 18:52 ` Marc Zyngier 2017-05-03 10:45 ` [PATCH 08/31] arm64: Add a facility to turn an ESR syndrome into a sysreg encoding Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-03 15:35 ` Mark Rutland 2017-05-03 15:35 ` Mark Rutland 2017-05-17 9:54 ` Auger Eric 2017-05-17 9:54 ` Auger Eric 2017-06-09 10:38 ` Catalin Marinas 2017-06-09 10:38 ` Catalin Marinas 2017-05-03 10:45 ` [PATCH 09/31] KVM: arm64: Make kvm_condition_valid32() accessible from EL2 Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-17 9:54 ` Auger Eric 2017-05-17 9:54 ` Auger Eric 2017-05-03 10:45 ` [PATCH 10/31] KVM: arm64: vgic-v3: Add hook to handle guest GICv3 sysreg accesses at EL2 Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-17 9:54 ` Auger Eric 2017-05-17 9:54 ` Auger Eric 2017-05-03 10:45 ` [PATCH 11/31] KVM: arm64: vgic-v3: Add ICV_BPR1_EL1 handler Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-17 15:39 ` Auger Eric 2017-05-17 15:39 ` Auger Eric 2017-05-03 10:45 ` [PATCH 12/31] KVM: arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-17 15:39 ` Auger Eric 2017-05-17 15:39 ` Auger Eric 2017-05-03 10:45 ` [PATCH 13/31] KVM: arm64: vgic-v3: Add ICV_IAR1_EL1 handler Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-18 7:41 ` Auger Eric 2017-05-18 7:41 ` Auger Eric 2017-05-22 17:52 ` Marc Zyngier 2017-05-22 17:52 ` Marc Zyngier 2017-05-23 7:22 ` Auger Eric 2017-05-23 7:22 ` Auger Eric 2017-05-23 9:26 ` Marc Zyngier 2017-05-23 9:26 ` Marc Zyngier 2017-05-03 10:45 ` [PATCH 14/31] KVM: arm64: vgic-v3: Add ICV_EOIR1_EL1 handler Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-30 7:48 ` Auger Eric 2017-05-30 7:48 ` Auger Eric 2017-05-30 14:24 ` Marc Zyngier 2017-05-30 14:24 ` Marc Zyngier 2017-05-31 6:33 ` Auger Eric 2017-05-31 6:33 ` Auger Eric 2017-05-31 6:46 ` Marc Zyngier 2017-05-31 6:46 ` Marc Zyngier 2017-05-31 6:46 ` Marc Zyngier 2017-05-31 7:26 ` Auger Eric 2017-05-31 7:26 ` Auger Eric 2017-05-31 7:54 ` Marc Zyngier 2017-05-31 7:54 ` Marc Zyngier 2017-05-03 10:45 ` [PATCH 15/31] KVM: arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-30 7:48 ` Auger Eric 2017-05-30 7:48 ` Auger Eric 2017-05-30 8:02 ` Auger Eric 2017-05-30 8:02 ` Auger Eric 2017-05-30 14:21 ` Marc Zyngier 2017-05-30 14:21 ` Marc Zyngier 2017-05-03 10:45 ` [PATCH 16/31] KVM: arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-30 8:05 ` Auger Eric 2017-05-30 8:05 ` Auger Eric 2017-05-03 10:45 ` [PATCH 17/31] KVM: arm64: vgic-v3: Enable trapping of Group-1 system registers Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-30 9:07 ` Auger Eric 2017-05-30 9:07 ` Auger Eric 2017-05-30 14:32 ` Marc Zyngier 2017-05-30 14:32 ` Marc Zyngier 2017-05-31 6:43 ` Auger Eric 2017-05-31 6:43 ` Auger Eric 2017-05-03 10:45 ` [PATCH 18/31] KVM: arm64: Enable GICv3 Group-1 sysreg trapping via command-line Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-03 10:45 ` [PATCH 19/31] KVM: arm64: vgic-v3: Add ICV_BPR0_EL1 handler Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-30 9:48 ` Auger Eric 2017-05-30 9:48 ` Auger Eric 2017-05-03 10:45 ` [PATCH 20/31] KVM: arm64: vgic-v3: Add ICV_IGNREN0_EL1 handler Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-30 9:48 ` Auger Eric 2017-05-30 9:48 ` Auger Eric 2017-05-03 10:45 ` [PATCH 21/31] KVM: arm64: vgic-v3: Add misc Group-0 handlers Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-30 9:48 ` Auger Eric 2017-05-30 9:48 ` Auger Eric 2017-05-03 10:45 ` [PATCH 22/31] KVM: arm64: vgic-v3: Enable trapping of Group-0 system registers Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-30 9:48 ` Auger Eric 2017-05-30 9:48 ` Auger Eric 2017-05-03 10:45 ` [PATCH 23/31] KVM: arm64: Enable GICv3 Group-0 sysreg trapping via command-line Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-03 10:45 ` [PATCH 24/31] arm64: Add MIDR values for Cavium cn83XX SoCs Marc Zyngier 2017-05-03 10:45 ` Marc Zyngier 2017-05-30 9:56 ` Auger Eric 2017-05-30 9:56 ` Auger Eric 2017-06-09 10:39 ` Catalin Marinas 2017-06-09 10:39 ` Catalin Marinas 2017-05-03 10:46 ` Marc Zyngier [this message] 2017-05-03 10:46 ` [PATCH 25/31] arm64: Add workaround for Cavium Thunder erratum 30115 Marc Zyngier 2017-05-30 9:56 ` Auger Eric 2017-05-30 9:56 ` Auger Eric 2017-06-09 10:43 ` Catalin Marinas 2017-06-09 10:43 ` Catalin Marinas 2017-05-03 10:46 ` [PATCH 26/31] KVM: arm64: vgic-v3: Add ICV_DIR_EL1 handler Marc Zyngier 2017-05-03 10:46 ` Marc Zyngier 2017-05-30 10:15 ` Auger Eric 2017-05-30 10:15 ` Auger Eric 2017-05-30 14:45 ` Marc Zyngier 2017-05-30 14:45 ` Marc Zyngier 2017-05-03 10:46 ` [PATCH 27/31] KVM: arm64: vgic-v3: Add ICV_RPR_EL1 handler Marc Zyngier 2017-05-03 10:46 ` Marc Zyngier 2017-05-30 10:16 ` Auger Eric 2017-05-30 10:16 ` Auger Eric 2017-05-03 10:46 ` [PATCH 28/31] KVM: arm64: vgic-v3: Add ICV_CTLR_EL1 handler Marc Zyngier 2017-05-03 10:46 ` Marc Zyngier 2017-05-30 10:27 ` Auger Eric 2017-05-30 10:27 ` Auger Eric 2017-05-03 10:46 ` [PATCH 29/31] KVM: arm64: vgic-v3: Add ICV_PMR_EL1 handler Marc Zyngier 2017-05-03 10:46 ` Marc Zyngier 2017-05-30 10:34 ` Auger Eric 2017-05-30 10:34 ` Auger Eric 2017-05-03 10:46 ` [PATCH 30/31] KVM: arm64: Enable GICv3 common sysreg trapping via command-line Marc Zyngier 2017-05-03 10:46 ` Marc Zyngier 2017-05-30 9:56 ` Auger Eric 2017-05-30 9:56 ` Auger Eric 2017-05-30 14:41 ` Marc Zyngier 2017-05-30 14:41 ` Marc Zyngier 2017-05-03 10:46 ` [PATCH 31/31] KVM: arm64: vgic-v3: Log which GICv3 system registers are trapped Marc Zyngier 2017-05-03 10:46 ` Marc Zyngier 2017-05-30 9:56 ` Auger Eric 2017-05-30 9:56 ` Auger Eric 2017-05-09 0:05 ` [PATCH 00/31] arm64: KVM: Mediate access to GICv3 sysregs at EL2 David Daney 2017-05-09 0:05 ` David Daney 2017-05-09 17:39 ` Marc Zyngier 2017-05-09 17:39 ` Marc Zyngier
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