[PATCH v2 0/2] reset: Basic reset controller

[PATCH v2 0/2] reset: Basic reset controller

[Joel Stanley]

Hello,

This is v2 of the basic reset controller, which addresses the points that
Philipp made. See the individual patches for changelogs. The original cover
letter follows:

In the Aspeed SoCs we have some reset registers spread out in various parts of
the soc: in the system controller IP, as well as other peripherals. I need to be
able to deassert those resets before other drivers work.

In writing a driver to do this I realised it was very generic. So instead I've
sent a generic driver that can be used by the device tree to clear reset lines
described by single bits in a register.

I've tested this driver on our SoC to release the UART reset.

Joel Stanley (2):
  dt-bindings: reset: Add bindings for basic reset controller
  reset: Add basic single-register reset driver

 .../devicetree/bindings/reset/reset-basic.txt      |  43 ++++++++
 drivers/reset/Kconfig                              |   7 ++
 drivers/reset/Makefile                             |   1 +
 drivers/reset/reset-basic.c                        | 113 +++++++++++++++++++++
 4 files changed, 164 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/reset-basic.txt
 create mode 100644 drivers/reset/reset-basic.c

-- 
2.11.0

[PATCH v2 0/2] reset: Basic reset controller

[Joel Stanley]

Hello,

This is v2 of the basic reset controller, which addresses the points that
Philipp made. See the individual patches for changelogs. The original cover
letter follows:

In the Aspeed SoCs we have some reset registers spread out in various parts of
the soc: in the system controller IP, as well as other peripherals. I need to be
able to deassert those resets before other drivers work.

In writing a driver to do this I realised it was very generic. So instead I've
sent a generic driver that can be used by the device tree to clear reset lines
described by single bits in a register.

I've tested this driver on our SoC to release the UART reset.

Joel Stanley (2):
  dt-bindings: reset: Add bindings for basic reset controller
  reset: Add basic single-register reset driver

 .../devicetree/bindings/reset/reset-basic.txt      |  43 ++++++++
 drivers/reset/Kconfig                              |   7 ++
 drivers/reset/Makefile                             |   1 +
 drivers/reset/reset-basic.c                        | 113 +++++++++++++++++++++
 4 files changed, 164 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/reset-basic.txt
 create mode 100644 drivers/reset/reset-basic.c

-- 
2.11.0

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[PATCH v2 1/2] dt-bindings: reset: Add bindings for basic reset controller

[Joel Stanley]

This adds the bindings documentation for a basic single-register reset
controller.

The bindings describe a single 32-bit register that contains up to 32
reset lines, each deasserted by clearing the appropriate bit in the
register. Optionally a property can be provided that changes this
behaviour to assert on clear.

Signed-off-by: Joel Stanley <joel@jms.id.au>

---
V2:
 Address review from Philipp:
 - add note about not auto clearing
 - add property for set to assert behaviour
 - use a decimal for the bit number

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 .../devicetree/bindings/reset/reset-basic.txt      | 43 ++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/reset-basic.txt

diff --git a/Documentation/devicetree/bindings/reset/reset-basic.txt b/Documentation/devicetree/bindings/reset/reset-basic.txt
new file mode 100644
index 000000000000..c19e5368be67
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/reset-basic.txt
@@ -0,0 +1,43 @@
+Basic single-register reset controller
+======================================
+
+This describes a generic reset controller where the reset lines are controlled
+by single bits within a 32-bit memory location. The memory location is assumed
+to be part of a syscon regmap.
+
+By default the bit will be cleared on deassert. This behaviour can be inverted
+with the assert-on-clear property mentioned below.
+
+The bits are assumed to not be auto-clearing, and therefore can be read back to
+determine the status.
+
+Reset controller required properties:
+ - compatible: should be "reset-basic"
+ - #reset-cells: must be set to 1
+ - reg: reset register location within regmap
+
+Reset controller optional properties:
+ - assert-on-clear: add this property when the hardware should clear (set to 0)
+   the bit should to assert the reset.
+   When this property is omitted the default is to set the bit to assert the
+   reset
+
+Device node required properties:
+ - resets phandle
+ - bit number, counting from zero, for the desired reset line. Max is 31.
+
+Example:
+
+syscon {
+	compatible = "syscon";
+
+	uart_reset: reset-controller@c {
+		compatible = "reset-basic";
+		#reset-cells = <1>;
+		reg = <0xc>;
+	};
+}
+
+&uart {
+	resets = <&uart_rest 4>;
+}
-- 
2.11.0

[PATCH v2 1/2] dt-bindings: reset: Add bindings for basic reset controller

[Joel Stanley]

This adds the bindings documentation for a basic single-register reset
controller.

The bindings describe a single 32-bit register that contains up to 32
reset lines, each deasserted by clearing the appropriate bit in the
register. Optionally a property can be provided that changes this
behaviour to assert on clear.

Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>

---
V2:
 Address review from Philipp:
 - add note about not auto clearing
 - add property for set to assert behaviour
 - use a decimal for the bit number

Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
---
 .../devicetree/bindings/reset/reset-basic.txt      | 43 ++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/reset-basic.txt

diff --git a/Documentation/devicetree/bindings/reset/reset-basic.txt b/Documentation/devicetree/bindings/reset/reset-basic.txt
new file mode 100644
index 000000000000..c19e5368be67
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/reset-basic.txt
@@ -0,0 +1,43 @@
+Basic single-register reset controller
+======================================
+
+This describes a generic reset controller where the reset lines are controlled
+by single bits within a 32-bit memory location. The memory location is assumed
+to be part of a syscon regmap.
+
+By default the bit will be cleared on deassert. This behaviour can be inverted
+with the assert-on-clear property mentioned below.
+
+The bits are assumed to not be auto-clearing, and therefore can be read back to
+determine the status.
+
+Reset controller required properties:
+ - compatible: should be "reset-basic"
+ - #reset-cells: must be set to 1
+ - reg: reset register location within regmap
+
+Reset controller optional properties:
+ - assert-on-clear: add this property when the hardware should clear (set to 0)
+   the bit should to assert the reset.
+   When this property is omitted the default is to set the bit to assert the
+   reset
+
+Device node required properties:
+ - resets phandle
+ - bit number, counting from zero, for the desired reset line. Max is 31.
+
+Example:
+
+syscon {
+	compatible = "syscon";
+
+	uart_reset: reset-controller@c {
+		compatible = "reset-basic";
+		#reset-cells = <1>;
+		reg = <0xc>;
+	};
+}
+
+&uart {
+	resets = <&uart_rest 4>;
+}
-- 
2.11.0

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[PATCH v2 2/2] reset: Add basic single-register reset driver

[Joel Stanley]

This driver is a basic single-register reset controller driver that
supports clearing a single bit in a register.

Signed-off-by: Joel Stanley <joel@jms.id.au>

---
v2:
  - Support assert-on-clear dt property
  - Depend on OF and MFD_SYSCON

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 drivers/reset/Kconfig       |   7 +++
 drivers/reset/Makefile      |   1 +
 drivers/reset/reset-basic.c | 113 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 121 insertions(+)
 create mode 100644 drivers/reset/reset-basic.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index d21c07ccc94e..8560e304905c 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -28,6 +28,13 @@ config RESET_ATH79
 	  This enables the ATH79 reset controller driver that supports the
 	  AR71xx SoC reset controller.
 
+config RESET_BASIC
+	bool "Basic Reset Driver"
+	depends on OF && MFD_SYSCON
+	help
+	  This enables a basic single-register reset controller driver that
+	  supports clearing a single bit in a register.
+
 config RESET_BERLIN
 	bool "Berlin Reset Driver" if COMPILE_TEST
 	default ARCH_BERLIN
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 02a74db94339..e8e8869e098d 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_STI) += sti/
 obj-$(CONFIG_ARCH_TEGRA) += tegra/
 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
+obj-$(CONFIG_RESET_BASIC) += reset-basic.o
 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
diff --git a/drivers/reset/reset-basic.c b/drivers/reset/reset-basic.c
new file mode 100644
index 000000000000..5afac408295a
--- /dev/null
+++ b/drivers/reset/reset-basic.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2017 IBM Corperation
+ *
+ * Joel Stanley <joel@jms.id.au>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/reset-controller.h>
+
+#define to_basic_reset_priv(p)		\
+	container_of((p), struct basic_reset_priv, rcdev)
+
+struct basic_reset_priv {
+	struct regmap			*regmap;
+	struct reset_controller_dev	rcdev;
+	u32				reg;
+	bool				assert_on_clear;
+};
+
+static int basic_reset_assert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	struct basic_reset_priv *priv = to_basic_reset_priv(rcdev);
+	u32 value = priv->assert_on_clear ? 0 : BIT(id);
+
+	regmap_update_bits(priv->regmap, priv->reg, BIT(id), value);
+
+	return 0;
+}
+
+static int basic_reset_deassert(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	struct basic_reset_priv *priv = to_basic_reset_priv(rcdev);
+	u32 value = priv->assert_on_clear ? BIT(id) : 0;
+
+	regmap_update_bits(priv->regmap, priv->reg, BIT(id), value);
+
+	return 0;
+}
+
+static int basic_reset_status(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	struct basic_reset_priv *priv = to_basic_reset_priv(rcdev);
+	u32 mask = BIT(id);
+	u32 val;
+
+	regmap_read(priv->regmap, priv->reg, &val);
+
+	return !!(val & mask);
+}
+
+static const struct reset_control_ops basic_reset_ops = {
+	.assert = basic_reset_assert,
+	.deassert = basic_reset_deassert,
+	.status = basic_reset_status,
+};
+
+static int basic_reset_probe(struct platform_device *pdev)
+{
+	struct device_node *parent_np = of_get_parent(pdev->dev.of_node);
+	struct basic_reset_priv *priv;
+	int ret;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->regmap = syscon_node_to_regmap(parent_np);
+	of_node_put(parent_np);
+	if (IS_ERR(priv->regmap))
+		return PTR_ERR(priv->regmap);
+
+	ret = of_property_read_u32(pdev->dev.of_node, "reg", &priv->reg);
+	if (ret)
+		return ret;
+
+	priv->assert_on_clear = of_property_read_bool(pdev->dev.of_node,
+			"assert-on-clear");
+
+	priv->rcdev.owner = THIS_MODULE;
+	priv->rcdev.ops = &basic_reset_ops;
+	priv->rcdev.of_node = pdev->dev.of_node;
+	priv->rcdev.nr_resets = 32;
+
+	return reset_controller_register(&priv->rcdev);
+}
+
+static const struct of_device_id basic_reset_dt_match[] = {
+	{ .compatible = "reset-basic" },
+	{ },
+};
+
+static struct platform_driver basic_reset_driver = {
+	.probe	= basic_reset_probe,
+	.driver	= {
+		.name = "basic-reset",
+		.of_match_table = basic_reset_dt_match,
+	},
+};
+builtin_platform_driver(basic_reset_driver);
-- 
2.11.0

Re: [v2,2/2] reset: Add basic single-register reset driver

[Russell Currey]

On Tue, 2017-05-30 at 15:38 +0930, Joel wrote:
> This driver is a basic single-register reset controller driver that
> supports clearing a single bit in a register.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>

Acked-by: Russell Currey <ruscur@russell.cc>

Re: [v2,2/2] reset: Add basic single-register reset driver

[Russell Currey]

On Tue, 2017-05-30 at 15:38 +0930, Joel wrote:
> This driver is a basic single-register reset controller driver that
> supports clearing a single bit in a register.
> 
> Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>

Acked-by: Russell Currey <ruscur-3Su/lFKaw5ejKv3TNrM5DQ@public.gmane.org>
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Re: [PATCH v2 1/2] dt-bindings: reset: Add bindings for basic reset controller

[Rob Herring]

On Tue, May 30, 2017 at 03:38:50PM +0930, Joel Stanley wrote:
> This adds the bindings documentation for a basic single-register reset
> controller.
> 
> The bindings describe a single 32-bit register that contains up to 32
> reset lines, each deasserted by clearing the appropriate bit in the
> register. Optionally a property can be provided that changes this
> behaviour to assert on clear.
> 

I think this is a good idea for kernel code, but not for bindings. We 
don't really want per register bindings. 

The problem with any generic/simple/basic binding is they always start 
that way. Then we add one property at a time not in any well planned 
way. I can easily come up with additions. For example, what about 
self-clearing reset bits. Or 2 bits per reset. Or multiple resets that 
have to be controlled together. 8 or 16-bit registers.

IRQs and GPIOs could also be described in some cases with just groups of 
32-bit registers for set,clear,status,mask,etc., but we don't do that in 
bindings for the same reasons.

Rob

Re: [PATCH v2 1/2] dt-bindings: reset: Add bindings for basic reset controller

[Joel Stanley]

On Thu, Jun 8, 2017 at 6:19 AM, Rob Herring <robh@kernel.org> wrote:
> On Tue, May 30, 2017 at 03:38:50PM +0930, Joel Stanley wrote:
>> This adds the bindings documentation for a basic single-register reset
>> controller.
>>
>> The bindings describe a single 32-bit register that contains up to 32
>> reset lines, each deasserted by clearing the appropriate bit in the
>> register. Optionally a property can be provided that changes this
>> behaviour to assert on clear.
>>
>
> I think this is a good idea for kernel code, but not for bindings. We
> don't really want per register bindings.
>
> The problem with any generic/simple/basic binding is they always start
> that way. Then we add one property at a time not in any well planned
> way. I can easily come up with additions. For example, what about
> self-clearing reset bits. Or 2 bits per reset. Or multiple resets that
> have to be controlled together. 8 or 16-bit registers.

Thanks for the explanation. I will send a v3 with aspeed specific bindings.

How should I handle the driver? Were you suggesting I keep it generic,
but with my aspeed compatible?

Cheers,

Joel

>
> IRQs and GPIOs could also be described in some cases with just groups of
> 32-bit registers for set,clear,status,mask,etc., but we don't do that in
> bindings for the same reasons.
>
> Rob

Re: [PATCH v2 1/2] dt-bindings: reset: Add bindings for basic reset controller

[Joel Stanley]

On Thu, Jun 8, 2017 at 6:19 AM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Tue, May 30, 2017 at 03:38:50PM +0930, Joel Stanley wrote:
>> This adds the bindings documentation for a basic single-register reset
>> controller.
>>
>> The bindings describe a single 32-bit register that contains up to 32
>> reset lines, each deasserted by clearing the appropriate bit in the
>> register. Optionally a property can be provided that changes this
>> behaviour to assert on clear.
>>
>
> I think this is a good idea for kernel code, but not for bindings. We
> don't really want per register bindings.
>
> The problem with any generic/simple/basic binding is they always start
> that way. Then we add one property at a time not in any well planned
> way. I can easily come up with additions. For example, what about
> self-clearing reset bits. Or 2 bits per reset. Or multiple resets that
> have to be controlled together. 8 or 16-bit registers.

Thanks for the explanation. I will send a v3 with aspeed specific bindings.

How should I handle the driver? Were you suggesting I keep it generic,
but with my aspeed compatible?

Cheers,

Joel

>
> IRQs and GPIOs could also be described in some cases with just groups of
> 32-bit registers for set,clear,status,mask,etc., but we don't do that in
> bindings for the same reasons.
>
> Rob
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