[PATCH 00/13] DVFS v2

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

These v2 fixes bugs found by CI, also shuffle things
around to get a bit more organized and avoid temporary
duplications.

Also by the last patch I try to make functions more generic
and include documentation.

So the only missing bit would be expanding that back to SKL.
But I suffered a lot with rebase around today and I'm sure
that skl patch would just increase the pain for now with no
benefit. So this is to be done after this start getting merged.

Thanks,
Rodrigo.

Kahola, Mika (3):
  drm/i915/cnl: Expose DVFS change functions
  drm/i915/cnl: DVFS for PLL enabling
  drm/i915/cnl: DVFS for PLL disabling

Paulo Zanoni (1):
  drm/i915/cnl: extract cnl_dvfs_{pre,post}_change

Rodrigo Vivi (9):
  drm/i915: Let's use more enum intel_dpll_id pll_id.
  drm/i915/cnl: Extract cnl_calc_pll_link following bxt style.
  drm/i915/skl: Extract skl_calc_pll_link following bxt,cnl style.
  drm/i915: Unify and export gen9+ port_clock calculation.
  drm/i915/cnl: Invert dvfs default level.
  drm/i915/cnl: Unify dvfs level selection.
  drm/i915/cnl: Only request voltage frequency switching when needed.
  drm/i915/cnl: When disabling pll put dvfs back to cdclk requirement.
  drm/i915: Make DVFS more generic and document them.

 drivers/gpu/drm/i915/intel_cdclk.c    | 108 ++++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_ddi.c      |  85 +++++++++++++++++---------
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  42 ++++++++-----
 drivers/gpu/drm/i915/intel_drv.h      |   7 ++-
 4 files changed, 175 insertions(+), 67 deletions(-)

-- 
2.13.5

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