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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH 12/13] drm/i915/cnl: When disabling pll put dvfs back to cdclk requirement.
Date: Tue,  3 Oct 2017 00:06:13 -0700	[thread overview]
Message-ID: <20171003070614.18396-13-rodrigo.vivi@intel.com> (raw)
In-Reply-To: <20171003070614.18396-1-rodrigo.vivi@intel.com>

Spec tells us to change the level "if the frequency will result
in a change to the voltage requirement."

When we don't have pll enabled yet we only base our level
calculation on cdclk. So let's do the same when disabling the
pll instead of forcing randomly to zero.

v2: Rebase.

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 85c000891439..4eb1be91a669 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2050,7 +2050,9 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
 				struct intel_shared_dpll *pll)
 {
 	uint32_t val;
-	int ret;
+	int ret = 0;
+	int cdclk, level;
+	bool change_level;
 
 	/*
 	 * 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
@@ -2062,7 +2064,11 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
 	 * requirement, follow the Display Voltage Frequency Switching
 	 * (DVFS) Sequence Before Frequency Change
 	 */
-	ret = cnl_dvfs_pre_change(dev_priv);
+	cdclk = dev_priv->cdclk.hw.cdclk;
+	level = cnl_dvfs_new_level(cdclk, 0);
+	change_level = cnl_dvfs_needs_change(dev_priv, level);
+	if (change_level)
+		ret = cnl_dvfs_pre_change(dev_priv);
 
 	/* 3. Disable DPLL through DPLL_ENABLE. */
 	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
@@ -2082,8 +2088,8 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
 	 * requirement, follow the Display Voltage Frequency Switching
 	 * (DVFS) Sequence After Frequency Change
 	 */
-	if (ret == 0)
-		cnl_dvfs_post_change(dev_priv, 0);
+	if (change_level && ret == 0)
+		cnl_dvfs_post_change(dev_priv, level);
 
 	/* 6. Disable DPLL power in DPLL_ENABLE. */
 	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
-- 
2.13.5

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  parent reply	other threads:[~2017-10-03  7:06 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-03  7:06 [PATCH 00/13] DVFS v2 Rodrigo Vivi
2017-10-03  7:06 ` [PATCH 01/13] drm/i915: Let's use more enum intel_dpll_id pll_id Rodrigo Vivi
2017-10-03  9:33   ` Mika Kahola
2017-10-03  7:06 ` [PATCH 02/13] drm/i915/cnl: Extract cnl_calc_pll_link following bxt style Rodrigo Vivi
2017-10-03 10:00   ` Mika Kahola
2017-10-03  7:06 ` [PATCH 03/13] drm/i915/skl: Extract skl_calc_pll_link following bxt, cnl style Rodrigo Vivi
2017-10-03 13:18   ` Mika Kahola
2017-10-03  7:06 ` [PATCH 04/13] drm/i915: Unify and export gen9+ port_clock calculation Rodrigo Vivi
2017-10-04  6:39   ` Mika Kahola
2017-10-04 19:38     ` Rodrigo Vivi
2017-10-04 21:26       ` Rodrigo Vivi
2017-10-05 10:49         ` Mika Kahola
2017-10-03  7:06 ` [PATCH 05/13] drm/i915/cnl: extract cnl_dvfs_{pre, post}_change Rodrigo Vivi
2017-10-04 21:58   ` Ausmus, James
2017-10-04 22:05   ` Manasi Navare
2017-10-03  7:06 ` [PATCH 06/13] drm/i915/cnl: Expose DVFS change functions Rodrigo Vivi
2017-10-04 22:07   ` Manasi Navare
2017-10-03  7:06 ` [PATCH 07/13] drm/i915/cnl: DVFS for PLL enabling Rodrigo Vivi
2017-10-04 22:22   ` Manasi Navare
2017-10-17 15:44   ` Ville Syrjälä
2017-10-17 16:47     ` Rodrigo Vivi
2017-10-17 17:23       ` Ville Syrjälä
2017-10-17 17:45         ` Rodrigo Vivi
2017-10-17 18:02           ` Ville Syrjälä
2017-10-17 20:36             ` Ville Syrjälä
2017-10-17 23:23               ` Rodrigo Vivi
2017-10-18 13:23                 ` Ville Syrjälä
2017-10-03  7:06 ` [PATCH 08/13] drm/i915/cnl: DVFS for PLL disabling Rodrigo Vivi
2017-10-04 22:23   ` Manasi Navare
2017-10-03  7:06 ` [PATCH 09/13] drm/i915/cnl: Invert dvfs default level Rodrigo Vivi
2017-10-04  9:46   ` Mika Kahola
2017-10-04 19:36     ` Rodrigo Vivi
2017-10-04 22:40       ` Manasi Navare
2017-10-04 23:03         ` Manasi Navare
2017-10-03  7:06 ` [PATCH 10/13] drm/i915/cnl: Unify dvfs level selection Rodrigo Vivi
2017-10-04 13:20   ` Mika Kahola
2017-10-05 14:59     ` Rodrigo Vivi
2017-10-18 18:22       ` Paulo Zanoni
2017-10-03  7:06 ` [PATCH 11/13] drm/i915/cnl: Only request voltage frequency switching when needed Rodrigo Vivi
2017-10-05 12:07   ` Mika Kahola
2017-10-05 15:00     ` Rodrigo Vivi
2017-10-03  7:06 ` Rodrigo Vivi [this message]
2017-10-03  7:06 ` [PATCH 13/13] drm/i915: Make DVFS more generic and document them Rodrigo Vivi
2017-10-03  7:42 ` ✓ Fi.CI.BAT: success for DVFS v2 Patchwork
2017-10-03  9:07 ` ✗ Fi.CI.IGT: warning " Patchwork
2017-10-03 19:51 ` ✓ Fi.CI.BAT: success " Patchwork

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