All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Ausmus, James" <james.ausmus@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Intel GFX <intel-gfx@lists.freedesktop.org>,
	Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH 05/13] drm/i915/cnl: extract cnl_dvfs_{pre, post}_change
Date: Wed, 4 Oct 2017 14:58:14 -0700	[thread overview]
Message-ID: <CAA1Hj7Ss2AzK35UjfLhc=CAWg6_cRAx=YgGUrfGEt5yu9du2bA@mail.gmail.com> (raw)
In-Reply-To: <20171003070614.18396-6-rodrigo.vivi@intel.com>

On Tue, Oct 3, 2017 at 12:06 AM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> These functions even have their own page in our spec,
> so extract them from cnl_set_cdclk().
>
> v2: (By Rodrigo) Fixed inverted logic on error return of
>     cnl_dvfs_pre_change.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: James Ausmus <james.ausmus@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 33 +++++++++++++++++++++++----------
>  1 file changed, 23 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 87fc42b19336..b35eb145d66e 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1510,12 +1510,8 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
>         dev_priv->cdclk.hw.vco = vco;
>  }
>
> -static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
> -                         const struct intel_cdclk_state *cdclk_state)
> +static int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv)
>  {
> -       int cdclk = cdclk_state->cdclk;
> -       int vco = cdclk_state->vco;
> -       u32 val, divider, pcu_ack;
>         int ret;
>
>         mutex_lock(&dev_priv->rps.hw_lock);
> @@ -1524,11 +1520,30 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
>                                 SKL_CDCLK_READY_FOR_CHANGE,
>                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
>         mutex_unlock(&dev_priv->rps.hw_lock);
> -       if (ret) {
> +
> +       if (ret)
>                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
>                           ret);
> +
> +       return ret;
> +}
> +
> +static void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level)
> +{
> +       mutex_lock(&dev_priv->rps.hw_lock);
> +       sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, level);
> +       mutex_unlock(&dev_priv->rps.hw_lock);
> +}
> +
> +static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
> +                         const struct intel_cdclk_state *cdclk_state)
> +{
> +       int cdclk = cdclk_state->cdclk;
> +       int vco = cdclk_state->vco;
> +       u32 val, divider, pcu_ack;
> +
> +       if (cnl_dvfs_pre_change(dev_priv))
>                 return;
> -       }
>
>         /* cdclk = vco / 2 / div{1,2} */
>         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
> @@ -1575,9 +1590,7 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
>         I915_WRITE(CDCLK_CTL, val);
>
>         /* inform PCU of the change */
> -       mutex_lock(&dev_priv->rps.hw_lock);
> -       sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
> -       mutex_unlock(&dev_priv->rps.hw_lock);
> +       cnl_dvfs_post_change(dev_priv, pcu_ack);
>
>         intel_update_cdclk(dev_priv);
>  }
> --
> 2.13.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 


James Ausmus
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2017-10-04 21:58 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-03  7:06 [PATCH 00/13] DVFS v2 Rodrigo Vivi
2017-10-03  7:06 ` [PATCH 01/13] drm/i915: Let's use more enum intel_dpll_id pll_id Rodrigo Vivi
2017-10-03  9:33   ` Mika Kahola
2017-10-03  7:06 ` [PATCH 02/13] drm/i915/cnl: Extract cnl_calc_pll_link following bxt style Rodrigo Vivi
2017-10-03 10:00   ` Mika Kahola
2017-10-03  7:06 ` [PATCH 03/13] drm/i915/skl: Extract skl_calc_pll_link following bxt, cnl style Rodrigo Vivi
2017-10-03 13:18   ` Mika Kahola
2017-10-03  7:06 ` [PATCH 04/13] drm/i915: Unify and export gen9+ port_clock calculation Rodrigo Vivi
2017-10-04  6:39   ` Mika Kahola
2017-10-04 19:38     ` Rodrigo Vivi
2017-10-04 21:26       ` Rodrigo Vivi
2017-10-05 10:49         ` Mika Kahola
2017-10-03  7:06 ` [PATCH 05/13] drm/i915/cnl: extract cnl_dvfs_{pre, post}_change Rodrigo Vivi
2017-10-04 21:58   ` Ausmus, James [this message]
2017-10-04 22:05   ` Manasi Navare
2017-10-03  7:06 ` [PATCH 06/13] drm/i915/cnl: Expose DVFS change functions Rodrigo Vivi
2017-10-04 22:07   ` Manasi Navare
2017-10-03  7:06 ` [PATCH 07/13] drm/i915/cnl: DVFS for PLL enabling Rodrigo Vivi
2017-10-04 22:22   ` Manasi Navare
2017-10-17 15:44   ` Ville Syrjälä
2017-10-17 16:47     ` Rodrigo Vivi
2017-10-17 17:23       ` Ville Syrjälä
2017-10-17 17:45         ` Rodrigo Vivi
2017-10-17 18:02           ` Ville Syrjälä
2017-10-17 20:36             ` Ville Syrjälä
2017-10-17 23:23               ` Rodrigo Vivi
2017-10-18 13:23                 ` Ville Syrjälä
2017-10-03  7:06 ` [PATCH 08/13] drm/i915/cnl: DVFS for PLL disabling Rodrigo Vivi
2017-10-04 22:23   ` Manasi Navare
2017-10-03  7:06 ` [PATCH 09/13] drm/i915/cnl: Invert dvfs default level Rodrigo Vivi
2017-10-04  9:46   ` Mika Kahola
2017-10-04 19:36     ` Rodrigo Vivi
2017-10-04 22:40       ` Manasi Navare
2017-10-04 23:03         ` Manasi Navare
2017-10-03  7:06 ` [PATCH 10/13] drm/i915/cnl: Unify dvfs level selection Rodrigo Vivi
2017-10-04 13:20   ` Mika Kahola
2017-10-05 14:59     ` Rodrigo Vivi
2017-10-18 18:22       ` Paulo Zanoni
2017-10-03  7:06 ` [PATCH 11/13] drm/i915/cnl: Only request voltage frequency switching when needed Rodrigo Vivi
2017-10-05 12:07   ` Mika Kahola
2017-10-05 15:00     ` Rodrigo Vivi
2017-10-03  7:06 ` [PATCH 12/13] drm/i915/cnl: When disabling pll put dvfs back to cdclk requirement Rodrigo Vivi
2017-10-03  7:06 ` [PATCH 13/13] drm/i915: Make DVFS more generic and document them Rodrigo Vivi
2017-10-03  7:42 ` ✓ Fi.CI.BAT: success for DVFS v2 Patchwork
2017-10-03  9:07 ` ✗ Fi.CI.IGT: warning " Patchwork
2017-10-03 19:51 ` ✓ Fi.CI.BAT: success " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='CAA1Hj7Ss2AzK35UjfLhc=CAWg6_cRAx=YgGUrfGEt5yu9du2bA@mail.gmail.com' \
    --to=james.ausmus@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=paulo.r.zanoni@intel.com \
    --cc=rodrigo.vivi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.