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From: Manasi Navare <manasi.d.navare@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Kahola@freedesktop.org
Subject: Re: [PATCH 06/13] drm/i915/cnl: Expose DVFS change functions
Date: Wed, 4 Oct 2017 15:07:44 -0700	[thread overview]
Message-ID: <20171004220744.GE15590@intel.com> (raw)
In-Reply-To: <20171003070614.18396-7-rodrigo.vivi@intel.com>

On Tue, Oct 03, 2017 at 12:06:07AM -0700, Rodrigo Vivi wrote:
> From: "Kahola, Mika" <mika.kahola@intel.com>
> 
> DVFS computation needs cnl_dvfs_{pre,post}_change() functions to be exposed.
> These functions will be used when computing DVFS levels in intel_dpll_mgr.c
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Kahola, Mika <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
>  drivers/gpu/drm/i915/intel_drv.h   | 2 ++
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index b35eb145d66e..af8411c2a6b9 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1510,7 +1510,7 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
>  	dev_priv->cdclk.hw.vco = vco;
>  }
>  
> -static int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv)
> +int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv)
>  {
>  	int ret;
>  
> @@ -1528,7 +1528,7 @@ static int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv)
>  	return ret;
>  }
>  
> -static void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level)
> +void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level)
>  {
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, level);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index fe4650d6db03..934ccf17f8ab 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1323,6 +1323,8 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv);
>  void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
>  void cnl_init_cdclk(struct drm_i915_private *dev_priv);
>  void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
> +int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv);
> +void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level);
>  void bxt_init_cdclk(struct drm_i915_private *dev_priv);
>  void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> -- 
> 2.13.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2017-10-04 22:03 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-03  7:06 [PATCH 00/13] DVFS v2 Rodrigo Vivi
2017-10-03  7:06 ` [PATCH 01/13] drm/i915: Let's use more enum intel_dpll_id pll_id Rodrigo Vivi
2017-10-03  9:33   ` Mika Kahola
2017-10-03  7:06 ` [PATCH 02/13] drm/i915/cnl: Extract cnl_calc_pll_link following bxt style Rodrigo Vivi
2017-10-03 10:00   ` Mika Kahola
2017-10-03  7:06 ` [PATCH 03/13] drm/i915/skl: Extract skl_calc_pll_link following bxt, cnl style Rodrigo Vivi
2017-10-03 13:18   ` Mika Kahola
2017-10-03  7:06 ` [PATCH 04/13] drm/i915: Unify and export gen9+ port_clock calculation Rodrigo Vivi
2017-10-04  6:39   ` Mika Kahola
2017-10-04 19:38     ` Rodrigo Vivi
2017-10-04 21:26       ` Rodrigo Vivi
2017-10-05 10:49         ` Mika Kahola
2017-10-03  7:06 ` [PATCH 05/13] drm/i915/cnl: extract cnl_dvfs_{pre, post}_change Rodrigo Vivi
2017-10-04 21:58   ` Ausmus, James
2017-10-04 22:05   ` Manasi Navare
2017-10-03  7:06 ` [PATCH 06/13] drm/i915/cnl: Expose DVFS change functions Rodrigo Vivi
2017-10-04 22:07   ` Manasi Navare [this message]
2017-10-03  7:06 ` [PATCH 07/13] drm/i915/cnl: DVFS for PLL enabling Rodrigo Vivi
2017-10-04 22:22   ` Manasi Navare
2017-10-17 15:44   ` Ville Syrjälä
2017-10-17 16:47     ` Rodrigo Vivi
2017-10-17 17:23       ` Ville Syrjälä
2017-10-17 17:45         ` Rodrigo Vivi
2017-10-17 18:02           ` Ville Syrjälä
2017-10-17 20:36             ` Ville Syrjälä
2017-10-17 23:23               ` Rodrigo Vivi
2017-10-18 13:23                 ` Ville Syrjälä
2017-10-03  7:06 ` [PATCH 08/13] drm/i915/cnl: DVFS for PLL disabling Rodrigo Vivi
2017-10-04 22:23   ` Manasi Navare
2017-10-03  7:06 ` [PATCH 09/13] drm/i915/cnl: Invert dvfs default level Rodrigo Vivi
2017-10-04  9:46   ` Mika Kahola
2017-10-04 19:36     ` Rodrigo Vivi
2017-10-04 22:40       ` Manasi Navare
2017-10-04 23:03         ` Manasi Navare
2017-10-03  7:06 ` [PATCH 10/13] drm/i915/cnl: Unify dvfs level selection Rodrigo Vivi
2017-10-04 13:20   ` Mika Kahola
2017-10-05 14:59     ` Rodrigo Vivi
2017-10-18 18:22       ` Paulo Zanoni
2017-10-03  7:06 ` [PATCH 11/13] drm/i915/cnl: Only request voltage frequency switching when needed Rodrigo Vivi
2017-10-05 12:07   ` Mika Kahola
2017-10-05 15:00     ` Rodrigo Vivi
2017-10-03  7:06 ` [PATCH 12/13] drm/i915/cnl: When disabling pll put dvfs back to cdclk requirement Rodrigo Vivi
2017-10-03  7:06 ` [PATCH 13/13] drm/i915: Make DVFS more generic and document them Rodrigo Vivi
2017-10-03  7:42 ` ✓ Fi.CI.BAT: success for DVFS v2 Patchwork
2017-10-03  9:07 ` ✗ Fi.CI.IGT: warning " Patchwork
2017-10-03 19:51 ` ✓ Fi.CI.BAT: success " Patchwork

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