[PATCH 1/4] drm/i915: Disable DC states around GMBUS on GLK

[PATCH 1/4] drm/i915: Disable DC states around GMBUS on GLK

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Prevent the DMC from destroying GMBUS transfers on GLK. GMBUS
lives in PG1 so DC off is all we need.

Cc: stable@vger.kernel.org
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 96ab74f3d101..522e0a63090f 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1792,6 +1792,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	BIT_ULL(POWER_DOMAIN_GT_IRQ) |			\
 	BIT_ULL(POWER_DOMAIN_MODESET) |			\
 	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
+	BIT_ULL(POWER_DOMAIN_GMBUS) |			\
 	BIT_ULL(POWER_DOMAIN_INIT))
 
 #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\
-- 
2.13.6

[PATCH 2/4] drm/i915: No need to power up PG2 for GMBUS on BXT

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

GMBUS lives in PG1, so no need to power up PG2. We do want to prevent
the DMC from making a mess of things though, so add GMBUS to the DC off
power well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 522e0a63090f..db9d57f39534 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1726,13 +1726,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	BIT_ULL(POWER_DOMAIN_AUX_C) |			\
 	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
 	BIT_ULL(POWER_DOMAIN_VGA) |				\
-	BIT_ULL(POWER_DOMAIN_GMBUS) |			\
 	BIT_ULL(POWER_DOMAIN_INIT))
 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (		\
 	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |		\
 	BIT_ULL(POWER_DOMAIN_GT_IRQ) |			\
 	BIT_ULL(POWER_DOMAIN_MODESET) |			\
 	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
+	BIT_ULL(POWER_DOMAIN_GMBUS) |			\
 	BIT_ULL(POWER_DOMAIN_INIT))
 #define BXT_DPIO_CMN_A_POWER_DOMAINS (			\
 	BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |		\
-- 
2.13.6

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[PATCH 3/4] drm/i915: Clean up the PNV bit banging vs. GMBUS clock gating w/a

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Give a proper name for the GMBUS clock gating disable bit on PNV,
and rename intel_i2c_quirk_set() to pnv_gmbus_clock_gating() for
clarity.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_i2c.c | 21 ++++++++++++---------
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 09bf043c1c2e..98e1781bce50 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3278,6 +3278,7 @@ enum i915_power_well_id {
 # define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
 # define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
 # define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
+# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
 # define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
 # define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
 # define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 49fdf09f9919..a8c08994f505 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -128,19 +128,17 @@ intel_i2c_reset(struct drm_i915_private *dev_priv)
 	I915_WRITE(GMBUS4, 0);
 }
 
-static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
+static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
+				   bool enable)
 {
 	u32 val;
 
 	/* When using bit bashing for I2C, this bit needs to be set to 1 */
-	if (!IS_PINEVIEW(dev_priv))
-		return;
-
 	val = I915_READ(DSPCLK_GATE_D);
-	if (enable)
-		val |= DPCUNIT_CLOCK_GATE_DISABLE;
+	if (!enable)
+		val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
 	else
-		val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
+		val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
 	I915_WRITE(DSPCLK_GATE_D, val);
 }
 
@@ -221,7 +219,10 @@ intel_gpio_pre_xfer(struct i2c_adapter *adapter)
 	struct drm_i915_private *dev_priv = bus->dev_priv;
 
 	intel_i2c_reset(dev_priv);
-	intel_i2c_quirk_set(dev_priv, true);
+
+	if (IS_PINEVIEW(dev_priv))
+		pnv_gmbus_clock_gating(dev_priv, false);
+
 	set_data(bus, 1);
 	set_clock(bus, 1);
 	udelay(I2C_RISEFALL_TIME);
@@ -238,7 +239,9 @@ intel_gpio_post_xfer(struct i2c_adapter *adapter)
 
 	set_data(bus, 1);
 	set_clock(bus, 1);
-	intel_i2c_quirk_set(dev_priv, false);
+
+	if (IS_PINEVIEW(dev_priv))
+		pnv_gmbus_clock_gating(dev_priv, true);
 }
 
 static void
-- 
2.13.6

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[PATCH 4/4] drm/i915: Disable GMBUS clock gating around GMBUS transfers on gen9+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Gen9+ need to disable GMBUS clock gating when doing multi part
transfers. Otherwise clock gating will kick in when GMBUS is in
the WAIT state and presumably that will corrupt the transfer.
This is documented as Display WA #0868.

Apparently older hardware doesn't allow clock gating in the WAIT
state and thus are unaffected by this problem.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 ++++
 drivers/gpu/drm/i915/intel_i2c.c | 38 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 98e1781bce50..827edbfbd5df 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3859,6 +3859,9 @@ enum {
 #define   PWM2_GATING_DIS		(1 << 14)
 #define   PWM1_GATING_DIS		(1 << 13)
 
+#define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
+#define   BXT_GMBUS_GATING_DIS		(1 << 14)
+
 #define _CLKGATE_DIS_PSL_A		0x46520
 #define _CLKGATE_DIS_PSL_B		0x46524
 #define _CLKGATE_DIS_PSL_C		0x46528
@@ -7553,6 +7556,7 @@ enum {
 #define FDI_RX_CHICKEN(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
 
 #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
+#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1<<31)
 #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
 #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index a8c08994f505..6d3361a0ec76 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -142,6 +142,32 @@ static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
 	I915_WRITE(DSPCLK_GATE_D, val);
 }
 
+static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
+				   bool enable)
+{
+	u32 val;
+
+	val = I915_READ(SOUTH_DSPCLK_GATE_D);
+	if (!enable)
+		val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
+	else
+		val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
+	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
+}
+
+static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
+				   bool enable)
+{
+	u32 val;
+
+	val = I915_READ(GEN9_CLKGATE_DIS_4);
+	if (!enable)
+		val |= BXT_GMBUS_GATING_DIS;
+	else
+		val &= ~BXT_GMBUS_GATING_DIS;
+	I915_WRITE(GEN9_CLKGATE_DIS_4, val);
+}
+
 static u32 get_reserved(struct intel_gmbus *bus)
 {
 	struct drm_i915_private *dev_priv = bus->dev_priv;
@@ -484,6 +510,12 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
 	int i = 0, inc, try = 0;
 	int ret = 0;
 
+	/* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
+	if (IS_GEN9_LP(dev_priv))
+		bxt_gmbus_clock_gating(dev_priv, false);
+	else if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) >= 9)
+		pch_gmbus_clock_gating(dev_priv, false);
+
 retry:
 	I915_WRITE_FW(GMBUS0, bus->reg0);
 
@@ -585,6 +617,12 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
 	ret = -EAGAIN;
 
 out:
+	/* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
+	if (IS_GEN9_LP(dev_priv))
+		bxt_gmbus_clock_gating(dev_priv, true);
+	else if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) >= 9)
+		pch_gmbus_clock_gating(dev_priv, true);
+
 	return ret;
 }
 
-- 
2.13.6

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Re: [PATCH 3/4] drm/i915: Clean up the PNV bit banging vs. GMBUS clock gating w/a

[Chris Wilson]

Quoting Ville Syrjala (2017-12-08 21:37:38)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Give a proper name for the GMBUS clock gating disable bit on PNV,
> and rename intel_i2c_quirk_set() to pnv_gmbus_clock_gating() for
> clarity.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Through all the inversions and name changes, the code remains the same.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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✗ Fi.CI.BAT: warning for series starting with [1/4] drm/i915: Disable DC states around GMBUS on GLK

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Disable DC states around GMBUS on GLK
URL   : https://patchwork.freedesktop.org/series/35117/
State : warning

== Summary ==

Series 35117v1 series starting with [1/4] drm/i915: Disable DC states around GMBUS on GLK
https://patchwork.freedesktop.org/api/1.0/series/35117/revisions/1/mbox/

Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                pass       -> FAIL       (fi-gdg-551) fdo#102575
Test kms_busy:
        Subgroup basic-flip-a:
                dmesg-warn -> PASS       (fi-elk-e7500) fdo#103989
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                dmesg-warn -> PASS       (fi-kbl-r) fdo#104172
        Subgroup suspend-read-crc-pipe-b:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713
                pass       -> DMESG-WARN (fi-kbl-r)

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:444s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:438s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:383s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:519s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:280s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:495s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:509s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:488s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:472s
fi-elk-e7500     total:224  pass:164  dwarn:14  dfail:0   fail:0   skip:45 
fi-gdg-551       total:288  pass:178  dwarn:1   dfail:0   fail:1   skip:108 time:268s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:359s
fi-hsw-4770r     total:288  pass:224  dwarn:0   dfail:0   fail:0   skip:64  time:266s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:400s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:482s
fi-ivb-3770      total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:450s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:488s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:528s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:477s
fi-kbl-r         total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  time:533s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:598s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:462s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:538s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:577s
fi-skl-6700k     total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:520s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:501s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:449s
fi-snb-2520m     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:548s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:420s
Blacklisted hosts:
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:589s
fi-cnl-y         total:239  pass:213  dwarn:0   dfail:0   fail:1   skip:24 
fi-glk-dsi       total:288  pass:256  dwarn:0   dfail:0   fail:2   skip:30  time:509s
fi-glk-1 failed to collect. IGT log at Patchwork_7455/fi-glk-1/igt.log

06dd422e3209a968c420e10504f75fbbe897f06c drm-tip: 2017y-12m-08d-21h-06m-35s UTC integration manifest
acd7e456cfb6 drm/i915: Disable GMBUS clock gating around GMBUS transfers on gen9+
20084de60144 drm/i915: Clean up the PNV bit banging vs. GMBUS clock gating w/a
2bd05cb8ba50 drm/i915: No need to power up PG2 for GMBUS on BXT
ec31545a1805 drm/i915: Disable DC states around GMBUS on GLK

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7455/issues.html
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Re: [Intel-gfx] [PATCH 1/4] drm/i915: Disable DC states around GMBUS on GLK

[Pandiyan, Dhinakaran]

On Fri, 2017-12-08 at 23:37 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Prevent the DMC from destroying GMBUS transfers on GLK. GMBUS
> lives in PG1 so DC off is all we need.
> 
Just so that I understand this correctly. DMC is expected to take care
of managing power for GMBUS transfers without the driver explicitly
turning on/off the power well 1 but it isn't. Do you know if this is a
DMC regression?

> Cc: stable@vger.kernel.org
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 96ab74f3d101..522e0a63090f 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1792,6 +1792,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>  	BIT_ULL(POWER_DOMAIN_GT_IRQ) |			\
>  	BIT_ULL(POWER_DOMAIN_MODESET) |			\
>  	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> +	BIT_ULL(POWER_DOMAIN_GMBUS) |			\
>  	BIT_ULL(POWER_DOMAIN_INIT))
>  
>  #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Disable DC states around GMBUS on GLK

[Ville Syrjälä]

On Mon, Dec 11, 2017 at 06:41:05PM +0000, Pandiyan, Dhinakaran wrote:
> On Fri, 2017-12-08 at 23:37 +0200, Ville Syrjala wrote:
> > From: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> > 
> > Prevent the DMC from destroying GMBUS transfers on GLK. GMBUS
> > lives in PG1 so DC off is all we need.
> > 
> Just so that I understand this correctly. DMC is expected to take care
> of managing power for GMBUS transfers without the driver explicitly
> turning on/off the power well 1 but it isn't. Do you know if this is a
> DMC regression?

No idea. The docs don't seem to even mention DMC and GMBUS in the same
sentence. But since DP AUX needs DC off I don't see why GMBUS would
be all that different.

And with bit banging I would be somewhat surprised if DMC could
maintain the state of the pins while in DC5. Although I suppose it
might be possible that the hw automagically prevents DC5 when we're
driving any of the pins.

Art?

> 
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 96ab74f3d101..522e0a63090f 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -1792,6 +1792,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> >  	BIT_ULL(POWER_DOMAIN_GT_IRQ) |			\
> >  	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> >  	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> > +	BIT_ULL(POWER_DOMAIN_GMBUS) |			\
> >  	BIT_ULL(POWER_DOMAIN_INIT))
> >  
> >  #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\

-- 
Ville Syrj�l�
Intel OTC

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Disable DC states around GMBUS on GLK

[Ville Syrjälä]

On Mon, Dec 11, 2017 at 06:41:05PM +0000, Pandiyan, Dhinakaran wrote:
> On Fri, 2017-12-08 at 23:37 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Prevent the DMC from destroying GMBUS transfers on GLK. GMBUS
> > lives in PG1 so DC off is all we need.
> > 
> Just so that I understand this correctly. DMC is expected to take care
> of managing power for GMBUS transfers without the driver explicitly
> turning on/off the power well 1 but it isn't. Do you know if this is a
> DMC regression?

No idea. The docs don't seem to even mention DMC and GMBUS in the same
sentence. But since DP AUX needs DC off I don't see why GMBUS would
be all that different.

And with bit banging I would be somewhat surprised if DMC could
maintain the state of the pins while in DC5. Although I suppose it
might be possible that the hw automagically prevents DC5 when we're
driving any of the pins.

Art?

> 
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 96ab74f3d101..522e0a63090f 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -1792,6 +1792,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> >  	BIT_ULL(POWER_DOMAIN_GT_IRQ) |			\
> >  	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> >  	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> > +	BIT_ULL(POWER_DOMAIN_GMBUS) |			\
> >  	BIT_ULL(POWER_DOMAIN_INIT))
> >  
> >  #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 4/4] drm/i915: Disable GMBUS clock gating around GMBUS transfers on gen9+

[Pandiyan, Dhinakaran]

On Fri, 2017-12-08 at 23:37 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Gen9+ need to disable GMBUS clock gating when doing multi part
> transfers. Otherwise clock gating will kick in when GMBUS is in
> the WAIT state and presumably that will corrupt the transfer.
> This is documented as Display WA #0868.
> 
> Apparently older hardware doesn't allow clock gating in the WAIT
> state and thus are unaffected by this problem.
> 
Checked this against bspec, lgtm.

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> with
one comment below.


> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  4 ++++
>  drivers/gpu/drm/i915/intel_i2c.c | 38 ++++++++++++++++++++++++++++++++++++++
>  2 files changed, 42 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 98e1781bce50..827edbfbd5df 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3859,6 +3859,9 @@ enum {
>  #define   PWM2_GATING_DIS		(1 << 14)
>  #define   PWM1_GATING_DIS		(1 << 13)
>  
> +#define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
> +#define   BXT_GMBUS_GATING_DIS		(1 << 14)
> +
>  #define _CLKGATE_DIS_PSL_A		0x46520
>  #define _CLKGATE_DIS_PSL_B		0x46524
>  #define _CLKGATE_DIS_PSL_C		0x46528
> @@ -7553,6 +7556,7 @@ enum {
>  #define FDI_RX_CHICKEN(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
>  
>  #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
> +#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1<<31)
>  #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
>  #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
>  #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index a8c08994f505..6d3361a0ec76 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -142,6 +142,32 @@ static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
>  	I915_WRITE(DSPCLK_GATE_D, val);
>  }
>  
> +static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
> +				   bool enable)
> +{
> +	u32 val;
> +
> +	val = I915_READ(SOUTH_DSPCLK_GATE_D);
> +	if (!enable)
> +		val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
> +	else
> +		val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
> +	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> +}
> +
> +static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
> +				   bool enable)
> +{
> +	u32 val;
> +
> +	val = I915_READ(GEN9_CLKGATE_DIS_4);
> +	if (!enable)
> +		val |= BXT_GMBUS_GATING_DIS;
> +	else
> +		val &= ~BXT_GMBUS_GATING_DIS;
> +	I915_WRITE(GEN9_CLKGATE_DIS_4, val);
> +}
> +
>  static u32 get_reserved(struct intel_gmbus *bus)
>  {
>  	struct drm_i915_private *dev_priv = bus->dev_priv;
> @@ -484,6 +510,12 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
>  	int i = 0, inc, try = 0;
>  	int ret = 0;
>  
> +	/* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
> +	if (IS_GEN9_LP(dev_priv))
> +		bxt_gmbus_clock_gating(dev_priv, false);
> +	else if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) >= 9)

Given that this is a platform specific workaround, I think it is better
to keep this [9,10]


> +		pch_gmbus_clock_gating(dev_priv, false);
> +
>  retry:
>  	I915_WRITE_FW(GMBUS0, bus->reg0);
>  
> @@ -585,6 +617,12 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
>  	ret = -EAGAIN;
>  
>  out:
> +	/* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
> +	if (IS_GEN9_LP(dev_priv))
> +		bxt_gmbus_clock_gating(dev_priv, true);
> +	else if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) >= 9)
> +		pch_gmbus_clock_gating(dev_priv, true);
> +
>  	return ret;
>  }
>  
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RE: [Intel-gfx] [PATCH 1/4] drm/i915: Disable DC states around GMBUS on GLK

[Runyan, Arthur J]

You're right.  DC5 could disrupt GMBUS.  We forgot to add a note on GMBUS when it got moved under DMC domain in GLK and BXT/APL.  I'll take care of that.

-----Original Message-----
From: Ville Syrj�l� [mailto:ville.syrjala@linux.intel.com] 
Sent: Monday, 11 December, 2017 11:03 AM
To: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>
Cc: intel-gfx@lists.freedesktop.org; stable@vger.kernel.org; Runyan, Arthur J <arthur.j.runyan@intel.com>
Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915: Disable DC states around GMBUS on GLK

On Mon, Dec 11, 2017 at 06:41:05PM +0000, Pandiyan, Dhinakaran wrote:
> On Fri, 2017-12-08 at 23:37 +0200, Ville Syrjala wrote:
> > From: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> > 
> > Prevent the DMC from destroying GMBUS transfers on GLK. GMBUS
> > lives in PG1 so DC off is all we need.
> > 
> Just so that I understand this correctly. DMC is expected to take care
> of managing power for GMBUS transfers without the driver explicitly
> turning on/off the power well 1 but it isn't. Do you know if this is a
> DMC regression?

No idea. The docs don't seem to even mention DMC and GMBUS in the same
sentence. But since DP AUX needs DC off I don't see why GMBUS would
be all that different.

And with bit banging I would be somewhat surprised if DMC could
maintain the state of the pins while in DC5. Although I suppose it
might be possible that the hw automagically prevents DC5 when we're
driving any of the pins.

Art?

> 
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 96ab74f3d101..522e0a63090f 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -1792,6 +1792,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> >  	BIT_ULL(POWER_DOMAIN_GT_IRQ) |			\
> >  	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> >  	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> > +	BIT_ULL(POWER_DOMAIN_GMBUS) |			\
> >  	BIT_ULL(POWER_DOMAIN_INIT))
> >  
> >  #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\

-- 
Ville Syrj�l�
Intel OTC

Re: [PATCH 1/4] drm/i915: Disable DC states around GMBUS on GLK

[Runyan, Arthur J]

You're right.  DC5 could disrupt GMBUS.  We forgot to add a note on GMBUS when it got moved under DMC domain in GLK and BXT/APL.  I'll take care of that.

-----Original Message-----
From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] 
Sent: Monday, 11 December, 2017 11:03 AM
To: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>
Cc: intel-gfx@lists.freedesktop.org; stable@vger.kernel.org; Runyan, Arthur J <arthur.j.runyan@intel.com>
Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915: Disable DC states around GMBUS on GLK

On Mon, Dec 11, 2017 at 06:41:05PM +0000, Pandiyan, Dhinakaran wrote:
> On Fri, 2017-12-08 at 23:37 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Prevent the DMC from destroying GMBUS transfers on GLK. GMBUS
> > lives in PG1 so DC off is all we need.
> > 
> Just so that I understand this correctly. DMC is expected to take care
> of managing power for GMBUS transfers without the driver explicitly
> turning on/off the power well 1 but it isn't. Do you know if this is a
> DMC regression?

No idea. The docs don't seem to even mention DMC and GMBUS in the same
sentence. But since DP AUX needs DC off I don't see why GMBUS would
be all that different.

And with bit banging I would be somewhat surprised if DMC could
maintain the state of the pins while in DC5. Although I suppose it
might be possible that the hw automagically prevents DC5 when we're
driving any of the pins.

Art?

> 
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 96ab74f3d101..522e0a63090f 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -1792,6 +1792,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> >  	BIT_ULL(POWER_DOMAIN_GT_IRQ) |			\
> >  	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> >  	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> > +	BIT_ULL(POWER_DOMAIN_GMBUS) |			\
> >  	BIT_ULL(POWER_DOMAIN_INIT))
> >  
> >  #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 1/4] drm/i915: Disable DC states around GMBUS on GLK

[Pandiyan, Dhinakaran]

On Mon, 2017-12-11 at 23:32 +0000, Runyan, Arthur J wrote:
> You're right.  DC5 could disrupt GMBUS.  We forgot to add a note on GMBUS when it got moved under DMC domain in GLK and BXT/APL.  I'll take care of that.
> 

In light of this confirmation, patches 1 and 2 are
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>


> -----Original Message-----
> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] 
> Sent: Monday, 11 December, 2017 11:03 AM
> To: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; stable@vger.kernel.org; Runyan, Arthur J <arthur.j.runyan@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915: Disable DC states around GMBUS on GLK
> 
> On Mon, Dec 11, 2017 at 06:41:05PM +0000, Pandiyan, Dhinakaran wrote:
> > On Fri, 2017-12-08 at 23:37 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Prevent the DMC from destroying GMBUS transfers on GLK. GMBUS
> > > lives in PG1 so DC off is all we need.
> > > 
> > Just so that I understand this correctly. DMC is expected to take care
> > of managing power for GMBUS transfers without the driver explicitly
> > turning on/off the power well 1 but it isn't. Do you know if this is a
> > DMC regression?
> 
> No idea. The docs don't seem to even mention DMC and GMBUS in the same
> sentence. But since DP AUX needs DC off I don't see why GMBUS would
> be all that different.
> 
> And with bit banging I would be somewhat surprised if DMC could
> maintain the state of the pins while in DC5. Although I suppose it
> might be possible that the hw automagically prevents DC5 when we're
> driving any of the pins.
> 
> Art?
> 
> > 
> > > Cc: stable@vger.kernel.org
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 96ab74f3d101..522e0a63090f 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -1792,6 +1792,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > >  	BIT_ULL(POWER_DOMAIN_GT_IRQ) |			\
> > >  	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> > >  	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> > > +	BIT_ULL(POWER_DOMAIN_GMBUS) |			\
> > >  	BIT_ULL(POWER_DOMAIN_INIT))
> > >  
> > >  #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\
> 

[PATCH v2 4/4] drm/i915: Disable GMBUS clock gating around GMBUS transfers on gen9+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Gen9+ need to disable GMBUS clock gating when doing multi part
transfers. Otherwise clock gating will kick in when GMBUS is in
the WAIT state and presumably that will corrupt the transfer.
This is documented as Display WA #0868.

Apparently older hardware doesn't allow clock gating in the WAIT
state and thus are unaffected by this problem.

v2: Limit the PCH w/a to gen9 and gen10 only (DK)
    Actually change it to check the PCH type instead since
    it's the PCH that actually contains the GMBUS hardware

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> #v1
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 ++++
 drivers/gpu/drm/i915/intel_i2c.c | 40 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb05849eabab..41285bec8fc0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3859,6 +3859,9 @@ enum {
 #define   PWM2_GATING_DIS		(1 << 14)
 #define   PWM1_GATING_DIS		(1 << 13)
 
+#define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
+#define   BXT_GMBUS_GATING_DIS		(1 << 14)
+
 #define _CLKGATE_DIS_PSL_A		0x46520
 #define _CLKGATE_DIS_PSL_B		0x46524
 #define _CLKGATE_DIS_PSL_C		0x46528
@@ -7557,6 +7560,7 @@ enum {
 #define FDI_RX_CHICKEN(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
 
 #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
+#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1<<31)
 #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
 #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index a8c08994f505..ef9f91a0b0c9 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -142,6 +142,32 @@ static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
 	I915_WRITE(DSPCLK_GATE_D, val);
 }
 
+static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
+				   bool enable)
+{
+	u32 val;
+
+	val = I915_READ(SOUTH_DSPCLK_GATE_D);
+	if (!enable)
+		val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
+	else
+		val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
+	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
+}
+
+static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
+				   bool enable)
+{
+	u32 val;
+
+	val = I915_READ(GEN9_CLKGATE_DIS_4);
+	if (!enable)
+		val |= BXT_GMBUS_GATING_DIS;
+	else
+		val &= ~BXT_GMBUS_GATING_DIS;
+	I915_WRITE(GEN9_CLKGATE_DIS_4, val);
+}
+
 static u32 get_reserved(struct intel_gmbus *bus)
 {
 	struct drm_i915_private *dev_priv = bus->dev_priv;
@@ -484,6 +510,13 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
 	int i = 0, inc, try = 0;
 	int ret = 0;
 
+	/* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
+	if (IS_GEN9_LP(dev_priv))
+		bxt_gmbus_clock_gating(dev_priv, false);
+	else if (HAS_PCH_SPT(dev_priv) ||
+		 HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
+		pch_gmbus_clock_gating(dev_priv, false);
+
 retry:
 	I915_WRITE_FW(GMBUS0, bus->reg0);
 
@@ -585,6 +618,13 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
 	ret = -EAGAIN;
 
 out:
+	/* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
+	if (IS_GEN9_LP(dev_priv))
+		bxt_gmbus_clock_gating(dev_priv, true);
+	else if (HAS_PCH_SPT(dev_priv) ||
+		 HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
+		pch_gmbus_clock_gating(dev_priv, true);
+
 	return ret;
 }
 
-- 
2.13.6

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✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Disable DC states around GMBUS on GLK (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Disable DC states around GMBUS on GLK (rev2)
URL   : https://patchwork.freedesktop.org/series/35117/
State : success

== Summary ==

Series 35117v2 series starting with [1/4] drm/i915: Disable DC states around GMBUS on GLK
https://patchwork.freedesktop.org/api/1.0/series/35117/revisions/2/mbox/

Test debugfs_test:
        Subgroup read_all_entries:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713
Test kms_psr_sink_crc:
        Subgroup psr_basic:
                pass       -> DMESG-WARN (fi-skl-6700hq) fdo#101144

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:434s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:437s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:384s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:496s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:275s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:489s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:497s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:476s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:467s
fi-elk-e7500     total:224  pass:163  dwarn:15  dfail:0   fail:0   skip:45 
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:259s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:533s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:404s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:415s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:476s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:425s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:473s
fi-kbl-7560u     total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  time:523s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:464s
fi-kbl-r         total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  time:529s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:587s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:453s
fi-skl-6600u     total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  time:537s
fi-skl-6700hq    total:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  time:554s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:505s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:510s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:444s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:552s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:409s
Blacklisted hosts:
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:584s
fi-cnl-y         total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:25 
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:483s

c0a64101df89fe312cb41d27e184555400d0e3b9 drm-tip: 2017y-12m-21d-18h-02m-56s UTC integration manifest
be940a4d2230 drm/i915: Disable GMBUS clock gating around GMBUS transfers on gen9+
50ebca98ff7b drm/i915: Clean up the PNV bit banging vs. GMBUS clock gating w/a
6f5f07314fb1 drm/i915: No need to power up PG2 for GMBUS on BXT
e88a2ff0d2d5 drm/i915: Disable DC states around GMBUS on GLK

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7559/issues.html
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✗ Fi.CI.IGT: warning for series starting with [1/4] drm/i915: Disable DC states around GMBUS on GLK (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Disable DC states around GMBUS on GLK (rev2)
URL   : https://patchwork.freedesktop.org/series/35117/
State : warning

== Summary ==

Test drv_suspend:
        Subgroup sysfs-reader:
                skip       -> PASS       (shard-hsw)
        Subgroup fence-restore-tiled2untiled:
                skip       -> PASS       (shard-snb)
                skip       -> PASS       (shard-hsw)
Test kms_busy:
        Subgroup basic-modeset-a:
                pass       -> DMESG-WARN (shard-hsw)
        Subgroup basic-modeset-b:
                pass       -> SKIP       (shard-hsw)
Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-offscren-pri-indfb-draw-pwrite:
                pass       -> SKIP       (shard-hsw) fdo#101623 +1
Test gem_eio:
        Subgroup in-flight:
                pass       -> DMESG-WARN (shard-snb) fdo#104058
Test pm_rpm:
        Subgroup system-suspend:
                skip       -> PASS       (shard-hsw) fdo#103375

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-hsw        total:2640 pass:1499 dwarn:2   dfail:0   fail:10  skip:1128 time:9185s
shard-snb        total:2712 pass:1308 dwarn:2   dfail:0   fail:11  skip:1391 time:8077s
Blacklisted hosts:
shard-apl        total:2712 pass:1685 dwarn:1   dfail:1   fail:24  skip:1001 time:13722s
shard-kbl        total:2653 pass:1757 dwarn:8   dfail:0   fail:22  skip:865 time:10631s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7559/shards.html
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Re: [PATCH v2 4/4] drm/i915: Disable GMBUS clock gating around GMBUS transfers on gen9+

[Jani Nikula]

On Thu, 21 Dec 2017, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Gen9+ need to disable GMBUS clock gating when doing multi part
> transfers. Otherwise clock gating will kick in when GMBUS is in
> the WAIT state and presumably that will corrupt the transfer.
> This is documented as Display WA #0868.
>
> Apparently older hardware doesn't allow clock gating in the WAIT
> state and thus are unaffected by this problem.
>
> v2: Limit the PCH w/a to gen9 and gen10 only (DK)
>     Actually change it to check the PCH type instead since
>     it's the PCH that actually contains the GMBUS hardware
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> #v1

Why wasn't this cc: stable? Should it have been?

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  4 ++++
>  drivers/gpu/drm/i915/intel_i2c.c | 40 ++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 44 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb05849eabab..41285bec8fc0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3859,6 +3859,9 @@ enum {
>  #define   PWM2_GATING_DIS		(1 << 14)
>  #define   PWM1_GATING_DIS		(1 << 13)
>  
> +#define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
> +#define   BXT_GMBUS_GATING_DIS		(1 << 14)
> +
>  #define _CLKGATE_DIS_PSL_A		0x46520
>  #define _CLKGATE_DIS_PSL_B		0x46524
>  #define _CLKGATE_DIS_PSL_C		0x46528
> @@ -7557,6 +7560,7 @@ enum {
>  #define FDI_RX_CHICKEN(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
>  
>  #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
> +#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1<<31)
>  #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
>  #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
>  #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index a8c08994f505..ef9f91a0b0c9 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -142,6 +142,32 @@ static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
>  	I915_WRITE(DSPCLK_GATE_D, val);
>  }
>  
> +static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
> +				   bool enable)
> +{
> +	u32 val;
> +
> +	val = I915_READ(SOUTH_DSPCLK_GATE_D);
> +	if (!enable)
> +		val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
> +	else
> +		val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
> +	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> +}
> +
> +static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
> +				   bool enable)
> +{
> +	u32 val;
> +
> +	val = I915_READ(GEN9_CLKGATE_DIS_4);
> +	if (!enable)
> +		val |= BXT_GMBUS_GATING_DIS;
> +	else
> +		val &= ~BXT_GMBUS_GATING_DIS;
> +	I915_WRITE(GEN9_CLKGATE_DIS_4, val);
> +}
> +
>  static u32 get_reserved(struct intel_gmbus *bus)
>  {
>  	struct drm_i915_private *dev_priv = bus->dev_priv;
> @@ -484,6 +510,13 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
>  	int i = 0, inc, try = 0;
>  	int ret = 0;
>  
> +	/* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
> +	if (IS_GEN9_LP(dev_priv))
> +		bxt_gmbus_clock_gating(dev_priv, false);
> +	else if (HAS_PCH_SPT(dev_priv) ||
> +		 HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
> +		pch_gmbus_clock_gating(dev_priv, false);
> +
>  retry:
>  	I915_WRITE_FW(GMBUS0, bus->reg0);
>  
> @@ -585,6 +618,13 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
>  	ret = -EAGAIN;
>  
>  out:
> +	/* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
> +	if (IS_GEN9_LP(dev_priv))
> +		bxt_gmbus_clock_gating(dev_priv, true);
> +	else if (HAS_PCH_SPT(dev_priv) ||
> +		 HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
> +		pch_gmbus_clock_gating(dev_priv, true);
> +
>  	return ret;
>  }

-- 
Jani Nikula, Intel Open Source Technology Center
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