[PATCH v5 00/16] OMAP2+ OneNAND driver update

[PATCH v5 00/16] OMAP2+ OneNAND driver update

[Ladislav Michl]

this patch serie updates OMAP2+ OneNAND driver to the present times, making
it fully DT configurable, using libgpio and dmaengine apis - those are
optional, driver will work without them.

Please note that unlike previous driver version, which basically ignored
DT specified timings, this one relies on it, so it is important to get
it right in your DT (dumping it from previous kernel version).

In case synchronous timings is requested, it is okay to specify timings
for the slowest chip ever used for you board as it is evetually optimized
after chip probe.

Original driver used DMA only if user specified INT gpio in platform
data, now DMA is used unconditionally and PIO mode is used as fallback.

In case anyone wants to give it a try, few DT related changes are needed:
- onenand node needs 'ti,omap2-onenand' compatible (for mailine boards this is
  done in patch 2)
- to use INT pin, int-gpios needs to be specified (for n900 and n8x0 this is
  done in patch 16, however patch lacks pinmux configuration.

Most notable changes from v3:
- added dmaengine patches by Peter Ujfalusi
- added dt bindings documentation
- added cleanup patches
- DMA enabled by default

Most notable changes from v4:
- collected tags
- used INT pin name properly
- hopefully all comments taken into account

Also note that driver will fail probe OneNAND chip after patch 13 and start
working again after patch 14.

Testing and benchmarking very welcome.

Depends on "memory: omap-gpmc: Make 'bank-width' property optional"
https://patchwork.kernel.org/patch/10043259/

Ladislav Michl (14):
  dt-bindings: mtd: gpmc-onenand: Update properties description
  ARM: dts: OMAP2+: Add compatible property to onenand node
  ARM: dts: omap3-igep: Update onenand node timings
  mtd: onenand: omap2: Remove regulator support
  mtd: onenand: omap2: Remove skip initial unlocking support
  mtd: onenand: omap2: Remove partitioning support from platform data
  mtd: onenand: omap2: Account waiting time as waiting on IO
  mtd: onenand: omap2: Unify OMAP2 and OMAP3 DMA implementation
  mtd: onenand: omap2: Do not make delay for GPIO OMAP3 specific
  mtd: onenand: omap2: Decouple DMA enabling from INT pin availability
  memory: omap-gpmc: Refactor OneNAND support
  mtd: onenand: omap2: Configure driver from DT
  ARM: OMAP2+: Remove gpmc-onenand
  ARM: dts: Nokia: Use OneNAND INT pin

Peter Ujfalusi (2):
  mtd: onenand: omap2: Simplify the DMA setup for various paths
  mtd: onenand: omap2: Convert to use dmaengine for memcpy

 .../devicetree/bindings/mtd/gpmc-onenand.txt       |   6 +-
 arch/arm/boot/dts/omap2420-n8x0-common.dtsi        |   5 +-
 arch/arm/boot/dts/omap3-igep.dtsi                  |  30 +-
 arch/arm/boot/dts/omap3-n900.dts                   |   3 +-
 arch/arm/boot/dts/omap3-n950-n9.dtsi               |   1 +
 arch/arm/boot/dts/omap3430-sdp.dts                 |   1 +
 arch/arm/mach-omap2/Makefile                       |   3 -
 arch/arm/mach-omap2/gpmc-onenand.c                 | 409 ---------------
 drivers/memory/omap-gpmc.c                         | 158 ++++--
 drivers/mtd/onenand/Kconfig                        |   3 +-
 drivers/mtd/onenand/omap2.c                        | 576 ++++++++-------------
 include/linux/omap-gpmc.h                          |  28 +
 include/linux/platform_data/mtd-onenand-omap2.h    |  34 --
 13 files changed, 387 insertions(+), 870 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/gpmc-onenand.c
 delete mode 100644 include/linux/platform_data/mtd-onenand-omap2.h

-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 00/16] OMAP2+ OneNAND driver update

[Ladislav Michl]

this patch serie updates OMAP2+ OneNAND driver to the present times, making
it fully DT configurable, using libgpio and dmaengine apis - those are
optional, driver will work without them.

Please note that unlike previous driver version, which basically ignored
DT specified timings, this one relies on it, so it is important to get
it right in your DT (dumping it from previous kernel version).

In case synchronous timings is requested, it is okay to specify timings
for the slowest chip ever used for you board as it is evetually optimized
after chip probe.

Original driver used DMA only if user specified INT gpio in platform
data, now DMA is used unconditionally and PIO mode is used as fallback.

In case anyone wants to give it a try, few DT related changes are needed:
- onenand node needs 'ti,omap2-onenand' compatible (for mailine boards this is
  done in patch 2)
- to use INT pin, int-gpios needs to be specified (for n900 and n8x0 this is
  done in patch 16, however patch lacks pinmux configuration.

Most notable changes from v3:
- added dmaengine patches by Peter Ujfalusi
- added dt bindings documentation
- added cleanup patches
- DMA enabled by default

Most notable changes from v4:
- collected tags
- used INT pin name properly
- hopefully all comments taken into account

Also note that driver will fail probe OneNAND chip after patch 13 and start
working again after patch 14.

Testing and benchmarking very welcome.

Depends on "memory: omap-gpmc: Make 'bank-width' property optional"
https://patchwork.kernel.org/patch/10043259/

Ladislav Michl (14):
  dt-bindings: mtd: gpmc-onenand: Update properties description
  ARM: dts: OMAP2+: Add compatible property to onenand node
  ARM: dts: omap3-igep: Update onenand node timings
  mtd: onenand: omap2: Remove regulator support
  mtd: onenand: omap2: Remove skip initial unlocking support
  mtd: onenand: omap2: Remove partitioning support from platform data
  mtd: onenand: omap2: Account waiting time as waiting on IO
  mtd: onenand: omap2: Unify OMAP2 and OMAP3 DMA implementation
  mtd: onenand: omap2: Do not make delay for GPIO OMAP3 specific
  mtd: onenand: omap2: Decouple DMA enabling from INT pin availability
  memory: omap-gpmc: Refactor OneNAND support
  mtd: onenand: omap2: Configure driver from DT
  ARM: OMAP2+: Remove gpmc-onenand
  ARM: dts: Nokia: Use OneNAND INT pin

Peter Ujfalusi (2):
  mtd: onenand: omap2: Simplify the DMA setup for various paths
  mtd: onenand: omap2: Convert to use dmaengine for memcpy

 .../devicetree/bindings/mtd/gpmc-onenand.txt       |   6 +-
 arch/arm/boot/dts/omap2420-n8x0-common.dtsi        |   5 +-
 arch/arm/boot/dts/omap3-igep.dtsi                  |  30 +-
 arch/arm/boot/dts/omap3-n900.dts                   |   3 +-
 arch/arm/boot/dts/omap3-n950-n9.dtsi               |   1 +
 arch/arm/boot/dts/omap3430-sdp.dts                 |   1 +
 arch/arm/mach-omap2/Makefile                       |   3 -
 arch/arm/mach-omap2/gpmc-onenand.c                 | 409 ---------------
 drivers/memory/omap-gpmc.c                         | 158 ++++--
 drivers/mtd/onenand/Kconfig                        |   3 +-
 drivers/mtd/onenand/omap2.c                        | 576 ++++++++-------------
 include/linux/omap-gpmc.h                          |  28 +
 include/linux/platform_data/mtd-onenand-omap2.h    |  34 --
 13 files changed, 387 insertions(+), 870 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/gpmc-onenand.c
 delete mode 100644 include/linux/platform_data/mtd-onenand-omap2.h

-- 
2.11.0

[PATCH v5 01/16] dt-bindings: mtd: gpmc-onenand: Update properties description

[Ladislav Michl]

Compatible property is required for OMAP2+ mtd driver. Also
add INT pin gpio description and delete unused dma-channel
property.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
---

Changes in v5:
- renamed R/B pin to INT pin

Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 Documentation/devicetree/bindings/mtd/gpmc-onenand.txt | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
index b6e8bfd024f4..e9f01a963a0a 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
@@ -9,13 +9,14 @@ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
 
 Required properties:
 
+ - compatible:		"ti,omap2-onenand"
  - reg:			The CS line the peripheral is connected to
- - gpmc,device-width	Width of the ONENAND device connected to the GPMC
+ - gpmc,device-width:	Width of the ONENAND device connected to the GPMC
 			in bytes. Must be 1 or 2.
 
 Optional properties:
 
- - dma-channel:		DMA Channel index
+ - int-gpios:		GPIO specifier for the INT pin.
 
 For inline partition table parsing (optional):
 
@@ -35,6 +36,7 @@ Example for an OMAP3430 board:
 		#size-cells = <1>;
 
 		onenand@0 {
+			compatible = "ti,omap2-onenand";
 			reg = <0 0 0>; /* CS0, offset 0 */
 			gpmc,device-width = <2>;
 
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 01/16] dt-bindings: mtd: gpmc-onenand: Update properties description

[Ladislav Michl]

Compatible property is required for OMAP2+ mtd driver. Also
add INT pin gpio description and delete unused dma-channel
property.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
---

Changes in v5:
- renamed R/B pin to INT pin

Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 Documentation/devicetree/bindings/mtd/gpmc-onenand.txt | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
index b6e8bfd024f4..e9f01a963a0a 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
@@ -9,13 +9,14 @@ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
 
 Required properties:
 
+ - compatible:		"ti,omap2-onenand"
  - reg:			The CS line the peripheral is connected to
- - gpmc,device-width	Width of the ONENAND device connected to the GPMC
+ - gpmc,device-width:	Width of the ONENAND device connected to the GPMC
 			in bytes. Must be 1 or 2.
 
 Optional properties:
 
- - dma-channel:		DMA Channel index
+ - int-gpios:		GPIO specifier for the INT pin.
 
 For inline partition table parsing (optional):
 
@@ -35,6 +36,7 @@ Example for an OMAP3430 board:
 		#size-cells = <1>;
 
 		onenand@0 {
+			compatible = "ti,omap2-onenand";
 			reg = <0 0 0>; /* CS0, offset 0 */
 			gpmc,device-width = <2>;
 
-- 
2.11.0

[PATCH v5 02/16] ARM: dts: OMAP2+: Add compatible property to onenand node

[Ladislav Michl]

OMAP onenand nodes are missing compatible property, add it.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/omap2420-n8x0-common.dtsi | 1 +
 arch/arm/boot/dts/omap3-n900.dts            | 1 +
 arch/arm/boot/dts/omap3-n950-n9.dtsi        | 1 +
 arch/arm/boot/dts/omap3430-sdp.dts          | 1 +
 4 files changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
index 1de80c7886ab..843f6a2f5e29 100644
--- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
+++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
@@ -48,6 +48,7 @@
 	onenand@0,0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
+		compatible = "ti,omap2-onenand";
 		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
 
 		gpmc,sync-read;
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 4acd32a1c4ef..aa5b1a439564 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -838,6 +838,7 @@
 	onenand@0,0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
+		compatible = "ti,omap2-onenand";
 		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
 
 		gpmc,sync-read;
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 1b0bd72945f2..cb3c7b2fce52 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -367,6 +367,7 @@
 	onenand@0,0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
+		compatible = "ti,omap2-onenand";
 		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
 
 		gpmc,sync-read;
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index d50a105c9dc6..ed65795ccc62 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -155,6 +155,7 @@
 		linux,mtd-name= "samsung,kfm2g16q2m-deb8";
 		#address-cells = <1>;
 		#size-cells = <1>;
+		compatible = "ti,omap2-onenand";
 		reg = <2 0 0x20000>;	/* CS2, offset 0, IO size 4 */
 
 		gpmc,device-width = <2>;
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 02/16] ARM: dts: OMAP2+: Add compatible property to onenand node

[Ladislav Michl]

OMAP onenand nodes are missing compatible property, add it.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/omap2420-n8x0-common.dtsi | 1 +
 arch/arm/boot/dts/omap3-n900.dts            | 1 +
 arch/arm/boot/dts/omap3-n950-n9.dtsi        | 1 +
 arch/arm/boot/dts/omap3430-sdp.dts          | 1 +
 4 files changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
index 1de80c7886ab..843f6a2f5e29 100644
--- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
+++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
@@ -48,6 +48,7 @@
 	onenand@0,0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
+		compatible = "ti,omap2-onenand";
 		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
 
 		gpmc,sync-read;
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 4acd32a1c4ef..aa5b1a439564 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -838,6 +838,7 @@
 	onenand@0,0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
+		compatible = "ti,omap2-onenand";
 		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
 
 		gpmc,sync-read;
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 1b0bd72945f2..cb3c7b2fce52 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -367,6 +367,7 @@
 	onenand@0,0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
+		compatible = "ti,omap2-onenand";
 		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
 
 		gpmc,sync-read;
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index d50a105c9dc6..ed65795ccc62 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -155,6 +155,7 @@
 		linux,mtd-name= "samsung,kfm2g16q2m-deb8";
 		#address-cells = <1>;
 		#size-cells = <1>;
+		compatible = "ti,omap2-onenand";
 		reg = <2 0 0x20000>;	/* CS2, offset 0, IO size 4 */
 
 		gpmc,device-width = <2>;
-- 
2.11.0

[PATCH v5 03/16] ARM: dts: omap3-igep: Update onenand node timings

[Ladislav Michl]

Update node timings to be compatible with actual chip used -
gpmc_cs_show_timings utilized to dump values.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/omap3-igep.dtsi | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index 4929ba1cb9d3..1e4b8d5c7572 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -144,32 +144,32 @@
 		gpmc,sync-read;
 		gpmc,sync-write;
 		gpmc,burst-length = <16>;
-		gpmc,burst-read;
 		gpmc,burst-wrap;
+		gpmc,burst-read;
 		gpmc,burst-write;
 		gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
 		gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
 		gpmc,cs-on-ns = <0>;
-		gpmc,cs-rd-off-ns = <87>;
-		gpmc,cs-wr-off-ns = <87>;
+		gpmc,cs-rd-off-ns = <96>;
+		gpmc,cs-wr-off-ns = <96>;
 		gpmc,adv-on-ns = <0>;
-		gpmc,adv-rd-off-ns = <10>;
-		gpmc,adv-wr-off-ns = <10>;
-		gpmc,oe-on-ns = <15>;
-		gpmc,oe-off-ns = <87>;
+		gpmc,adv-rd-off-ns = <12>;
+		gpmc,adv-wr-off-ns = <12>;
+		gpmc,oe-on-ns = <18>;
+		gpmc,oe-off-ns = <96>;
 		gpmc,we-on-ns = <0>;
-		gpmc,we-off-ns = <87>;
-		gpmc,rd-cycle-ns = <112>;
-		gpmc,wr-cycle-ns = <112>;
-		gpmc,access-ns = <81>;
-		gpmc,page-burst-access-ns = <15>;
+		gpmc,we-off-ns = <96>;
+		gpmc,rd-cycle-ns = <114>;
+		gpmc,wr-cycle-ns = <114>;
+		gpmc,access-ns = <90>;
+		gpmc,page-burst-access-ns = <12>;
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <0>;
 		gpmc,wait-monitoring-ns = <0>;
-		gpmc,clk-activation-ns = <5>;
+		gpmc,clk-activation-ns = <6>;
 		gpmc,wr-data-mux-bus-ns = <30>;
-		gpmc,wr-access-ns = <81>;
-		gpmc,sync-clk-ps = <15000>;
+		gpmc,wr-access-ns = <90>;
+		gpmc,sync-clk-ps = <12000>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 03/16] ARM: dts: omap3-igep: Update onenand node timings

[Ladislav Michl]

Update node timings to be compatible with actual chip used -
gpmc_cs_show_timings utilized to dump values.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/omap3-igep.dtsi | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index 4929ba1cb9d3..1e4b8d5c7572 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -144,32 +144,32 @@
 		gpmc,sync-read;
 		gpmc,sync-write;
 		gpmc,burst-length = <16>;
-		gpmc,burst-read;
 		gpmc,burst-wrap;
+		gpmc,burst-read;
 		gpmc,burst-write;
 		gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
 		gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
 		gpmc,cs-on-ns = <0>;
-		gpmc,cs-rd-off-ns = <87>;
-		gpmc,cs-wr-off-ns = <87>;
+		gpmc,cs-rd-off-ns = <96>;
+		gpmc,cs-wr-off-ns = <96>;
 		gpmc,adv-on-ns = <0>;
-		gpmc,adv-rd-off-ns = <10>;
-		gpmc,adv-wr-off-ns = <10>;
-		gpmc,oe-on-ns = <15>;
-		gpmc,oe-off-ns = <87>;
+		gpmc,adv-rd-off-ns = <12>;
+		gpmc,adv-wr-off-ns = <12>;
+		gpmc,oe-on-ns = <18>;
+		gpmc,oe-off-ns = <96>;
 		gpmc,we-on-ns = <0>;
-		gpmc,we-off-ns = <87>;
-		gpmc,rd-cycle-ns = <112>;
-		gpmc,wr-cycle-ns = <112>;
-		gpmc,access-ns = <81>;
-		gpmc,page-burst-access-ns = <15>;
+		gpmc,we-off-ns = <96>;
+		gpmc,rd-cycle-ns = <114>;
+		gpmc,wr-cycle-ns = <114>;
+		gpmc,access-ns = <90>;
+		gpmc,page-burst-access-ns = <12>;
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <0>;
 		gpmc,wait-monitoring-ns = <0>;
-		gpmc,clk-activation-ns = <5>;
+		gpmc,clk-activation-ns = <6>;
 		gpmc,wr-data-mux-bus-ns = <30>;
-		gpmc,wr-access-ns = <81>;
-		gpmc,sync-clk-ps = <15000>;
+		gpmc,wr-access-ns = <90>;
+		gpmc,sync-clk-ps = <12000>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
2.11.0

[PATCH v5 04/16] mtd: onenand: omap2: Remove regulator support

[Ladislav Michl]

As no platform data user sets regulator_can_sleep, regulator code is
no-op and can be deleted.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- new patch

 drivers/mtd/onenand/omap2.c | 42 +-----------------------------------------
 1 file changed, 1 insertion(+), 41 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 24a1388d3031..a03e1fe4aa48 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -34,7 +34,6 @@
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
 #include <linux/slab.h>
-#include <linux/regulator/consumer.h>
 #include <linux/gpio.h>
 
 #include <asm/mach/flash.h>
@@ -59,7 +58,6 @@ struct omap2_onenand {
 	int dma_channel;
 	int freq;
 	int (*setup)(void __iomem *base, int *freq_ptr);
-	struct regulator *regulator;
 	u8 flags;
 };
 
@@ -583,30 +581,6 @@ static void omap2_onenand_shutdown(struct platform_device *pdev)
 	memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
 }
 
-static int omap2_onenand_enable(struct mtd_info *mtd)
-{
-	int ret;
-	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
-
-	ret = regulator_enable(c->regulator);
-	if (ret != 0)
-		dev_err(&c->pdev->dev, "can't enable regulator\n");
-
-	return ret;
-}
-
-static int omap2_onenand_disable(struct mtd_info *mtd)
-{
-	int ret;
-	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
-
-	ret = regulator_disable(c->regulator);
-	if (ret != 0)
-		dev_err(&c->pdev->dev, "can't disable regulator\n");
-
-	return ret;
-}
-
 static int omap2_onenand_probe(struct platform_device *pdev)
 {
 	struct omap_onenand_platform_data *pdata;
@@ -726,22 +700,11 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 		}
 	}
 
-	if (pdata->regulator_can_sleep) {
-		c->regulator = regulator_get(&pdev->dev, "vonenand");
-		if (IS_ERR(c->regulator)) {
-			dev_err(&pdev->dev,  "Failed to get regulator\n");
-			r = PTR_ERR(c->regulator);
-			goto err_release_dma;
-		}
-		c->onenand.enable = omap2_onenand_enable;
-		c->onenand.disable = omap2_onenand_disable;
-	}
-
 	if (pdata->skip_initial_unlocking)
 		this->options |= ONENAND_SKIP_INITIAL_UNLOCKING;
 
 	if ((r = onenand_scan(&c->mtd, 1)) < 0)
-		goto err_release_regulator;
+		goto err_release_dma;
 
 	r = mtd_device_register(&c->mtd, pdata ? pdata->parts : NULL,
 				pdata ? pdata->nr_parts : 0);
@@ -754,8 +717,6 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 
 err_release_onenand:
 	onenand_release(&c->mtd);
-err_release_regulator:
-	regulator_put(c->regulator);
 err_release_dma:
 	if (c->dma_channel != -1)
 		omap_free_dma(c->dma_channel);
@@ -779,7 +740,6 @@ static int omap2_onenand_remove(struct platform_device *pdev)
 	struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 
 	onenand_release(&c->mtd);
-	regulator_put(c->regulator);
 	if (c->dma_channel != -1)
 		omap_free_dma(c->dma_channel);
 	omap2_onenand_shutdown(pdev);
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 04/16] mtd: onenand: omap2: Remove regulator support

[Ladislav Michl]

As no platform data user sets regulator_can_sleep, regulator code is
no-op and can be deleted.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- new patch

 drivers/mtd/onenand/omap2.c | 42 +-----------------------------------------
 1 file changed, 1 insertion(+), 41 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 24a1388d3031..a03e1fe4aa48 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -34,7 +34,6 @@
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
 #include <linux/slab.h>
-#include <linux/regulator/consumer.h>
 #include <linux/gpio.h>
 
 #include <asm/mach/flash.h>
@@ -59,7 +58,6 @@ struct omap2_onenand {
 	int dma_channel;
 	int freq;
 	int (*setup)(void __iomem *base, int *freq_ptr);
-	struct regulator *regulator;
 	u8 flags;
 };
 
@@ -583,30 +581,6 @@ static void omap2_onenand_shutdown(struct platform_device *pdev)
 	memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
 }
 
-static int omap2_onenand_enable(struct mtd_info *mtd)
-{
-	int ret;
-	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
-
-	ret = regulator_enable(c->regulator);
-	if (ret != 0)
-		dev_err(&c->pdev->dev, "can't enable regulator\n");
-
-	return ret;
-}
-
-static int omap2_onenand_disable(struct mtd_info *mtd)
-{
-	int ret;
-	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
-
-	ret = regulator_disable(c->regulator);
-	if (ret != 0)
-		dev_err(&c->pdev->dev, "can't disable regulator\n");
-
-	return ret;
-}
-
 static int omap2_onenand_probe(struct platform_device *pdev)
 {
 	struct omap_onenand_platform_data *pdata;
@@ -726,22 +700,11 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 		}
 	}
 
-	if (pdata->regulator_can_sleep) {
-		c->regulator = regulator_get(&pdev->dev, "vonenand");
-		if (IS_ERR(c->regulator)) {
-			dev_err(&pdev->dev,  "Failed to get regulator\n");
-			r = PTR_ERR(c->regulator);
-			goto err_release_dma;
-		}
-		c->onenand.enable = omap2_onenand_enable;
-		c->onenand.disable = omap2_onenand_disable;
-	}
-
 	if (pdata->skip_initial_unlocking)
 		this->options |= ONENAND_SKIP_INITIAL_UNLOCKING;
 
 	if ((r = onenand_scan(&c->mtd, 1)) < 0)
-		goto err_release_regulator;
+		goto err_release_dma;
 
 	r = mtd_device_register(&c->mtd, pdata ? pdata->parts : NULL,
 				pdata ? pdata->nr_parts : 0);
@@ -754,8 +717,6 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 
 err_release_onenand:
 	onenand_release(&c->mtd);
-err_release_regulator:
-	regulator_put(c->regulator);
 err_release_dma:
 	if (c->dma_channel != -1)
 		omap_free_dma(c->dma_channel);
@@ -779,7 +740,6 @@ static int omap2_onenand_remove(struct platform_device *pdev)
 	struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 
 	onenand_release(&c->mtd);
-	regulator_put(c->regulator);
 	if (c->dma_channel != -1)
 		omap_free_dma(c->dma_channel);
 	omap2_onenand_shutdown(pdev);
-- 
2.11.0

[PATCH v5 05/16] mtd: onenand: omap2: Remove skip initial unlocking support

[Ladislav Michl]

No platform data user sets skip_initial_unlocking, so remove test
for this field.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- new patch

 drivers/mtd/onenand/omap2.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index a03e1fe4aa48..93bd94337b35 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -700,9 +700,6 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 		}
 	}
 
-	if (pdata->skip_initial_unlocking)
-		this->options |= ONENAND_SKIP_INITIAL_UNLOCKING;
-
 	if ((r = onenand_scan(&c->mtd, 1)) < 0)
 		goto err_release_dma;
 
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 05/16] mtd: onenand: omap2: Remove skip initial unlocking support

[Ladislav Michl]

No platform data user sets skip_initial_unlocking, so remove test
for this field.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- new patch

 drivers/mtd/onenand/omap2.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index a03e1fe4aa48..93bd94337b35 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -700,9 +700,6 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 		}
 	}
 
-	if (pdata->skip_initial_unlocking)
-		this->options |= ONENAND_SKIP_INITIAL_UNLOCKING;
-
 	if ((r = onenand_scan(&c->mtd, 1)) < 0)
 		goto err_release_dma;
 
-- 
2.11.0

[PATCH v5 06/16] mtd: onenand: omap2: Remove partitioning support from platform data

[Ladislav Michl]

No platform data user setups partitioning information, so remove.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- new patch

 drivers/mtd/onenand/omap2.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 93bd94337b35..883993bbe40b 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -703,8 +703,7 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 	if ((r = onenand_scan(&c->mtd, 1)) < 0)
 		goto err_release_dma;
 
-	r = mtd_device_register(&c->mtd, pdata ? pdata->parts : NULL,
-				pdata ? pdata->nr_parts : 0);
+	r = mtd_device_register(&c->mtd, NULL, 0);
 	if (r)
 		goto err_release_onenand;
 
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 06/16] mtd: onenand: omap2: Remove partitioning support from platform data

[Ladislav Michl]

No platform data user setups partitioning information, so remove.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- new patch

 drivers/mtd/onenand/omap2.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 93bd94337b35..883993bbe40b 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -703,8 +703,7 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 	if ((r = onenand_scan(&c->mtd, 1)) < 0)
 		goto err_release_dma;
 
-	r = mtd_device_register(&c->mtd, pdata ? pdata->parts : NULL,
-				pdata ? pdata->nr_parts : 0);
+	r = mtd_device_register(&c->mtd, NULL, 0);
 	if (r)
 		goto err_release_onenand;
 
-- 
2.11.0

[PATCH v5 07/16] mtd: onenand: omap2: Account waiting time as waiting on IO

[Ladislav Michl]

Use wait_for_completion_io_timeout, which has an impact on how the
task is accounted in scheduling stats.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 drivers/mtd/onenand/omap2.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 883993bbe40b..0e7772e16d75 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -170,9 +170,8 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 		if (result == 0) {
 			int retry_cnt = 0;
 retry:
-			result = wait_for_completion_timeout(&c->irq_done,
-						    msecs_to_jiffies(20));
-			if (result == 0) {
+			if (!wait_for_completion_io_timeout(&c->irq_done,
+						msecs_to_jiffies(20))) {
 				/* Timeout after 20ms */
 				ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 				if (ctrl & ONENAND_CTRL_ONGO &&
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 07/16] mtd: onenand: omap2: Account waiting time as waiting on IO

[Ladislav Michl]

Use wait_for_completion_io_timeout, which has an impact on how the
task is accounted in scheduling stats.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 drivers/mtd/onenand/omap2.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 883993bbe40b..0e7772e16d75 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -170,9 +170,8 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 		if (result == 0) {
 			int retry_cnt = 0;
 retry:
-			result = wait_for_completion_timeout(&c->irq_done,
-						    msecs_to_jiffies(20));
-			if (result == 0) {
+			if (!wait_for_completion_io_timeout(&c->irq_done,
+						msecs_to_jiffies(20))) {
 				/* Timeout after 20ms */
 				ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 				if (ctrl & ONENAND_CTRL_ONGO &&
-- 
2.11.0

[PATCH v5 08/16] mtd: onenand: omap2: Simplify the DMA setup for various paths

[Ladislav Michl]

From: Peter Ujfalusi <peter.ujfalusi@ti.com>

We have 4 functions containing almost identical DMA setup code. Create one
function which can set up the DMA for both read and write and use this in
place for the setup code in the driver.
The new function will use wait_for_completion_io_timeout() and it will
figure out the best data_type to be used for the transfer instead of
hardwiring 32 or 16 bit data.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 drivers/mtd/onenand/omap2.c | 109 ++++++++++++++++++--------------------------
 1 file changed, 45 insertions(+), 64 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 0e7772e16d75..d22163271dc9 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -288,6 +288,33 @@ static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 	return 0;
 }
 
+static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
+					     dma_addr_t src, dma_addr_t dst,
+					     size_t count)
+{
+	int data_type = __ffs((src | dst | count));
+
+	if (data_type > OMAP_DMA_DATA_TYPE_S32)
+		data_type = OMAP_DMA_DATA_TYPE_S32;
+
+	omap_set_dma_transfer_params(c->dma_channel, data_type,
+				     count / BIT(data_type), 1, 0, 0, 0);
+	omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
+				src, 0, 0);
+	omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
+				 dst, 0, 0);
+
+	reinit_completion(&c->dma_done);
+	omap_start_dma(c->dma_channel);
+	if (!wait_for_completion_io_timeout(&c->dma_done,
+					    msecs_to_jiffies(20))) {
+		omap_stop_dma(c->dma_channel);
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
 #if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
 
 static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
@@ -298,10 +325,9 @@ static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
 	struct onenand_chip *this = mtd->priv;
 	dma_addr_t dma_src, dma_dst;
 	int bram_offset;
-	unsigned long timeout;
 	void *buf = (void *)buffer;
 	size_t xtra;
-	volatile unsigned *done;
+	int ret;
 
 	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 	if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
@@ -338,25 +364,10 @@ static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
 		goto out_copy;
 	}
 
-	omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
-				     count >> 2, 1, 0, 0, 0);
-	omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				dma_src, 0, 0);
-	omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				 dma_dst, 0, 0);
-
-	reinit_completion(&c->dma_done);
-	omap_start_dma(c->dma_channel);
-
-	timeout = jiffies + msecs_to_jiffies(20);
-	done = &c->dma_done.done;
-	while (time_before(jiffies, timeout))
-		if (*done)
-			break;
-
+	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 	dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 
-	if (!*done) {
+	if (ret) {
 		dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 		goto out_copy;
 	}
@@ -376,9 +387,8 @@ static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
 	struct onenand_chip *this = mtd->priv;
 	dma_addr_t dma_src, dma_dst;
 	int bram_offset;
-	unsigned long timeout;
 	void *buf = (void *)buffer;
-	volatile unsigned *done;
+	int ret;
 
 	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 	if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
@@ -409,25 +419,10 @@ static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
 		return -1;
 	}
 
-	omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
-				     count >> 2, 1, 0, 0, 0);
-	omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				dma_src, 0, 0);
-	omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				 dma_dst, 0, 0);
-
-	reinit_completion(&c->dma_done);
-	omap_start_dma(c->dma_channel);
-
-	timeout = jiffies + msecs_to_jiffies(20);
-	done = &c->dma_done.done;
-	while (time_before(jiffies, timeout))
-		if (*done)
-			break;
-
+	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 	dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
 
-	if (!*done) {
+	if (ret) {
 		dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 		goto out_copy;
 	}
@@ -466,7 +461,7 @@ static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 	struct onenand_chip *this = mtd->priv;
 	dma_addr_t dma_src, dma_dst;
-	int bram_offset;
+	int bram_offset, ret;
 
 	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 	/* DMA is not used.  Revisit PM requirements before enabling it. */
@@ -488,20 +483,13 @@ static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 		return -1;
 	}
 
-	omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
-				     count / 4, 1, 0, 0, 0);
-	omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				dma_src, 0, 0);
-	omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				 dma_dst, 0, 0);
-
-	reinit_completion(&c->dma_done);
-	omap_start_dma(c->dma_channel);
-	wait_for_completion(&c->dma_done);
-
+	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 	dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 
-	return 0;
+	if (ret)
+		dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
+
+	return ret;
 }
 
 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
@@ -511,7 +499,7 @@ static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 	struct onenand_chip *this = mtd->priv;
 	dma_addr_t dma_src, dma_dst;
-	int bram_offset;
+	int bram_offset, ret;
 
 	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 	/* DMA is not used.  Revisit PM requirements before enabling it. */
@@ -533,20 +521,13 @@ static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 		return -1;
 	}
 
-	omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S16,
-				     count / 2, 1, 0, 0, 0);
-	omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				dma_src, 0, 0);
-	omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				 dma_dst, 0, 0);
-
-	reinit_completion(&c->dma_done);
-	omap_start_dma(c->dma_channel);
-	wait_for_completion(&c->dma_done);
-
+	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 	dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
 
-	return 0;
+	if (ret)
+		dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
+
+	return ret;
 }
 
 #else
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 08/16] mtd: onenand: omap2: Simplify the DMA setup for various paths

[Ladislav Michl]

From: Peter Ujfalusi <peter.ujfalusi@ti.com>

We have 4 functions containing almost identical DMA setup code. Create one
function which can set up the DMA for both read and write and use this in
place for the setup code in the driver.
The new function will use wait_for_completion_io_timeout() and it will
figure out the best data_type to be used for the transfer instead of
hardwiring 32 or 16 bit data.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 drivers/mtd/onenand/omap2.c | 109 ++++++++++++++++++--------------------------
 1 file changed, 45 insertions(+), 64 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 0e7772e16d75..d22163271dc9 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -288,6 +288,33 @@ static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 	return 0;
 }
 
+static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
+					     dma_addr_t src, dma_addr_t dst,
+					     size_t count)
+{
+	int data_type = __ffs((src | dst | count));
+
+	if (data_type > OMAP_DMA_DATA_TYPE_S32)
+		data_type = OMAP_DMA_DATA_TYPE_S32;
+
+	omap_set_dma_transfer_params(c->dma_channel, data_type,
+				     count / BIT(data_type), 1, 0, 0, 0);
+	omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
+				src, 0, 0);
+	omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
+				 dst, 0, 0);
+
+	reinit_completion(&c->dma_done);
+	omap_start_dma(c->dma_channel);
+	if (!wait_for_completion_io_timeout(&c->dma_done,
+					    msecs_to_jiffies(20))) {
+		omap_stop_dma(c->dma_channel);
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
 #if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
 
 static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
@@ -298,10 +325,9 @@ static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
 	struct onenand_chip *this = mtd->priv;
 	dma_addr_t dma_src, dma_dst;
 	int bram_offset;
-	unsigned long timeout;
 	void *buf = (void *)buffer;
 	size_t xtra;
-	volatile unsigned *done;
+	int ret;
 
 	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 	if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
@@ -338,25 +364,10 @@ static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
 		goto out_copy;
 	}
 
-	omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
-				     count >> 2, 1, 0, 0, 0);
-	omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				dma_src, 0, 0);
-	omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				 dma_dst, 0, 0);
-
-	reinit_completion(&c->dma_done);
-	omap_start_dma(c->dma_channel);
-
-	timeout = jiffies + msecs_to_jiffies(20);
-	done = &c->dma_done.done;
-	while (time_before(jiffies, timeout))
-		if (*done)
-			break;
-
+	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 	dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 
-	if (!*done) {
+	if (ret) {
 		dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 		goto out_copy;
 	}
@@ -376,9 +387,8 @@ static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
 	struct onenand_chip *this = mtd->priv;
 	dma_addr_t dma_src, dma_dst;
 	int bram_offset;
-	unsigned long timeout;
 	void *buf = (void *)buffer;
-	volatile unsigned *done;
+	int ret;
 
 	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 	if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
@@ -409,25 +419,10 @@ static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
 		return -1;
 	}
 
-	omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
-				     count >> 2, 1, 0, 0, 0);
-	omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				dma_src, 0, 0);
-	omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				 dma_dst, 0, 0);
-
-	reinit_completion(&c->dma_done);
-	omap_start_dma(c->dma_channel);
-
-	timeout = jiffies + msecs_to_jiffies(20);
-	done = &c->dma_done.done;
-	while (time_before(jiffies, timeout))
-		if (*done)
-			break;
-
+	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 	dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
 
-	if (!*done) {
+	if (ret) {
 		dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 		goto out_copy;
 	}
@@ -466,7 +461,7 @@ static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 	struct onenand_chip *this = mtd->priv;
 	dma_addr_t dma_src, dma_dst;
-	int bram_offset;
+	int bram_offset, ret;
 
 	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 	/* DMA is not used.  Revisit PM requirements before enabling it. */
@@ -488,20 +483,13 @@ static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 		return -1;
 	}
 
-	omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
-				     count / 4, 1, 0, 0, 0);
-	omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				dma_src, 0, 0);
-	omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				 dma_dst, 0, 0);
-
-	reinit_completion(&c->dma_done);
-	omap_start_dma(c->dma_channel);
-	wait_for_completion(&c->dma_done);
-
+	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 	dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 
-	return 0;
+	if (ret)
+		dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
+
+	return ret;
 }
 
 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
@@ -511,7 +499,7 @@ static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 	struct onenand_chip *this = mtd->priv;
 	dma_addr_t dma_src, dma_dst;
-	int bram_offset;
+	int bram_offset, ret;
 
 	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 	/* DMA is not used.  Revisit PM requirements before enabling it. */
@@ -533,20 +521,13 @@ static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 		return -1;
 	}
 
-	omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S16,
-				     count / 2, 1, 0, 0, 0);
-	omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				dma_src, 0, 0);
-	omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				 dma_dst, 0, 0);
-
-	reinit_completion(&c->dma_done);
-	omap_start_dma(c->dma_channel);
-	wait_for_completion(&c->dma_done);
-
+	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 	dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
 
-	return 0;
+	if (ret)
+		dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
+
+	return ret;
 }
 
 #else
-- 
2.11.0

[PATCH v5 09/16] mtd: onenand: omap2: Unify OMAP2 and OMAP3 DMA implementation

[Ladislav Michl]

Since the very first commit (36cd4fb5d277: "[MTD] [OneNAND] Add
OMAP2 / OMAP3 OneNAND driver") DMA is disabled for OMAP2. Later
fixes thus went only into OMAP3 specific DMA functions which
turned out not to be so OMAP3 specific, so merge those two
implementations.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4:
- rebase on top of Peter's patch

Changes in v3:
- new patch

Changes in v2: None

 drivers/mtd/onenand/omap2.c | 129 ++------------------------------------------
 1 file changed, 4 insertions(+), 125 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index d22163271dc9..36314124488d 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -315,9 +315,7 @@ static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
 	return 0;
 }
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
-
-static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
+static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 					unsigned char *buffer, int offset,
 					size_t count)
 {
@@ -379,7 +377,7 @@ static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
 	return 0;
 }
 
-static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
+static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 					 const unsigned char *buffer,
 					 int offset, size_t count)
 {
@@ -434,120 +432,6 @@ static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
 	return 0;
 }
 
-#else
-
-static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
-					unsigned char *buffer, int offset,
-					size_t count)
-{
-	return -ENOSYS;
-}
-
-static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
-					 const unsigned char *buffer,
-					 int offset, size_t count)
-{
-	return -ENOSYS;
-}
-
-#endif
-
-#if defined(CONFIG_ARCH_OMAP2) || defined(MULTI_OMAP2)
-
-static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
-					unsigned char *buffer, int offset,
-					size_t count)
-{
-	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
-	struct onenand_chip *this = mtd->priv;
-	dma_addr_t dma_src, dma_dst;
-	int bram_offset, ret;
-
-	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
-	/* DMA is not used.  Revisit PM requirements before enabling it. */
-	if (1 || (c->dma_channel < 0) ||
-	    ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
-	    (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
-		memcpy(buffer, (__force void *)(this->base + bram_offset),
-		       count);
-		return 0;
-	}
-
-	dma_src = c->phys_base + bram_offset;
-	dma_dst = dma_map_single(&c->pdev->dev, buffer, count,
-				 DMA_FROM_DEVICE);
-	if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
-		dev_err(&c->pdev->dev,
-			"Couldn't DMA map a %d byte buffer\n",
-			count);
-		return -1;
-	}
-
-	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
-	dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
-
-	if (ret)
-		dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
-
-	return ret;
-}
-
-static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
-					 const unsigned char *buffer,
-					 int offset, size_t count)
-{
-	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
-	struct onenand_chip *this = mtd->priv;
-	dma_addr_t dma_src, dma_dst;
-	int bram_offset, ret;
-
-	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
-	/* DMA is not used.  Revisit PM requirements before enabling it. */
-	if (1 || (c->dma_channel < 0) ||
-	    ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
-	    (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
-		memcpy((__force void *)(this->base + bram_offset), buffer,
-		       count);
-		return 0;
-	}
-
-	dma_src = dma_map_single(&c->pdev->dev, (void *) buffer, count,
-				 DMA_TO_DEVICE);
-	dma_dst = c->phys_base + bram_offset;
-	if (dma_mapping_error(&c->pdev->dev, dma_src)) {
-		dev_err(&c->pdev->dev,
-			"Couldn't DMA map a %d byte buffer\n",
-			count);
-		return -1;
-	}
-
-	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
-	dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
-
-	if (ret)
-		dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
-
-	return ret;
-}
-
-#else
-
-static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
-					unsigned char *buffer, int offset,
-					size_t count)
-{
-	return -ENOSYS;
-}
-
-static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
-					 const unsigned char *buffer,
-					 int offset, size_t count)
-{
-	return -ENOSYS;
-}
-
-#endif
-
 static struct platform_driver omap2_onenand_driver;
 
 static void omap2_onenand_shutdown(struct platform_device *pdev)
@@ -671,13 +555,8 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 	this = &c->onenand;
 	if (c->dma_channel >= 0) {
 		this->wait = omap2_onenand_wait;
-		if (c->flags & ONENAND_IN_OMAP34XX) {
-			this->read_bufferram = omap3_onenand_read_bufferram;
-			this->write_bufferram = omap3_onenand_write_bufferram;
-		} else {
-			this->read_bufferram = omap2_onenand_read_bufferram;
-			this->write_bufferram = omap2_onenand_write_bufferram;
-		}
+		this->read_bufferram = omap2_onenand_read_bufferram;
+		this->write_bufferram = omap2_onenand_write_bufferram;
 	}
 
 	if ((r = onenand_scan(&c->mtd, 1)) < 0)
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 09/16] mtd: onenand: omap2: Unify OMAP2 and OMAP3 DMA implementation

[Ladislav Michl]

Since the very first commit (36cd4fb5d277: "[MTD] [OneNAND] Add
OMAP2 / OMAP3 OneNAND driver") DMA is disabled for OMAP2. Later
fixes thus went only into OMAP3 specific DMA functions which
turned out not to be so OMAP3 specific, so merge those two
implementations.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4:
- rebase on top of Peter's patch

Changes in v3:
- new patch

Changes in v2: None

 drivers/mtd/onenand/omap2.c | 129 ++------------------------------------------
 1 file changed, 4 insertions(+), 125 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index d22163271dc9..36314124488d 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -315,9 +315,7 @@ static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
 	return 0;
 }
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
-
-static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
+static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 					unsigned char *buffer, int offset,
 					size_t count)
 {
@@ -379,7 +377,7 @@ static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
 	return 0;
 }
 
-static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
+static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 					 const unsigned char *buffer,
 					 int offset, size_t count)
 {
@@ -434,120 +432,6 @@ static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
 	return 0;
 }
 
-#else
-
-static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
-					unsigned char *buffer, int offset,
-					size_t count)
-{
-	return -ENOSYS;
-}
-
-static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
-					 const unsigned char *buffer,
-					 int offset, size_t count)
-{
-	return -ENOSYS;
-}
-
-#endif
-
-#if defined(CONFIG_ARCH_OMAP2) || defined(MULTI_OMAP2)
-
-static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
-					unsigned char *buffer, int offset,
-					size_t count)
-{
-	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
-	struct onenand_chip *this = mtd->priv;
-	dma_addr_t dma_src, dma_dst;
-	int bram_offset, ret;
-
-	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
-	/* DMA is not used.  Revisit PM requirements before enabling it. */
-	if (1 || (c->dma_channel < 0) ||
-	    ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
-	    (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
-		memcpy(buffer, (__force void *)(this->base + bram_offset),
-		       count);
-		return 0;
-	}
-
-	dma_src = c->phys_base + bram_offset;
-	dma_dst = dma_map_single(&c->pdev->dev, buffer, count,
-				 DMA_FROM_DEVICE);
-	if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
-		dev_err(&c->pdev->dev,
-			"Couldn't DMA map a %d byte buffer\n",
-			count);
-		return -1;
-	}
-
-	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
-	dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
-
-	if (ret)
-		dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
-
-	return ret;
-}
-
-static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
-					 const unsigned char *buffer,
-					 int offset, size_t count)
-{
-	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
-	struct onenand_chip *this = mtd->priv;
-	dma_addr_t dma_src, dma_dst;
-	int bram_offset, ret;
-
-	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
-	/* DMA is not used.  Revisit PM requirements before enabling it. */
-	if (1 || (c->dma_channel < 0) ||
-	    ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
-	    (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
-		memcpy((__force void *)(this->base + bram_offset), buffer,
-		       count);
-		return 0;
-	}
-
-	dma_src = dma_map_single(&c->pdev->dev, (void *) buffer, count,
-				 DMA_TO_DEVICE);
-	dma_dst = c->phys_base + bram_offset;
-	if (dma_mapping_error(&c->pdev->dev, dma_src)) {
-		dev_err(&c->pdev->dev,
-			"Couldn't DMA map a %d byte buffer\n",
-			count);
-		return -1;
-	}
-
-	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
-	dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
-
-	if (ret)
-		dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
-
-	return ret;
-}
-
-#else
-
-static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
-					unsigned char *buffer, int offset,
-					size_t count)
-{
-	return -ENOSYS;
-}
-
-static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
-					 const unsigned char *buffer,
-					 int offset, size_t count)
-{
-	return -ENOSYS;
-}
-
-#endif
-
 static struct platform_driver omap2_onenand_driver;
 
 static void omap2_onenand_shutdown(struct platform_device *pdev)
@@ -671,13 +555,8 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 	this = &c->onenand;
 	if (c->dma_channel >= 0) {
 		this->wait = omap2_onenand_wait;
-		if (c->flags & ONENAND_IN_OMAP34XX) {
-			this->read_bufferram = omap3_onenand_read_bufferram;
-			this->write_bufferram = omap3_onenand_write_bufferram;
-		} else {
-			this->read_bufferram = omap2_onenand_read_bufferram;
-			this->write_bufferram = omap2_onenand_write_bufferram;
-		}
+		this->read_bufferram = omap2_onenand_read_bufferram;
+		this->write_bufferram = omap2_onenand_write_bufferram;
 	}
 
 	if ((r = onenand_scan(&c->mtd, 1)) < 0)
-- 
2.11.0

[PATCH v5 10/16] mtd: onenand: omap2: Convert to use dmaengine for memcpy

[Ladislav Michl]

From: Peter Ujfalusi <peter.ujfalusi@ti.com>

Do not use the legacy and deprecated omap-dma interface for setting up the
memcpy.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 drivers/mtd/onenand/omap2.c | 80 +++++++++++++++++++++------------------------
 1 file changed, 38 insertions(+), 42 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 36314124488d..c9ff67100ef4 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -32,6 +32,7 @@
 #include <linux/interrupt.h>
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/gpio.h>
@@ -39,8 +40,6 @@
 #include <asm/mach/flash.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
 
-#include <linux/omap-dma.h>
-
 #define DRIVER_NAME "omap2-onenand"
 
 #define ONENAND_BUFRAM_SIZE	(1024 * 5)
@@ -55,17 +54,15 @@ struct omap2_onenand {
 	struct onenand_chip onenand;
 	struct completion irq_done;
 	struct completion dma_done;
-	int dma_channel;
+	struct dma_chan *dma_chan;
 	int freq;
 	int (*setup)(void __iomem *base, int *freq_ptr);
 	u8 flags;
 };
 
-static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
+static void omap2_onenand_dma_complete_func(void *completion)
 {
-	struct omap2_onenand *c = data;
-
-	complete(&c->dma_done);
+	complete(completion);
 }
 
 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
@@ -292,23 +289,31 @@ static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
 					     dma_addr_t src, dma_addr_t dst,
 					     size_t count)
 {
-	int data_type = __ffs((src | dst | count));
+	struct dma_async_tx_descriptor *tx;
+	dma_cookie_t cookie;
 
-	if (data_type > OMAP_DMA_DATA_TYPE_S32)
-		data_type = OMAP_DMA_DATA_TYPE_S32;
-
-	omap_set_dma_transfer_params(c->dma_channel, data_type,
-				     count / BIT(data_type), 1, 0, 0, 0);
-	omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				src, 0, 0);
-	omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				 dst, 0, 0);
+	tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, 0);
+	if (!tx) {
+		dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");
+		return -EIO;
+	}
 
 	reinit_completion(&c->dma_done);
-	omap_start_dma(c->dma_channel);
+
+	tx->callback = omap2_onenand_dma_complete_func;
+	tx->callback_param = &c->dma_done;
+
+	cookie = tx->tx_submit(tx);
+	if (dma_submit_error(cookie)) {
+		dev_err(&c->pdev->dev, "Failed to do DMA tx_submit\n");
+		return -EIO;
+	}
+
+	dma_async_issue_pending(c->dma_chan);
+
 	if (!wait_for_completion_io_timeout(&c->dma_done,
 					    msecs_to_jiffies(20))) {
-		omap_stop_dma(c->dma_channel);
+		dmaengine_terminate_sync(c->dma_chan);
 		return -ETIMEDOUT;
 	}
 
@@ -468,8 +473,7 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 	c->flags = pdata->flags;
 	c->gpmc_cs = pdata->cs;
 	c->gpio_irq = pdata->gpio_irq;
-	c->dma_channel = pdata->dma_channel;
-	if (c->dma_channel < 0) {
+	if (pdata->dma_channel < 0) {
 		/* if -1, don't use DMA */
 		c->gpio_irq = 0;
 	}
@@ -521,25 +525,17 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 		goto err_release_gpio;
 	}
 
-	if (c->dma_channel >= 0) {
-		r = omap_request_dma(0, pdev->dev.driver->name,
-				     omap2_onenand_dma_cb, (void *) c,
-				     &c->dma_channel);
-		if (r == 0) {
-			omap_set_dma_write_mode(c->dma_channel,
-						OMAP_DMA_WRITE_NON_POSTED);
-			omap_set_dma_src_data_pack(c->dma_channel, 1);
-			omap_set_dma_src_burst_mode(c->dma_channel,
-						    OMAP_DMA_DATA_BURST_8);
-			omap_set_dma_dest_data_pack(c->dma_channel, 1);
-			omap_set_dma_dest_burst_mode(c->dma_channel,
-						     OMAP_DMA_DATA_BURST_8);
-		} else {
+	if (pdata->dma_channel >= 0) {
+		dma_cap_mask_t mask;
+
+		dma_cap_zero(mask);
+		dma_cap_set(DMA_MEMCPY, mask);
+
+		c->dma_chan = dma_request_channel(mask, NULL, NULL);
+		if (!c->dma_chan)
 			dev_info(&pdev->dev,
 				 "failed to allocate DMA for OneNAND, "
 				 "using PIO instead\n");
-			c->dma_channel = -1;
-		}
 	}
 
 	dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
@@ -553,7 +549,7 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 	mtd_set_of_node(&c->mtd, pdata->of_node);
 
 	this = &c->onenand;
-	if (c->dma_channel >= 0) {
+	if (c->dma_chan) {
 		this->wait = omap2_onenand_wait;
 		this->read_bufferram = omap2_onenand_read_bufferram;
 		this->write_bufferram = omap2_onenand_write_bufferram;
@@ -573,8 +569,8 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 err_release_onenand:
 	onenand_release(&c->mtd);
 err_release_dma:
-	if (c->dma_channel != -1)
-		omap_free_dma(c->dma_channel);
+	if (c->dma_chan)
+		dma_release_channel(c->dma_chan);
 	if (c->gpio_irq)
 		free_irq(gpio_to_irq(c->gpio_irq), c);
 err_release_gpio:
@@ -595,8 +591,8 @@ static int omap2_onenand_remove(struct platform_device *pdev)
 	struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 
 	onenand_release(&c->mtd);
-	if (c->dma_channel != -1)
-		omap_free_dma(c->dma_channel);
+	if (c->dma_chan)
+		dma_release_channel(c->dma_chan);
 	omap2_onenand_shutdown(pdev);
 	if (c->gpio_irq) {
 		free_irq(gpio_to_irq(c->gpio_irq), c);
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 10/16] mtd: onenand: omap2: Convert to use dmaengine for memcpy

[Ladislav Michl]

From: Peter Ujfalusi <peter.ujfalusi@ti.com>

Do not use the legacy and deprecated omap-dma interface for setting up the
memcpy.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 drivers/mtd/onenand/omap2.c | 80 +++++++++++++++++++++------------------------
 1 file changed, 38 insertions(+), 42 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 36314124488d..c9ff67100ef4 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -32,6 +32,7 @@
 #include <linux/interrupt.h>
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/gpio.h>
@@ -39,8 +40,6 @@
 #include <asm/mach/flash.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
 
-#include <linux/omap-dma.h>
-
 #define DRIVER_NAME "omap2-onenand"
 
 #define ONENAND_BUFRAM_SIZE	(1024 * 5)
@@ -55,17 +54,15 @@ struct omap2_onenand {
 	struct onenand_chip onenand;
 	struct completion irq_done;
 	struct completion dma_done;
-	int dma_channel;
+	struct dma_chan *dma_chan;
 	int freq;
 	int (*setup)(void __iomem *base, int *freq_ptr);
 	u8 flags;
 };
 
-static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
+static void omap2_onenand_dma_complete_func(void *completion)
 {
-	struct omap2_onenand *c = data;
-
-	complete(&c->dma_done);
+	complete(completion);
 }
 
 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
@@ -292,23 +289,31 @@ static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
 					     dma_addr_t src, dma_addr_t dst,
 					     size_t count)
 {
-	int data_type = __ffs((src | dst | count));
+	struct dma_async_tx_descriptor *tx;
+	dma_cookie_t cookie;
 
-	if (data_type > OMAP_DMA_DATA_TYPE_S32)
-		data_type = OMAP_DMA_DATA_TYPE_S32;
-
-	omap_set_dma_transfer_params(c->dma_channel, data_type,
-				     count / BIT(data_type), 1, 0, 0, 0);
-	omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				src, 0, 0);
-	omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
-				 dst, 0, 0);
+	tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, 0);
+	if (!tx) {
+		dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");
+		return -EIO;
+	}
 
 	reinit_completion(&c->dma_done);
-	omap_start_dma(c->dma_channel);
+
+	tx->callback = omap2_onenand_dma_complete_func;
+	tx->callback_param = &c->dma_done;
+
+	cookie = tx->tx_submit(tx);
+	if (dma_submit_error(cookie)) {
+		dev_err(&c->pdev->dev, "Failed to do DMA tx_submit\n");
+		return -EIO;
+	}
+
+	dma_async_issue_pending(c->dma_chan);
+
 	if (!wait_for_completion_io_timeout(&c->dma_done,
 					    msecs_to_jiffies(20))) {
-		omap_stop_dma(c->dma_channel);
+		dmaengine_terminate_sync(c->dma_chan);
 		return -ETIMEDOUT;
 	}
 
@@ -468,8 +473,7 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 	c->flags = pdata->flags;
 	c->gpmc_cs = pdata->cs;
 	c->gpio_irq = pdata->gpio_irq;
-	c->dma_channel = pdata->dma_channel;
-	if (c->dma_channel < 0) {
+	if (pdata->dma_channel < 0) {
 		/* if -1, don't use DMA */
 		c->gpio_irq = 0;
 	}
@@ -521,25 +525,17 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 		goto err_release_gpio;
 	}
 
-	if (c->dma_channel >= 0) {
-		r = omap_request_dma(0, pdev->dev.driver->name,
-				     omap2_onenand_dma_cb, (void *) c,
-				     &c->dma_channel);
-		if (r == 0) {
-			omap_set_dma_write_mode(c->dma_channel,
-						OMAP_DMA_WRITE_NON_POSTED);
-			omap_set_dma_src_data_pack(c->dma_channel, 1);
-			omap_set_dma_src_burst_mode(c->dma_channel,
-						    OMAP_DMA_DATA_BURST_8);
-			omap_set_dma_dest_data_pack(c->dma_channel, 1);
-			omap_set_dma_dest_burst_mode(c->dma_channel,
-						     OMAP_DMA_DATA_BURST_8);
-		} else {
+	if (pdata->dma_channel >= 0) {
+		dma_cap_mask_t mask;
+
+		dma_cap_zero(mask);
+		dma_cap_set(DMA_MEMCPY, mask);
+
+		c->dma_chan = dma_request_channel(mask, NULL, NULL);
+		if (!c->dma_chan)
 			dev_info(&pdev->dev,
 				 "failed to allocate DMA for OneNAND, "
 				 "using PIO instead\n");
-			c->dma_channel = -1;
-		}
 	}
 
 	dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
@@ -553,7 +549,7 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 	mtd_set_of_node(&c->mtd, pdata->of_node);
 
 	this = &c->onenand;
-	if (c->dma_channel >= 0) {
+	if (c->dma_chan) {
 		this->wait = omap2_onenand_wait;
 		this->read_bufferram = omap2_onenand_read_bufferram;
 		this->write_bufferram = omap2_onenand_write_bufferram;
@@ -573,8 +569,8 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 err_release_onenand:
 	onenand_release(&c->mtd);
 err_release_dma:
-	if (c->dma_channel != -1)
-		omap_free_dma(c->dma_channel);
+	if (c->dma_chan)
+		dma_release_channel(c->dma_chan);
 	if (c->gpio_irq)
 		free_irq(gpio_to_irq(c->gpio_irq), c);
 err_release_gpio:
@@ -595,8 +591,8 @@ static int omap2_onenand_remove(struct platform_device *pdev)
 	struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 
 	onenand_release(&c->mtd);
-	if (c->dma_channel != -1)
-		omap_free_dma(c->dma_channel);
+	if (c->dma_chan)
+		dma_release_channel(c->dma_chan);
 	omap2_onenand_shutdown(pdev);
 	if (c->gpio_irq) {
 		free_irq(gpio_to_irq(c->gpio_irq), c);
-- 
2.11.0

[PATCH v5 11/16] mtd: onenand: omap2: Do not make delay for GPIO OMAP3 specific

[Ladislav Michl]

Second commit in driver history (782b7a367d81: "[MTD] [OneNAND] OMAP3:
add delay for GPIO") added quirk for waiting until GPIO line settle.
As DMA was disabled for OMAP2 boards, chances are this problem was
not OMAP3 specific and as it is just one register read, previous
test for SoC type is approximately as expensive as read itself.
Make delay unconditional, which allows removing SoC specific code
alltogether.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- new patch

Changes in v2: None

 drivers/mtd/onenand/omap2.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index c9ff67100ef4..e4857a41760d 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -57,7 +57,6 @@ struct omap2_onenand {
 	struct dma_chan *dma_chan;
 	int freq;
 	int (*setup)(void __iomem *base, int *freq_ptr);
-	u8 flags;
 };
 
 static void omap2_onenand_dma_complete_func(void *completion)
@@ -148,9 +147,8 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 		if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
 			syscfg |= ONENAND_SYS_CFG1_IOBE;
 			write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
-			if (c->flags & ONENAND_IN_OMAP34XX)
-				/* Add a delay to let GPIO settle */
-				syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
+			/* Add a delay to let GPIO settle */
+			syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 		}
 
 		reinit_completion(&c->irq_done);
@@ -470,7 +468,6 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 
 	init_completion(&c->irq_done);
 	init_completion(&c->dma_done);
-	c->flags = pdata->flags;
 	c->gpmc_cs = pdata->cs;
 	c->gpio_irq = pdata->gpio_irq;
 	if (pdata->dma_channel < 0) {
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 11/16] mtd: onenand: omap2: Do not make delay for GPIO OMAP3 specific

[Ladislav Michl]

Second commit in driver history (782b7a367d81: "[MTD] [OneNAND] OMAP3:
add delay for GPIO") added quirk for waiting until GPIO line settle.
As DMA was disabled for OMAP2 boards, chances are this problem was
not OMAP3 specific and as it is just one register read, previous
test for SoC type is approximately as expensive as read itself.
Make delay unconditional, which allows removing SoC specific code
alltogether.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- new patch

Changes in v2: None

 drivers/mtd/onenand/omap2.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index c9ff67100ef4..e4857a41760d 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -57,7 +57,6 @@ struct omap2_onenand {
 	struct dma_chan *dma_chan;
 	int freq;
 	int (*setup)(void __iomem *base, int *freq_ptr);
-	u8 flags;
 };
 
 static void omap2_onenand_dma_complete_func(void *completion)
@@ -148,9 +147,8 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 		if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
 			syscfg |= ONENAND_SYS_CFG1_IOBE;
 			write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
-			if (c->flags & ONENAND_IN_OMAP34XX)
-				/* Add a delay to let GPIO settle */
-				syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
+			/* Add a delay to let GPIO settle */
+			syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 		}
 
 		reinit_completion(&c->irq_done);
@@ -470,7 +468,6 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 
 	init_completion(&c->irq_done);
 	init_completion(&c->dma_done);
-	c->flags = pdata->flags;
 	c->gpmc_cs = pdata->cs;
 	c->gpio_irq = pdata->gpio_irq;
 	if (pdata->dma_channel < 0) {
-- 
2.11.0

[PATCH v5 12/16] mtd: onenand: omap2: Decouple DMA enabling from INT pin availability

[Ladislav Michl]

INT pin (gpio_irq) is not really needed for DMA but only for notification
when a command that needs wait has completed. DMA memcpy can be still used
even without gpio_irq available, so enable it unconditionally.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5:
- rename patch and fix commit message

Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 drivers/mtd/onenand/omap2.c | 52 ++++++++++++++++++---------------------------
 1 file changed, 21 insertions(+), 31 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index e4857a41760d..1cd78a076759 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -152,17 +152,13 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 		}
 
 		reinit_completion(&c->irq_done);
-		if (c->gpio_irq) {
-			result = gpio_get_value(c->gpio_irq);
-			if (result == -1) {
-				ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
-				intr = read_reg(c, ONENAND_REG_INTERRUPT);
-				wait_err("gpio error", state, ctrl, intr);
-				return -EIO;
-			}
-		} else
-			result = 0;
-		if (result == 0) {
+		result = gpio_get_value(c->gpio_irq);
+		if (result < 0) {
+			ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
+			intr = read_reg(c, ONENAND_REG_INTERRUPT);
+			wait_err("gpio error", state, ctrl, intr);
+			return -EIO;
+		} else if (result == 0) {
 			int retry_cnt = 0;
 retry:
 			if (!wait_for_completion_io_timeout(&c->irq_done,
@@ -450,6 +446,7 @@ static void omap2_onenand_shutdown(struct platform_device *pdev)
 
 static int omap2_onenand_probe(struct platform_device *pdev)
 {
+	dma_cap_mask_t mask;
 	struct omap_onenand_platform_data *pdata;
 	struct omap2_onenand *c;
 	struct onenand_chip *this;
@@ -513,31 +510,25 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 			dev_err(&pdev->dev,  "Failed to request GPIO%d for "
 				"OneNAND\n", c->gpio_irq);
 			goto err_iounmap;
-	}
-	gpio_direction_input(c->gpio_irq);
+		}
+		gpio_direction_input(c->gpio_irq);
 
-	if ((r = request_irq(gpio_to_irq(c->gpio_irq),
-			     omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
-			     pdev->dev.driver->name, c)) < 0)
-		goto err_release_gpio;
-	}
+		if ((r = request_irq(gpio_to_irq(c->gpio_irq),
+				     omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
+				     pdev->dev.driver->name, c)) < 0)
+			goto err_release_gpio;
 
-	if (pdata->dma_channel >= 0) {
-		dma_cap_mask_t mask;
+		this->wait = omap2_onenand_wait;
+	}
 
-		dma_cap_zero(mask);
-		dma_cap_set(DMA_MEMCPY, mask);
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_MEMCPY, mask);
 
-		c->dma_chan = dma_request_channel(mask, NULL, NULL);
-		if (!c->dma_chan)
-			dev_info(&pdev->dev,
-				 "failed to allocate DMA for OneNAND, "
-				 "using PIO instead\n");
-	}
+	c->dma_chan = dma_request_channel(mask, NULL, NULL);
 
 	dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
-		 "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base,
-		 c->onenand.base, c->freq);
+		 "base %p, freq %d MHz, %s mode\n", c->gpmc_cs, c->phys_base,
+		 c->onenand.base, c->freq, c->dma_chan ? "DMA" : "PIO");
 
 	c->pdev = pdev;
 	c->mtd.priv = &c->onenand;
@@ -547,7 +538,6 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 
 	this = &c->onenand;
 	if (c->dma_chan) {
-		this->wait = omap2_onenand_wait;
 		this->read_bufferram = omap2_onenand_read_bufferram;
 		this->write_bufferram = omap2_onenand_write_bufferram;
 	}
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 12/16] mtd: onenand: omap2: Decouple DMA enabling from INT pin availability

[Ladislav Michl]

INT pin (gpio_irq) is not really needed for DMA but only for notification
when a command that needs wait has completed. DMA memcpy can be still used
even without gpio_irq available, so enable it unconditionally.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5:
- rename patch and fix commit message

Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 drivers/mtd/onenand/omap2.c | 52 ++++++++++++++++++---------------------------
 1 file changed, 21 insertions(+), 31 deletions(-)

diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index e4857a41760d..1cd78a076759 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -152,17 +152,13 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 		}
 
 		reinit_completion(&c->irq_done);
-		if (c->gpio_irq) {
-			result = gpio_get_value(c->gpio_irq);
-			if (result == -1) {
-				ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
-				intr = read_reg(c, ONENAND_REG_INTERRUPT);
-				wait_err("gpio error", state, ctrl, intr);
-				return -EIO;
-			}
-		} else
-			result = 0;
-		if (result == 0) {
+		result = gpio_get_value(c->gpio_irq);
+		if (result < 0) {
+			ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
+			intr = read_reg(c, ONENAND_REG_INTERRUPT);
+			wait_err("gpio error", state, ctrl, intr);
+			return -EIO;
+		} else if (result == 0) {
 			int retry_cnt = 0;
 retry:
 			if (!wait_for_completion_io_timeout(&c->irq_done,
@@ -450,6 +446,7 @@ static void omap2_onenand_shutdown(struct platform_device *pdev)
 
 static int omap2_onenand_probe(struct platform_device *pdev)
 {
+	dma_cap_mask_t mask;
 	struct omap_onenand_platform_data *pdata;
 	struct omap2_onenand *c;
 	struct onenand_chip *this;
@@ -513,31 +510,25 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 			dev_err(&pdev->dev,  "Failed to request GPIO%d for "
 				"OneNAND\n", c->gpio_irq);
 			goto err_iounmap;
-	}
-	gpio_direction_input(c->gpio_irq);
+		}
+		gpio_direction_input(c->gpio_irq);
 
-	if ((r = request_irq(gpio_to_irq(c->gpio_irq),
-			     omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
-			     pdev->dev.driver->name, c)) < 0)
-		goto err_release_gpio;
-	}
+		if ((r = request_irq(gpio_to_irq(c->gpio_irq),
+				     omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
+				     pdev->dev.driver->name, c)) < 0)
+			goto err_release_gpio;
 
-	if (pdata->dma_channel >= 0) {
-		dma_cap_mask_t mask;
+		this->wait = omap2_onenand_wait;
+	}
 
-		dma_cap_zero(mask);
-		dma_cap_set(DMA_MEMCPY, mask);
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_MEMCPY, mask);
 
-		c->dma_chan = dma_request_channel(mask, NULL, NULL);
-		if (!c->dma_chan)
-			dev_info(&pdev->dev,
-				 "failed to allocate DMA for OneNAND, "
-				 "using PIO instead\n");
-	}
+	c->dma_chan = dma_request_channel(mask, NULL, NULL);
 
 	dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
-		 "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base,
-		 c->onenand.base, c->freq);
+		 "base %p, freq %d MHz, %s mode\n", c->gpmc_cs, c->phys_base,
+		 c->onenand.base, c->freq, c->dma_chan ? "DMA" : "PIO");
 
 	c->pdev = pdev;
 	c->mtd.priv = &c->onenand;
@@ -547,7 +538,6 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 
 	this = &c->onenand;
 	if (c->dma_chan) {
-		this->wait = omap2_onenand_wait;
 		this->read_bufferram = omap2_onenand_read_bufferram;
 		this->write_bufferram = omap2_onenand_write_bufferram;
 	}
-- 
2.11.0

[PATCH v5 13/16] memory: omap-gpmc: Refactor OneNAND support

[Ladislav Michl]

Use generic probe function to deal with OneNAND node and remove now useless
gpmc_probe_onenand_child function.
Import sync mode timing calculation function from mach-omap2/gpmc-onenand.c
and prepare for MTD driver DTfication.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5:
- make gpmc_omap_onenand_set_timings decsription more descriptive

Changes in v4: None
Changes in v3: None
Changes in v2:
- add gpmc_omap_onenand_set_timings description

 drivers/memory/omap-gpmc.c | 158 +++++++++++++++++++++++++++++++++------------
 include/linux/omap-gpmc.h  |  28 ++++++++
 2 files changed, 145 insertions(+), 41 deletions(-)

diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 0e30ee1c8677..90a66b3f7ae1 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -32,7 +32,6 @@
 #include <linux/pm_runtime.h>
 
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include <asm/mach-types.h>
 
@@ -1138,6 +1137,112 @@ struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
 }
 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
 
+static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
+						struct gpmc_settings *s,
+						int freq, int latency)
+{
+	struct gpmc_device_timings dev_t;
+	const int t_cer  = 15;
+	const int t_avdp = 12;
+	const int t_cez  = 20; /* max of t_cez, t_oez */
+	const int t_wpl  = 40;
+	const int t_wph  = 30;
+	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
+
+	switch (freq) {
+	case 104:
+		min_gpmc_clk_period = 9600; /* 104 MHz */
+		t_ces   = 3;
+		t_avds  = 4;
+		t_avdh  = 2;
+		t_ach   = 3;
+		t_aavdh = 6;
+		t_rdyo  = 6;
+		break;
+	case 83:
+		min_gpmc_clk_period = 12000; /* 83 MHz */
+		t_ces   = 5;
+		t_avds  = 4;
+		t_avdh  = 2;
+		t_ach   = 6;
+		t_aavdh = 6;
+		t_rdyo  = 9;
+		break;
+	case 66:
+		min_gpmc_clk_period = 15000; /* 66 MHz */
+		t_ces   = 6;
+		t_avds  = 5;
+		t_avdh  = 2;
+		t_ach   = 6;
+		t_aavdh = 6;
+		t_rdyo  = 11;
+		break;
+	default:
+		min_gpmc_clk_period = 18500; /* 54 MHz */
+		t_ces   = 7;
+		t_avds  = 7;
+		t_avdh  = 7;
+		t_ach   = 9;
+		t_aavdh = 7;
+		t_rdyo  = 15;
+		break;
+	}
+
+	/* Set synchronous read timings */
+	memset(&dev_t, 0, sizeof(dev_t));
+
+	if (!s->sync_write) {
+		dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
+		dev_t.t_wpl = t_wpl * 1000;
+		dev_t.t_wph = t_wph * 1000;
+		dev_t.t_aavdh = t_aavdh * 1000;
+	}
+	dev_t.ce_xdelay = true;
+	dev_t.avd_xdelay = true;
+	dev_t.oe_xdelay = true;
+	dev_t.we_xdelay = true;
+	dev_t.clk = min_gpmc_clk_period;
+	dev_t.t_bacc = dev_t.clk;
+	dev_t.t_ces = t_ces * 1000;
+	dev_t.t_avds = t_avds * 1000;
+	dev_t.t_avdh = t_avdh * 1000;
+	dev_t.t_ach = t_ach * 1000;
+	dev_t.cyc_iaa = (latency + 1);
+	dev_t.t_cez_r = t_cez * 1000;
+	dev_t.t_cez_w = dev_t.t_cez_r;
+	dev_t.cyc_aavdh_oe = 1;
+	dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
+
+	gpmc_calc_timings(t, s, &dev_t);
+}
+
+int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
+				  int latency,
+				  struct gpmc_onenand_info *info)
+{
+	int ret;
+	struct gpmc_timings gpmc_t;
+	struct gpmc_settings gpmc_s;
+
+	gpmc_read_settings_dt(dev->of_node, &gpmc_s);
+
+	info->sync_read = gpmc_s.sync_read;
+	info->sync_write = gpmc_s.sync_write;
+	info->burst_len = gpmc_s.burst_len;
+
+	if (!gpmc_s.sync_read && !gpmc_s.sync_write)
+		return 0;
+
+	gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
+
+	ret = gpmc_cs_program_settings(cs, &gpmc_s);
+	if (ret < 0)
+		return ret;
+
+	return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
+}
+EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
+
 int gpmc_get_client_irq(unsigned irq_config)
 {
 	if (!gpmc_irq_domain) {
@@ -1916,41 +2021,6 @@ static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
 		of_property_read_bool(np, "gpmc,time-para-granularity");
 }
 
-#if IS_ENABLED(CONFIG_MTD_ONENAND)
-static int gpmc_probe_onenand_child(struct platform_device *pdev,
-				 struct device_node *child)
-{
-	u32 val;
-	struct omap_onenand_platform_data *gpmc_onenand_data;
-
-	if (of_property_read_u32(child, "reg", &val) < 0) {
-		dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
-			child);
-		return -ENODEV;
-	}
-
-	gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
-					 GFP_KERNEL);
-	if (!gpmc_onenand_data)
-		return -ENOMEM;
-
-	gpmc_onenand_data->cs = val;
-	gpmc_onenand_data->of_node = child;
-	gpmc_onenand_data->dma_channel = -1;
-
-	if (!of_property_read_u32(child, "dma-channel", &val))
-		gpmc_onenand_data->dma_channel = val;
-
-	return gpmc_onenand_init(gpmc_onenand_data);
-}
-#else
-static int gpmc_probe_onenand_child(struct platform_device *pdev,
-				    struct device_node *child)
-{
-	return 0;
-}
-#endif
-
 /**
  * gpmc_probe_generic_child - configures the gpmc for a child device
  * @pdev:	pointer to gpmc platform device
@@ -2053,6 +2123,16 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
 		}
 	}
 
+	if (of_node_cmp(child->name, "onenand") == 0) {
+		/* Warn about older DT blobs with no compatible property */
+		if (!of_property_read_bool(child, "compatible")) {
+			dev_warn(&pdev->dev,
+				 "Incompatible OneNAND node: missing compatible");
+			ret = -EINVAL;
+			goto err;
+		}
+	}
+
 	if (of_device_is_compatible(child, "ti,omap2-nand")) {
 		/* NAND specific setup */
 		val = 8;
@@ -2189,11 +2269,7 @@ static void gpmc_probe_dt_children(struct platform_device *pdev)
 		if (!child->name)
 			continue;
 
-		if (of_node_cmp(child->name, "onenand") == 0)
-			ret = gpmc_probe_onenand_child(pdev, child);
-		else
-			ret = gpmc_probe_generic_child(pdev, child);
-
+		ret = gpmc_probe_generic_child(pdev, child);
 		if (ret) {
 			dev_err(&pdev->dev, "failed to probe DT child '%s': %d\n",
 				child->name, ret);
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
index edfa280c3d56..053feb41510a 100644
--- a/include/linux/omap-gpmc.h
+++ b/include/linux/omap-gpmc.h
@@ -25,15 +25,43 @@ struct gpmc_nand_ops {
 
 struct gpmc_nand_regs;
 
+struct gpmc_onenand_info {
+	bool sync_read;
+	bool sync_write;
+	int burst_len;
+};
+
 #if IS_ENABLED(CONFIG_OMAP_GPMC)
 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *regs,
 					     int cs);
+/**
+ * gpmc_omap_onenand_set_timings - set optimized sync timings.
+ * @cs:      Chip Select Region
+ * @freq:    Chip frequency
+ * @latency: Burst latency cycle count
+ * @info:    Structure describing parameters used
+ *
+ * Sets optimized timings for the @cs region based on @freq and @latency.
+ * Updates the @info structure based on the GPMC settings.
+ */
+int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
+				  int latency,
+				  struct gpmc_onenand_info *info);
+
 #else
 static inline struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *regs,
 							   int cs)
 {
 	return NULL;
 }
+
+static inline
+int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
+				  int latency,
+				  struct gpmc_onenand_info *info)
+{
+	return -EINVAL;
+}
 #endif /* CONFIG_OMAP_GPMC */
 
 extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 13/16] memory: omap-gpmc: Refactor OneNAND support

[Ladislav Michl]

Use generic probe function to deal with OneNAND node and remove now useless
gpmc_probe_onenand_child function.
Import sync mode timing calculation function from mach-omap2/gpmc-onenand.c
and prepare for MTD driver DTfication.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5:
- make gpmc_omap_onenand_set_timings decsription more descriptive

Changes in v4: None
Changes in v3: None
Changes in v2:
- add gpmc_omap_onenand_set_timings description

 drivers/memory/omap-gpmc.c | 158 +++++++++++++++++++++++++++++++++------------
 include/linux/omap-gpmc.h  |  28 ++++++++
 2 files changed, 145 insertions(+), 41 deletions(-)

diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 0e30ee1c8677..90a66b3f7ae1 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -32,7 +32,6 @@
 #include <linux/pm_runtime.h>
 
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include <asm/mach-types.h>
 
@@ -1138,6 +1137,112 @@ struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
 }
 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
 
+static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
+						struct gpmc_settings *s,
+						int freq, int latency)
+{
+	struct gpmc_device_timings dev_t;
+	const int t_cer  = 15;
+	const int t_avdp = 12;
+	const int t_cez  = 20; /* max of t_cez, t_oez */
+	const int t_wpl  = 40;
+	const int t_wph  = 30;
+	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
+
+	switch (freq) {
+	case 104:
+		min_gpmc_clk_period = 9600; /* 104 MHz */
+		t_ces   = 3;
+		t_avds  = 4;
+		t_avdh  = 2;
+		t_ach   = 3;
+		t_aavdh = 6;
+		t_rdyo  = 6;
+		break;
+	case 83:
+		min_gpmc_clk_period = 12000; /* 83 MHz */
+		t_ces   = 5;
+		t_avds  = 4;
+		t_avdh  = 2;
+		t_ach   = 6;
+		t_aavdh = 6;
+		t_rdyo  = 9;
+		break;
+	case 66:
+		min_gpmc_clk_period = 15000; /* 66 MHz */
+		t_ces   = 6;
+		t_avds  = 5;
+		t_avdh  = 2;
+		t_ach   = 6;
+		t_aavdh = 6;
+		t_rdyo  = 11;
+		break;
+	default:
+		min_gpmc_clk_period = 18500; /* 54 MHz */
+		t_ces   = 7;
+		t_avds  = 7;
+		t_avdh  = 7;
+		t_ach   = 9;
+		t_aavdh = 7;
+		t_rdyo  = 15;
+		break;
+	}
+
+	/* Set synchronous read timings */
+	memset(&dev_t, 0, sizeof(dev_t));
+
+	if (!s->sync_write) {
+		dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
+		dev_t.t_wpl = t_wpl * 1000;
+		dev_t.t_wph = t_wph * 1000;
+		dev_t.t_aavdh = t_aavdh * 1000;
+	}
+	dev_t.ce_xdelay = true;
+	dev_t.avd_xdelay = true;
+	dev_t.oe_xdelay = true;
+	dev_t.we_xdelay = true;
+	dev_t.clk = min_gpmc_clk_period;
+	dev_t.t_bacc = dev_t.clk;
+	dev_t.t_ces = t_ces * 1000;
+	dev_t.t_avds = t_avds * 1000;
+	dev_t.t_avdh = t_avdh * 1000;
+	dev_t.t_ach = t_ach * 1000;
+	dev_t.cyc_iaa = (latency + 1);
+	dev_t.t_cez_r = t_cez * 1000;
+	dev_t.t_cez_w = dev_t.t_cez_r;
+	dev_t.cyc_aavdh_oe = 1;
+	dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
+
+	gpmc_calc_timings(t, s, &dev_t);
+}
+
+int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
+				  int latency,
+				  struct gpmc_onenand_info *info)
+{
+	int ret;
+	struct gpmc_timings gpmc_t;
+	struct gpmc_settings gpmc_s;
+
+	gpmc_read_settings_dt(dev->of_node, &gpmc_s);
+
+	info->sync_read = gpmc_s.sync_read;
+	info->sync_write = gpmc_s.sync_write;
+	info->burst_len = gpmc_s.burst_len;
+
+	if (!gpmc_s.sync_read && !gpmc_s.sync_write)
+		return 0;
+
+	gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
+
+	ret = gpmc_cs_program_settings(cs, &gpmc_s);
+	if (ret < 0)
+		return ret;
+
+	return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
+}
+EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
+
 int gpmc_get_client_irq(unsigned irq_config)
 {
 	if (!gpmc_irq_domain) {
@@ -1916,41 +2021,6 @@ static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
 		of_property_read_bool(np, "gpmc,time-para-granularity");
 }
 
-#if IS_ENABLED(CONFIG_MTD_ONENAND)
-static int gpmc_probe_onenand_child(struct platform_device *pdev,
-				 struct device_node *child)
-{
-	u32 val;
-	struct omap_onenand_platform_data *gpmc_onenand_data;
-
-	if (of_property_read_u32(child, "reg", &val) < 0) {
-		dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
-			child);
-		return -ENODEV;
-	}
-
-	gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
-					 GFP_KERNEL);
-	if (!gpmc_onenand_data)
-		return -ENOMEM;
-
-	gpmc_onenand_data->cs = val;
-	gpmc_onenand_data->of_node = child;
-	gpmc_onenand_data->dma_channel = -1;
-
-	if (!of_property_read_u32(child, "dma-channel", &val))
-		gpmc_onenand_data->dma_channel = val;
-
-	return gpmc_onenand_init(gpmc_onenand_data);
-}
-#else
-static int gpmc_probe_onenand_child(struct platform_device *pdev,
-				    struct device_node *child)
-{
-	return 0;
-}
-#endif
-
 /**
  * gpmc_probe_generic_child - configures the gpmc for a child device
  * @pdev:	pointer to gpmc platform device
@@ -2053,6 +2123,16 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
 		}
 	}
 
+	if (of_node_cmp(child->name, "onenand") == 0) {
+		/* Warn about older DT blobs with no compatible property */
+		if (!of_property_read_bool(child, "compatible")) {
+			dev_warn(&pdev->dev,
+				 "Incompatible OneNAND node: missing compatible");
+			ret = -EINVAL;
+			goto err;
+		}
+	}
+
 	if (of_device_is_compatible(child, "ti,omap2-nand")) {
 		/* NAND specific setup */
 		val = 8;
@@ -2189,11 +2269,7 @@ static void gpmc_probe_dt_children(struct platform_device *pdev)
 		if (!child->name)
 			continue;
 
-		if (of_node_cmp(child->name, "onenand") == 0)
-			ret = gpmc_probe_onenand_child(pdev, child);
-		else
-			ret = gpmc_probe_generic_child(pdev, child);
-
+		ret = gpmc_probe_generic_child(pdev, child);
 		if (ret) {
 			dev_err(&pdev->dev, "failed to probe DT child '%s': %d\n",
 				child->name, ret);
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
index edfa280c3d56..053feb41510a 100644
--- a/include/linux/omap-gpmc.h
+++ b/include/linux/omap-gpmc.h
@@ -25,15 +25,43 @@ struct gpmc_nand_ops {
 
 struct gpmc_nand_regs;
 
+struct gpmc_onenand_info {
+	bool sync_read;
+	bool sync_write;
+	int burst_len;
+};
+
 #if IS_ENABLED(CONFIG_OMAP_GPMC)
 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *regs,
 					     int cs);
+/**
+ * gpmc_omap_onenand_set_timings - set optimized sync timings.
+ * @cs:      Chip Select Region
+ * @freq:    Chip frequency
+ * @latency: Burst latency cycle count
+ * @info:    Structure describing parameters used
+ *
+ * Sets optimized timings for the @cs region based on @freq and @latency.
+ * Updates the @info structure based on the GPMC settings.
+ */
+int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
+				  int latency,
+				  struct gpmc_onenand_info *info);
+
 #else
 static inline struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *regs,
 							   int cs)
 {
 	return NULL;
 }
+
+static inline
+int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
+				  int latency,
+				  struct gpmc_onenand_info *info)
+{
+	return -EINVAL;
+}
 #endif /* CONFIG_OMAP_GPMC */
 
 extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
-- 
2.11.0

[PATCH v5 14/16] mtd: onenand: omap2: Configure driver from DT

[Ladislav Michl]

Move away from platform data configuration and use pure DT approach.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5:
- rename ready_gpiod to int_gpiod
- use int-gpios as property name
- use devm_ioremap_resource
- "onenand" is now requested irq name
- add Kconfig dependencies

Changes in v4: None
Changes in v3:
- remove 'ti,omap3-onenand' compatible as it is not needed anymore

Changes in v2:
- move cleanups into separate patches
- simplify dma setup
- fix checkpatch error
- print info about otimized timings in sync mode only

 drivers/mtd/onenand/Kconfig |   3 +-
 drivers/mtd/onenand/omap2.c | 250 +++++++++++++++++++++++++++-----------------
 2 files changed, 155 insertions(+), 98 deletions(-)

diff --git a/drivers/mtd/onenand/Kconfig b/drivers/mtd/onenand/Kconfig
index aaeb30458139..9ec5f8757a1e 100644
--- a/drivers/mtd/onenand/Kconfig
+++ b/drivers/mtd/onenand/Kconfig
@@ -25,8 +25,9 @@ config MTD_ONENAND_GENERIC
 config MTD_ONENAND_OMAP2
 	tristate "OneNAND on OMAP2/OMAP3 support"
 	depends on ARCH_OMAP2 || ARCH_OMAP3
+	depends on (OF && GPIOLIB && DMA_ENGINE) || COMPILE_TEST
 	help
-	  Support for a OneNAND flash device connected to an OMAP2/OMAP3 CPU
+	  Support for a OneNAND flash device connected to an OMAP2/OMAP3 SoC
 	  via the GPMC memory controller.
 
 config MTD_ONENAND_SAMSUNG
diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 1cd78a076759..2ce73fb6da1c 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -28,6 +28,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/onenand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/of_device.h>
+#include <linux/omap-gpmc.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/delay.h>
@@ -35,10 +37,9 @@
 #include <linux/dmaengine.h>
 #include <linux/io.h>
 #include <linux/slab.h>
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 
 #include <asm/mach/flash.h>
-#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #define DRIVER_NAME "omap2-onenand"
 
@@ -48,15 +49,12 @@ struct omap2_onenand {
 	struct platform_device *pdev;
 	int gpmc_cs;
 	unsigned long phys_base;
-	unsigned int mem_size;
-	int gpio_irq;
+	struct gpio_desc *int_gpiod;
 	struct mtd_info mtd;
 	struct onenand_chip onenand;
 	struct completion irq_done;
 	struct completion dma_done;
 	struct dma_chan *dma_chan;
-	int freq;
-	int (*setup)(void __iomem *base, int *freq_ptr);
 };
 
 static void omap2_onenand_dma_complete_func(void *completion)
@@ -84,6 +82,65 @@ static inline void write_reg(struct omap2_onenand *c, unsigned short value,
 	writew(value, c->onenand.base + reg);
 }
 
+static int omap2_onenand_set_cfg(struct omap2_onenand *c,
+				 bool sr, bool sw,
+				 int latency, int burst_len)
+{
+	unsigned short reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
+
+	reg |= latency << ONENAND_SYS_CFG1_BRL_SHIFT;
+
+	switch (burst_len) {
+	case 0:		/* continuous */
+		break;
+	case 4:
+		reg |= ONENAND_SYS_CFG1_BL_4;
+		break;
+	case 8:
+		reg |= ONENAND_SYS_CFG1_BL_8;
+		break;
+	case 16:
+		reg |= ONENAND_SYS_CFG1_BL_16;
+		break;
+	case 32:
+		reg |= ONENAND_SYS_CFG1_BL_32;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (latency > 5)
+		reg |= ONENAND_SYS_CFG1_HF;
+	if (latency > 7)
+		reg |= ONENAND_SYS_CFG1_VHF;
+	if (sr)
+		reg |= ONENAND_SYS_CFG1_SYNC_READ;
+	if (sw)
+		reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
+
+	write_reg(c, reg, ONENAND_REG_SYS_CFG1);
+
+	return 0;
+}
+
+static int omap2_onenand_get_freq(int ver)
+{
+	switch ((ver >> 4) & 0xf) {
+	case 0:
+		return 40;
+	case 1:
+		return 54;
+	case 2:
+		return 66;
+	case 3:
+		return 83;
+	case 4:
+		return 104;
+	}
+
+	return -EINVAL;
+}
+
 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
 {
 	printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
@@ -152,12 +209,12 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 		}
 
 		reinit_completion(&c->irq_done);
-		result = gpio_get_value(c->gpio_irq);
+		result = gpiod_get_value(c->int_gpiod);
 		if (result < 0) {
 			ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 			intr = read_reg(c, ONENAND_REG_INTERRUPT);
 			wait_err("gpio error", state, ctrl, intr);
-			return -EIO;
+			return result;
 		} else if (result == 0) {
 			int retry_cnt = 0;
 retry:
@@ -431,8 +488,6 @@ static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 	return 0;
 }
 
-static struct platform_driver omap2_onenand_driver;
-
 static void omap2_onenand_shutdown(struct platform_device *pdev)
 {
 	struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
@@ -446,105 +501,117 @@ static void omap2_onenand_shutdown(struct platform_device *pdev)
 
 static int omap2_onenand_probe(struct platform_device *pdev)
 {
+	u32 val;
 	dma_cap_mask_t mask;
-	struct omap_onenand_platform_data *pdata;
-	struct omap2_onenand *c;
-	struct onenand_chip *this;
-	int r;
+	int freq, latency, r;
 	struct resource *res;
+	struct omap2_onenand *c;
+	struct gpmc_onenand_info info;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "error getting memory resource\n");
+		return -EINVAL;
+	}
 
-	pdata = dev_get_platdata(&pdev->dev);
-	if (pdata == NULL) {
-		dev_err(&pdev->dev, "platform data missing\n");
-		return -ENODEV;
+	r = of_property_read_u32(np, "reg", &val);
+	if (r) {
+		dev_err(dev, "reg not found in DT\n");
+		return r;
 	}
 
-	c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
+	c = devm_kzalloc(dev, sizeof(struct omap2_onenand), GFP_KERNEL);
 	if (!c)
 		return -ENOMEM;
 
 	init_completion(&c->irq_done);
 	init_completion(&c->dma_done);
-	c->gpmc_cs = pdata->cs;
-	c->gpio_irq = pdata->gpio_irq;
-	if (pdata->dma_channel < 0) {
-		/* if -1, don't use DMA */
-		c->gpio_irq = 0;
-	}
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (res == NULL) {
-		r = -EINVAL;
-		dev_err(&pdev->dev, "error getting memory resource\n");
-		goto err_kfree;
-	}
-
+	c->gpmc_cs = val;
 	c->phys_base = res->start;
-	c->mem_size = resource_size(res);
-
-	if (request_mem_region(c->phys_base, c->mem_size,
-			       pdev->dev.driver->name) == NULL) {
-		dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
-						c->phys_base, c->mem_size);
-		r = -EBUSY;
-		goto err_kfree;
-	}
-	c->onenand.base = ioremap(c->phys_base, c->mem_size);
-	if (c->onenand.base == NULL) {
-		r = -ENOMEM;
-		goto err_release_mem_region;
-	}
 
-	if (pdata->onenand_setup != NULL) {
-		r = pdata->onenand_setup(c->onenand.base, &c->freq);
-		if (r < 0) {
-			dev_err(&pdev->dev, "Onenand platform setup failed: "
-				"%d\n", r);
-			goto err_iounmap;
-		}
-		c->setup = pdata->onenand_setup;
+	c->onenand.base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(c->onenand.base)) {
+		dev_err(dev, "Cannot reserve memory region at 0x%08x, size: 0x%x\n",
+			res->start, resource_size(res));
+		return PTR_ERR(c->onenand.base);
 	}
 
-	if (c->gpio_irq) {
-		if ((r = gpio_request(c->gpio_irq, "OneNAND irq")) < 0) {
-			dev_err(&pdev->dev,  "Failed to request GPIO%d for "
-				"OneNAND\n", c->gpio_irq);
-			goto err_iounmap;
-		}
-		gpio_direction_input(c->gpio_irq);
+	c->int_gpiod = devm_gpiod_get_optional(dev, "int", GPIOD_IN);
+	if (IS_ERR(c->int_gpiod)) {
+		r = PTR_ERR(c->int_gpiod);
+		/* Just try again if this happens */
+		if (r != -EPROBE_DEFER)
+			dev_err(dev, "error getting gpio: %d\n", r);
+		return r;
+	}
 
-		if ((r = request_irq(gpio_to_irq(c->gpio_irq),
-				     omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
-				     pdev->dev.driver->name, c)) < 0)
-			goto err_release_gpio;
+	if (c->int_gpiod) {
+		r = devm_request_irq(dev, gpiod_to_irq(c->int_gpiod),
+				     omap2_onenand_interrupt,
+				     IRQF_TRIGGER_RISING, "onenand", c);
+		if (r)
+			return r;
 
-		this->wait = omap2_onenand_wait;
+		c->onenand.wait = omap2_onenand_wait;
 	}
 
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_MEMCPY, mask);
 
 	c->dma_chan = dma_request_channel(mask, NULL, NULL);
-
-	dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
-		 "base %p, freq %d MHz, %s mode\n", c->gpmc_cs, c->phys_base,
-		 c->onenand.base, c->freq, c->dma_chan ? "DMA" : "PIO");
+	if (c->dma_chan) {
+		c->onenand.read_bufferram = omap2_onenand_read_bufferram;
+		c->onenand.write_bufferram = omap2_onenand_write_bufferram;
+	}
 
 	c->pdev = pdev;
 	c->mtd.priv = &c->onenand;
+	c->mtd.dev.parent = dev;
+	mtd_set_of_node(&c->mtd, dev->of_node);
 
-	c->mtd.dev.parent = &pdev->dev;
-	mtd_set_of_node(&c->mtd, pdata->of_node);
-
-	this = &c->onenand;
-	if (c->dma_chan) {
-		this->read_bufferram = omap2_onenand_read_bufferram;
-		this->write_bufferram = omap2_onenand_write_bufferram;
-	}
+	dev_info(dev, "initializing on CS%d (0x%08lx), va %p, %s mode\n",
+		 c->gpmc_cs, c->phys_base, c->onenand.base,
+		 c->dma_chan ? "DMA" : "PIO");
 
 	if ((r = onenand_scan(&c->mtd, 1)) < 0)
 		goto err_release_dma;
 
+	freq = omap2_onenand_get_freq(c->onenand.version_id);
+	if (freq > 0) {
+		switch (freq) {
+		case 104:
+			latency = 7;
+			break;
+		case 83:
+			latency = 6;
+			break;
+		case 66:
+			latency = 5;
+			break;
+		case 56:
+			latency = 4;
+			break;
+		default:	/* 40 MHz or lower */
+			latency = 3;
+			break;
+		}
+
+		r = gpmc_omap_onenand_set_timings(dev, c->gpmc_cs,
+						  freq, latency, &info);
+		if (r)
+			goto err_release_onenand;
+
+		r = omap2_onenand_set_cfg(c, info.sync_read, info.sync_write,
+					  latency, info.burst_len);
+		if (r)
+			goto err_release_onenand;
+
+		if (info.sync_read || info.sync_write)
+			dev_info(dev, "optimized timings for %d MHz\n", freq);
+	}
+
 	r = mtd_device_register(&c->mtd, NULL, 0);
 	if (r)
 		goto err_release_onenand;
@@ -558,17 +625,6 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 err_release_dma:
 	if (c->dma_chan)
 		dma_release_channel(c->dma_chan);
-	if (c->gpio_irq)
-		free_irq(gpio_to_irq(c->gpio_irq), c);
-err_release_gpio:
-	if (c->gpio_irq)
-		gpio_free(c->gpio_irq);
-err_iounmap:
-	iounmap(c->onenand.base);
-err_release_mem_region:
-	release_mem_region(c->phys_base, c->mem_size);
-err_kfree:
-	kfree(c);
 
 	return r;
 }
@@ -581,23 +637,23 @@ static int omap2_onenand_remove(struct platform_device *pdev)
 	if (c->dma_chan)
 		dma_release_channel(c->dma_chan);
 	omap2_onenand_shutdown(pdev);
-	if (c->gpio_irq) {
-		free_irq(gpio_to_irq(c->gpio_irq), c);
-		gpio_free(c->gpio_irq);
-	}
-	iounmap(c->onenand.base);
-	release_mem_region(c->phys_base, c->mem_size);
-	kfree(c);
 
 	return 0;
 }
 
+static const struct of_device_id omap2_onenand_id_table[] = {
+	{ .compatible = "ti,omap2-onenand", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, omap2_onenand_id_table);
+
 static struct platform_driver omap2_onenand_driver = {
 	.probe		= omap2_onenand_probe,
 	.remove		= omap2_onenand_remove,
 	.shutdown	= omap2_onenand_shutdown,
 	.driver		= {
 		.name	= DRIVER_NAME,
+		.of_match_table = omap2_onenand_id_table,
 	},
 };
 
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 14/16] mtd: onenand: omap2: Configure driver from DT

[Ladislav Michl]

Move away from platform data configuration and use pure DT approach.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5:
- rename ready_gpiod to int_gpiod
- use int-gpios as property name
- use devm_ioremap_resource
- "onenand" is now requested irq name
- add Kconfig dependencies

Changes in v4: None
Changes in v3:
- remove 'ti,omap3-onenand' compatible as it is not needed anymore

Changes in v2:
- move cleanups into separate patches
- simplify dma setup
- fix checkpatch error
- print info about otimized timings in sync mode only

 drivers/mtd/onenand/Kconfig |   3 +-
 drivers/mtd/onenand/omap2.c | 250 +++++++++++++++++++++++++++-----------------
 2 files changed, 155 insertions(+), 98 deletions(-)

diff --git a/drivers/mtd/onenand/Kconfig b/drivers/mtd/onenand/Kconfig
index aaeb30458139..9ec5f8757a1e 100644
--- a/drivers/mtd/onenand/Kconfig
+++ b/drivers/mtd/onenand/Kconfig
@@ -25,8 +25,9 @@ config MTD_ONENAND_GENERIC
 config MTD_ONENAND_OMAP2
 	tristate "OneNAND on OMAP2/OMAP3 support"
 	depends on ARCH_OMAP2 || ARCH_OMAP3
+	depends on (OF && GPIOLIB && DMA_ENGINE) || COMPILE_TEST
 	help
-	  Support for a OneNAND flash device connected to an OMAP2/OMAP3 CPU
+	  Support for a OneNAND flash device connected to an OMAP2/OMAP3 SoC
 	  via the GPMC memory controller.
 
 config MTD_ONENAND_SAMSUNG
diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 1cd78a076759..2ce73fb6da1c 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -28,6 +28,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/onenand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/of_device.h>
+#include <linux/omap-gpmc.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/delay.h>
@@ -35,10 +37,9 @@
 #include <linux/dmaengine.h>
 #include <linux/io.h>
 #include <linux/slab.h>
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 
 #include <asm/mach/flash.h>
-#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #define DRIVER_NAME "omap2-onenand"
 
@@ -48,15 +49,12 @@ struct omap2_onenand {
 	struct platform_device *pdev;
 	int gpmc_cs;
 	unsigned long phys_base;
-	unsigned int mem_size;
-	int gpio_irq;
+	struct gpio_desc *int_gpiod;
 	struct mtd_info mtd;
 	struct onenand_chip onenand;
 	struct completion irq_done;
 	struct completion dma_done;
 	struct dma_chan *dma_chan;
-	int freq;
-	int (*setup)(void __iomem *base, int *freq_ptr);
 };
 
 static void omap2_onenand_dma_complete_func(void *completion)
@@ -84,6 +82,65 @@ static inline void write_reg(struct omap2_onenand *c, unsigned short value,
 	writew(value, c->onenand.base + reg);
 }
 
+static int omap2_onenand_set_cfg(struct omap2_onenand *c,
+				 bool sr, bool sw,
+				 int latency, int burst_len)
+{
+	unsigned short reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
+
+	reg |= latency << ONENAND_SYS_CFG1_BRL_SHIFT;
+
+	switch (burst_len) {
+	case 0:		/* continuous */
+		break;
+	case 4:
+		reg |= ONENAND_SYS_CFG1_BL_4;
+		break;
+	case 8:
+		reg |= ONENAND_SYS_CFG1_BL_8;
+		break;
+	case 16:
+		reg |= ONENAND_SYS_CFG1_BL_16;
+		break;
+	case 32:
+		reg |= ONENAND_SYS_CFG1_BL_32;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (latency > 5)
+		reg |= ONENAND_SYS_CFG1_HF;
+	if (latency > 7)
+		reg |= ONENAND_SYS_CFG1_VHF;
+	if (sr)
+		reg |= ONENAND_SYS_CFG1_SYNC_READ;
+	if (sw)
+		reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
+
+	write_reg(c, reg, ONENAND_REG_SYS_CFG1);
+
+	return 0;
+}
+
+static int omap2_onenand_get_freq(int ver)
+{
+	switch ((ver >> 4) & 0xf) {
+	case 0:
+		return 40;
+	case 1:
+		return 54;
+	case 2:
+		return 66;
+	case 3:
+		return 83;
+	case 4:
+		return 104;
+	}
+
+	return -EINVAL;
+}
+
 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
 {
 	printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
@@ -152,12 +209,12 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 		}
 
 		reinit_completion(&c->irq_done);
-		result = gpio_get_value(c->gpio_irq);
+		result = gpiod_get_value(c->int_gpiod);
 		if (result < 0) {
 			ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 			intr = read_reg(c, ONENAND_REG_INTERRUPT);
 			wait_err("gpio error", state, ctrl, intr);
-			return -EIO;
+			return result;
 		} else if (result == 0) {
 			int retry_cnt = 0;
 retry:
@@ -431,8 +488,6 @@ static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 	return 0;
 }
 
-static struct platform_driver omap2_onenand_driver;
-
 static void omap2_onenand_shutdown(struct platform_device *pdev)
 {
 	struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
@@ -446,105 +501,117 @@ static void omap2_onenand_shutdown(struct platform_device *pdev)
 
 static int omap2_onenand_probe(struct platform_device *pdev)
 {
+	u32 val;
 	dma_cap_mask_t mask;
-	struct omap_onenand_platform_data *pdata;
-	struct omap2_onenand *c;
-	struct onenand_chip *this;
-	int r;
+	int freq, latency, r;
 	struct resource *res;
+	struct omap2_onenand *c;
+	struct gpmc_onenand_info info;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "error getting memory resource\n");
+		return -EINVAL;
+	}
 
-	pdata = dev_get_platdata(&pdev->dev);
-	if (pdata == NULL) {
-		dev_err(&pdev->dev, "platform data missing\n");
-		return -ENODEV;
+	r = of_property_read_u32(np, "reg", &val);
+	if (r) {
+		dev_err(dev, "reg not found in DT\n");
+		return r;
 	}
 
-	c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
+	c = devm_kzalloc(dev, sizeof(struct omap2_onenand), GFP_KERNEL);
 	if (!c)
 		return -ENOMEM;
 
 	init_completion(&c->irq_done);
 	init_completion(&c->dma_done);
-	c->gpmc_cs = pdata->cs;
-	c->gpio_irq = pdata->gpio_irq;
-	if (pdata->dma_channel < 0) {
-		/* if -1, don't use DMA */
-		c->gpio_irq = 0;
-	}
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (res == NULL) {
-		r = -EINVAL;
-		dev_err(&pdev->dev, "error getting memory resource\n");
-		goto err_kfree;
-	}
-
+	c->gpmc_cs = val;
 	c->phys_base = res->start;
-	c->mem_size = resource_size(res);
-
-	if (request_mem_region(c->phys_base, c->mem_size,
-			       pdev->dev.driver->name) == NULL) {
-		dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
-						c->phys_base, c->mem_size);
-		r = -EBUSY;
-		goto err_kfree;
-	}
-	c->onenand.base = ioremap(c->phys_base, c->mem_size);
-	if (c->onenand.base == NULL) {
-		r = -ENOMEM;
-		goto err_release_mem_region;
-	}
 
-	if (pdata->onenand_setup != NULL) {
-		r = pdata->onenand_setup(c->onenand.base, &c->freq);
-		if (r < 0) {
-			dev_err(&pdev->dev, "Onenand platform setup failed: "
-				"%d\n", r);
-			goto err_iounmap;
-		}
-		c->setup = pdata->onenand_setup;
+	c->onenand.base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(c->onenand.base)) {
+		dev_err(dev, "Cannot reserve memory region at 0x%08x, size: 0x%x\n",
+			res->start, resource_size(res));
+		return PTR_ERR(c->onenand.base);
 	}
 
-	if (c->gpio_irq) {
-		if ((r = gpio_request(c->gpio_irq, "OneNAND irq")) < 0) {
-			dev_err(&pdev->dev,  "Failed to request GPIO%d for "
-				"OneNAND\n", c->gpio_irq);
-			goto err_iounmap;
-		}
-		gpio_direction_input(c->gpio_irq);
+	c->int_gpiod = devm_gpiod_get_optional(dev, "int", GPIOD_IN);
+	if (IS_ERR(c->int_gpiod)) {
+		r = PTR_ERR(c->int_gpiod);
+		/* Just try again if this happens */
+		if (r != -EPROBE_DEFER)
+			dev_err(dev, "error getting gpio: %d\n", r);
+		return r;
+	}
 
-		if ((r = request_irq(gpio_to_irq(c->gpio_irq),
-				     omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
-				     pdev->dev.driver->name, c)) < 0)
-			goto err_release_gpio;
+	if (c->int_gpiod) {
+		r = devm_request_irq(dev, gpiod_to_irq(c->int_gpiod),
+				     omap2_onenand_interrupt,
+				     IRQF_TRIGGER_RISING, "onenand", c);
+		if (r)
+			return r;
 
-		this->wait = omap2_onenand_wait;
+		c->onenand.wait = omap2_onenand_wait;
 	}
 
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_MEMCPY, mask);
 
 	c->dma_chan = dma_request_channel(mask, NULL, NULL);
-
-	dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
-		 "base %p, freq %d MHz, %s mode\n", c->gpmc_cs, c->phys_base,
-		 c->onenand.base, c->freq, c->dma_chan ? "DMA" : "PIO");
+	if (c->dma_chan) {
+		c->onenand.read_bufferram = omap2_onenand_read_bufferram;
+		c->onenand.write_bufferram = omap2_onenand_write_bufferram;
+	}
 
 	c->pdev = pdev;
 	c->mtd.priv = &c->onenand;
+	c->mtd.dev.parent = dev;
+	mtd_set_of_node(&c->mtd, dev->of_node);
 
-	c->mtd.dev.parent = &pdev->dev;
-	mtd_set_of_node(&c->mtd, pdata->of_node);
-
-	this = &c->onenand;
-	if (c->dma_chan) {
-		this->read_bufferram = omap2_onenand_read_bufferram;
-		this->write_bufferram = omap2_onenand_write_bufferram;
-	}
+	dev_info(dev, "initializing on CS%d (0x%08lx), va %p, %s mode\n",
+		 c->gpmc_cs, c->phys_base, c->onenand.base,
+		 c->dma_chan ? "DMA" : "PIO");
 
 	if ((r = onenand_scan(&c->mtd, 1)) < 0)
 		goto err_release_dma;
 
+	freq = omap2_onenand_get_freq(c->onenand.version_id);
+	if (freq > 0) {
+		switch (freq) {
+		case 104:
+			latency = 7;
+			break;
+		case 83:
+			latency = 6;
+			break;
+		case 66:
+			latency = 5;
+			break;
+		case 56:
+			latency = 4;
+			break;
+		default:	/* 40 MHz or lower */
+			latency = 3;
+			break;
+		}
+
+		r = gpmc_omap_onenand_set_timings(dev, c->gpmc_cs,
+						  freq, latency, &info);
+		if (r)
+			goto err_release_onenand;
+
+		r = omap2_onenand_set_cfg(c, info.sync_read, info.sync_write,
+					  latency, info.burst_len);
+		if (r)
+			goto err_release_onenand;
+
+		if (info.sync_read || info.sync_write)
+			dev_info(dev, "optimized timings for %d MHz\n", freq);
+	}
+
 	r = mtd_device_register(&c->mtd, NULL, 0);
 	if (r)
 		goto err_release_onenand;
@@ -558,17 +625,6 @@ static int omap2_onenand_probe(struct platform_device *pdev)
 err_release_dma:
 	if (c->dma_chan)
 		dma_release_channel(c->dma_chan);
-	if (c->gpio_irq)
-		free_irq(gpio_to_irq(c->gpio_irq), c);
-err_release_gpio:
-	if (c->gpio_irq)
-		gpio_free(c->gpio_irq);
-err_iounmap:
-	iounmap(c->onenand.base);
-err_release_mem_region:
-	release_mem_region(c->phys_base, c->mem_size);
-err_kfree:
-	kfree(c);
 
 	return r;
 }
@@ -581,23 +637,23 @@ static int omap2_onenand_remove(struct platform_device *pdev)
 	if (c->dma_chan)
 		dma_release_channel(c->dma_chan);
 	omap2_onenand_shutdown(pdev);
-	if (c->gpio_irq) {
-		free_irq(gpio_to_irq(c->gpio_irq), c);
-		gpio_free(c->gpio_irq);
-	}
-	iounmap(c->onenand.base);
-	release_mem_region(c->phys_base, c->mem_size);
-	kfree(c);
 
 	return 0;
 }
 
+static const struct of_device_id omap2_onenand_id_table[] = {
+	{ .compatible = "ti,omap2-onenand", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, omap2_onenand_id_table);
+
 static struct platform_driver omap2_onenand_driver = {
 	.probe		= omap2_onenand_probe,
 	.remove		= omap2_onenand_remove,
 	.shutdown	= omap2_onenand_shutdown,
 	.driver		= {
 		.name	= DRIVER_NAME,
+		.of_match_table = omap2_onenand_id_table,
 	},
 };
 
-- 
2.11.0

[PATCH v5 15/16] ARM: OMAP2+: Remove gpmc-onenand

[Ladislav Michl]

As OneNAND driver is now using devicetree, gpmc-onenand and its
platform data is unused and can be removed.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 arch/arm/mach-omap2/Makefile                    |   3 -
 arch/arm/mach-omap2/gpmc-onenand.c              | 409 ------------------------
 include/linux/platform_data/mtd-onenand-omap2.h |  34 --
 3 files changed, 446 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/gpmc-onenand.c
 delete mode 100644 include/linux/platform_data/mtd-onenand-omap2.h

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 38f1748a4500..e0306d3df41a 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -235,6 +235,3 @@ obj-y					+= $(omap-hsmmc-m) $(omap-hsmmc-y)
 obj-y					+= omap_phy_internal.o
 
 obj-$(CONFIG_MACH_OMAP2_TUSB6010)	+= usb-tusb6010.o
-
-onenand-$(CONFIG_MTD_ONENAND_OMAP2)	:= gpmc-onenand.o
-obj-y					+= $(onenand-m) $(onenand-y)
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
deleted file mode 100644
index 2944af820558..000000000000
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/gpmc-onenand.c
- *
- * Copyright (C) 2006 - 2009 Nokia Corporation
- * Contacts:	Juha Yrjola
- *		Tony Lindgren
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/onenand_regs.h>
-#include <linux/io.h>
-#include <linux/omap-gpmc.h>
-#include <linux/platform_data/mtd-onenand-omap2.h>
-#include <linux/err.h>
-
-#include <asm/mach/flash.h>
-
-#include "soc.h"
-
-#define	ONENAND_IO_SIZE	SZ_128K
-
-#define	ONENAND_FLAG_SYNCREAD	(1 << 0)
-#define	ONENAND_FLAG_SYNCWRITE	(1 << 1)
-#define	ONENAND_FLAG_HF		(1 << 2)
-#define	ONENAND_FLAG_VHF	(1 << 3)
-
-static unsigned onenand_flags;
-static unsigned latency;
-
-static struct omap_onenand_platform_data *gpmc_onenand_data;
-
-static struct resource gpmc_onenand_resource = {
-	.flags		= IORESOURCE_MEM,
-};
-
-static struct platform_device gpmc_onenand_device = {
-	.name		= "omap2-onenand",
-	.id		= -1,
-	.num_resources	= 1,
-	.resource	= &gpmc_onenand_resource,
-};
-
-static struct gpmc_settings onenand_async = {
-	.device_width	= GPMC_DEVWIDTH_16BIT,
-	.mux_add_data	= GPMC_MUX_AD,
-};
-
-static struct gpmc_settings onenand_sync = {
-	.burst_read	= true,
-	.burst_wrap	= true,
-	.burst_len	= GPMC_BURST_16,
-	.device_width	= GPMC_DEVWIDTH_16BIT,
-	.mux_add_data	= GPMC_MUX_AD,
-	.wait_pin	= 0,
-};
-
-static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
-{
-	struct gpmc_device_timings dev_t;
-	const int t_cer = 15;
-	const int t_avdp = 12;
-	const int t_aavdh = 7;
-	const int t_ce = 76;
-	const int t_aa = 76;
-	const int t_oe = 20;
-	const int t_cez = 20; /* max of t_cez, t_oez */
-	const int t_wpl = 40;
-	const int t_wph = 30;
-
-	memset(&dev_t, 0, sizeof(dev_t));
-
-	dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
-	dev_t.t_avdp_w = dev_t.t_avdp_r;
-	dev_t.t_aavdh = t_aavdh * 1000;
-	dev_t.t_aa = t_aa * 1000;
-	dev_t.t_ce = t_ce * 1000;
-	dev_t.t_oe = t_oe * 1000;
-	dev_t.t_cez_r = t_cez * 1000;
-	dev_t.t_cez_w = dev_t.t_cez_r;
-	dev_t.t_wpl = t_wpl * 1000;
-	dev_t.t_wph = t_wph * 1000;
-
-	gpmc_calc_timings(t, &onenand_async, &dev_t);
-}
-
-static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
-{
-	u32 reg;
-
-	/* Ensure sync read and sync write are disabled */
-	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
-	reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
-	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
-}
-
-static void set_onenand_cfg(void __iomem *onenand_base)
-{
-	u32 reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
-
-	reg |=	(latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
-		ONENAND_SYS_CFG1_BL_16;
-	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
-		reg |= ONENAND_SYS_CFG1_SYNC_READ;
-	else
-		reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
-	if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
-		reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
-	else
-		reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
-	if (onenand_flags & ONENAND_FLAG_HF)
-		reg |= ONENAND_SYS_CFG1_HF;
-	else
-		reg &= ~ONENAND_SYS_CFG1_HF;
-	if (onenand_flags & ONENAND_FLAG_VHF)
-		reg |= ONENAND_SYS_CFG1_VHF;
-	else
-		reg &= ~ONENAND_SYS_CFG1_VHF;
-
-	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
-}
-
-static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
-				  void __iomem *onenand_base)
-{
-	u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
-	int freq;
-
-	switch ((ver >> 4) & 0xf) {
-	case 0:
-		freq = 40;
-		break;
-	case 1:
-		freq = 54;
-		break;
-	case 2:
-		freq = 66;
-		break;
-	case 3:
-		freq = 83;
-		break;
-	case 4:
-		freq = 104;
-		break;
-	default:
-		pr_err("onenand rate not detected, bad GPMC async timings?\n");
-		freq = 0;
-	}
-
-	return freq;
-}
-
-static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
-					    unsigned int flags,
-					    int freq)
-{
-	struct gpmc_device_timings dev_t;
-	const int t_cer  = 15;
-	const int t_avdp = 12;
-	const int t_cez  = 20; /* max of t_cez, t_oez */
-	const int t_wpl  = 40;
-	const int t_wph  = 30;
-	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
-	int div, gpmc_clk_ns;
-
-	if (flags & ONENAND_SYNC_READ)
-		onenand_flags = ONENAND_FLAG_SYNCREAD;
-	else if (flags & ONENAND_SYNC_READWRITE)
-		onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
-
-	switch (freq) {
-	case 104:
-		min_gpmc_clk_period = 9600; /* 104 MHz */
-		t_ces   = 3;
-		t_avds  = 4;
-		t_avdh  = 2;
-		t_ach   = 3;
-		t_aavdh = 6;
-		t_rdyo  = 6;
-		break;
-	case 83:
-		min_gpmc_clk_period = 12000; /* 83 MHz */
-		t_ces   = 5;
-		t_avds  = 4;
-		t_avdh  = 2;
-		t_ach   = 6;
-		t_aavdh = 6;
-		t_rdyo  = 9;
-		break;
-	case 66:
-		min_gpmc_clk_period = 15000; /* 66 MHz */
-		t_ces   = 6;
-		t_avds  = 5;
-		t_avdh  = 2;
-		t_ach   = 6;
-		t_aavdh = 6;
-		t_rdyo  = 11;
-		break;
-	default:
-		min_gpmc_clk_period = 18500; /* 54 MHz */
-		t_ces   = 7;
-		t_avds  = 7;
-		t_avdh  = 7;
-		t_ach   = 9;
-		t_aavdh = 7;
-		t_rdyo  = 15;
-		onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
-		break;
-	}
-
-	div = gpmc_calc_divider(min_gpmc_clk_period);
-	gpmc_clk_ns = gpmc_ticks_to_ns(div);
-	if (gpmc_clk_ns < 15) /* >66MHz */
-		onenand_flags |= ONENAND_FLAG_HF;
-	else
-		onenand_flags &= ~ONENAND_FLAG_HF;
-	if (gpmc_clk_ns < 12) /* >83MHz */
-		onenand_flags |= ONENAND_FLAG_VHF;
-	else
-		onenand_flags &= ~ONENAND_FLAG_VHF;
-	if (onenand_flags & ONENAND_FLAG_VHF)
-		latency = 8;
-	else if (onenand_flags & ONENAND_FLAG_HF)
-		latency = 6;
-	else if (gpmc_clk_ns >= 25) /* 40 MHz*/
-		latency = 3;
-	else
-		latency = 4;
-
-	/* Set synchronous read timings */
-	memset(&dev_t, 0, sizeof(dev_t));
-
-	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
-		onenand_sync.sync_read = true;
-	if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
-		onenand_sync.sync_write = true;
-		onenand_sync.burst_write = true;
-	} else {
-		dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
-		dev_t.t_wpl = t_wpl * 1000;
-		dev_t.t_wph = t_wph * 1000;
-		dev_t.t_aavdh = t_aavdh * 1000;
-	}
-	dev_t.ce_xdelay = true;
-	dev_t.avd_xdelay = true;
-	dev_t.oe_xdelay = true;
-	dev_t.we_xdelay = true;
-	dev_t.clk = min_gpmc_clk_period;
-	dev_t.t_bacc = dev_t.clk;
-	dev_t.t_ces = t_ces * 1000;
-	dev_t.t_avds = t_avds * 1000;
-	dev_t.t_avdh = t_avdh * 1000;
-	dev_t.t_ach = t_ach * 1000;
-	dev_t.cyc_iaa = (latency + 1);
-	dev_t.t_cez_r = t_cez * 1000;
-	dev_t.t_cez_w = dev_t.t_cez_r;
-	dev_t.cyc_aavdh_oe = 1;
-	dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
-
-	gpmc_calc_timings(t, &onenand_sync, &dev_t);
-}
-
-static int omap2_onenand_setup_async(void __iomem *onenand_base)
-{
-	struct gpmc_timings t;
-	int ret;
-
-	/*
-	 * Note that we need to keep sync_write set for the call to
-	 * omap2_onenand_set_async_mode() to work to detect the onenand
-	 * supported clock rate for the sync timings.
-	 */
-	if (gpmc_onenand_data->of_node) {
-		gpmc_read_settings_dt(gpmc_onenand_data->of_node,
-				      &onenand_async);
-		if (onenand_async.sync_read || onenand_async.sync_write) {
-			if (onenand_async.sync_write)
-				gpmc_onenand_data->flags |=
-					ONENAND_SYNC_READWRITE;
-			else
-				gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
-			onenand_async.sync_read = false;
-		}
-	}
-
-	onenand_async.sync_write = true;
-	omap2_onenand_calc_async_timings(&t);
-
-	ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
-	if (ret < 0)
-		return ret;
-
-	ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_async);
-	if (ret < 0)
-		return ret;
-
-	omap2_onenand_set_async_mode(onenand_base);
-
-	return 0;
-}
-
-static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
-{
-	int ret, freq = *freq_ptr;
-	struct gpmc_timings t;
-
-	if (!freq) {
-		/* Very first call freq is not known */
-		freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
-		if (!freq)
-			return -ENODEV;
-		set_onenand_cfg(onenand_base);
-	}
-
-	if (gpmc_onenand_data->of_node) {
-		gpmc_read_settings_dt(gpmc_onenand_data->of_node,
-				      &onenand_sync);
-	} else {
-		/*
-		 * FIXME: Appears to be legacy code from initial ONENAND commit.
-		 * Unclear what boards this is for and if this can be removed.
-		 */
-		if (!cpu_is_omap34xx())
-			onenand_sync.wait_on_read = true;
-	}
-
-	omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
-
-	ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
-	if (ret < 0)
-		return ret;
-
-	ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_sync);
-	if (ret < 0)
-		return ret;
-
-	set_onenand_cfg(onenand_base);
-
-	*freq_ptr = freq;
-
-	return 0;
-}
-
-static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
-{
-	struct device *dev = &gpmc_onenand_device.dev;
-	unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
-	int ret;
-
-	ret = omap2_onenand_setup_async(onenand_base);
-	if (ret) {
-		dev_err(dev, "unable to set to async mode\n");
-		return ret;
-	}
-
-	if (!(gpmc_onenand_data->flags & l))
-		return 0;
-
-	ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
-	if (ret)
-		dev_err(dev, "unable to set to sync mode\n");
-	return ret;
-}
-
-int gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
-{
-	int err;
-	struct device *dev = &gpmc_onenand_device.dev;
-
-	gpmc_onenand_data = _onenand_data;
-	gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
-	gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
-
-	if (cpu_is_omap24xx() &&
-			(gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
-		dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
-		gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
-		gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
-	}
-
-	if (cpu_is_omap34xx())
-		gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
-	else
-		gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
-
-	err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
-				(unsigned long *)&gpmc_onenand_resource.start);
-	if (err < 0) {
-		dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
-			gpmc_onenand_data->cs, err);
-		return err;
-	}
-
-	gpmc_onenand_resource.end = gpmc_onenand_resource.start +
-							ONENAND_IO_SIZE - 1;
-
-	err = platform_device_register(&gpmc_onenand_device);
-	if (err) {
-		dev_err(dev, "Unable to register OneNAND device\n");
-		gpmc_cs_free(gpmc_onenand_data->cs);
-	}
-
-	return err;
-}
diff --git a/include/linux/platform_data/mtd-onenand-omap2.h b/include/linux/platform_data/mtd-onenand-omap2.h
deleted file mode 100644
index 56ff0e6f5ad1..000000000000
--- a/include/linux/platform_data/mtd-onenand-omap2.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (C) 2006 Nokia Corporation
- * Author: Juha Yrjola
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef	__MTD_ONENAND_OMAP2_H
-#define	__MTD_ONENAND_OMAP2_H
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
-#define ONENAND_SYNC_READ	(1 << 0)
-#define ONENAND_SYNC_READWRITE	(1 << 1)
-#define	ONENAND_IN_OMAP34XX	(1 << 2)
-
-struct omap_onenand_platform_data {
-	int			cs;
-	int			gpio_irq;
-	struct mtd_partition	*parts;
-	int			nr_parts;
-	int			(*onenand_setup)(void __iomem *, int *freq_ptr);
-	int			dma_channel;
-	u8			flags;
-	u8			regulator_can_sleep;
-	u8			skip_initial_unlocking;
-
-	/* for passing the partitions */
-	struct device_node	*of_node;
-};
-#endif
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 15/16] ARM: OMAP2+: Remove gpmc-onenand

[Ladislav Michl]

As OneNAND driver is now using devicetree, gpmc-onenand and its
platform data is unused and can be removed.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Tony Lindgren <tony@atomide.com>
---

Changes in v5: None
Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 arch/arm/mach-omap2/Makefile                    |   3 -
 arch/arm/mach-omap2/gpmc-onenand.c              | 409 ------------------------
 include/linux/platform_data/mtd-onenand-omap2.h |  34 --
 3 files changed, 446 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/gpmc-onenand.c
 delete mode 100644 include/linux/platform_data/mtd-onenand-omap2.h

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 38f1748a4500..e0306d3df41a 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -235,6 +235,3 @@ obj-y					+= $(omap-hsmmc-m) $(omap-hsmmc-y)
 obj-y					+= omap_phy_internal.o
 
 obj-$(CONFIG_MACH_OMAP2_TUSB6010)	+= usb-tusb6010.o
-
-onenand-$(CONFIG_MTD_ONENAND_OMAP2)	:= gpmc-onenand.o
-obj-y					+= $(onenand-m) $(onenand-y)
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
deleted file mode 100644
index 2944af820558..000000000000
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/gpmc-onenand.c
- *
- * Copyright (C) 2006 - 2009 Nokia Corporation
- * Contacts:	Juha Yrjola
- *		Tony Lindgren
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/onenand_regs.h>
-#include <linux/io.h>
-#include <linux/omap-gpmc.h>
-#include <linux/platform_data/mtd-onenand-omap2.h>
-#include <linux/err.h>
-
-#include <asm/mach/flash.h>
-
-#include "soc.h"
-
-#define	ONENAND_IO_SIZE	SZ_128K
-
-#define	ONENAND_FLAG_SYNCREAD	(1 << 0)
-#define	ONENAND_FLAG_SYNCWRITE	(1 << 1)
-#define	ONENAND_FLAG_HF		(1 << 2)
-#define	ONENAND_FLAG_VHF	(1 << 3)
-
-static unsigned onenand_flags;
-static unsigned latency;
-
-static struct omap_onenand_platform_data *gpmc_onenand_data;
-
-static struct resource gpmc_onenand_resource = {
-	.flags		= IORESOURCE_MEM,
-};
-
-static struct platform_device gpmc_onenand_device = {
-	.name		= "omap2-onenand",
-	.id		= -1,
-	.num_resources	= 1,
-	.resource	= &gpmc_onenand_resource,
-};
-
-static struct gpmc_settings onenand_async = {
-	.device_width	= GPMC_DEVWIDTH_16BIT,
-	.mux_add_data	= GPMC_MUX_AD,
-};
-
-static struct gpmc_settings onenand_sync = {
-	.burst_read	= true,
-	.burst_wrap	= true,
-	.burst_len	= GPMC_BURST_16,
-	.device_width	= GPMC_DEVWIDTH_16BIT,
-	.mux_add_data	= GPMC_MUX_AD,
-	.wait_pin	= 0,
-};
-
-static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
-{
-	struct gpmc_device_timings dev_t;
-	const int t_cer = 15;
-	const int t_avdp = 12;
-	const int t_aavdh = 7;
-	const int t_ce = 76;
-	const int t_aa = 76;
-	const int t_oe = 20;
-	const int t_cez = 20; /* max of t_cez, t_oez */
-	const int t_wpl = 40;
-	const int t_wph = 30;
-
-	memset(&dev_t, 0, sizeof(dev_t));
-
-	dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
-	dev_t.t_avdp_w = dev_t.t_avdp_r;
-	dev_t.t_aavdh = t_aavdh * 1000;
-	dev_t.t_aa = t_aa * 1000;
-	dev_t.t_ce = t_ce * 1000;
-	dev_t.t_oe = t_oe * 1000;
-	dev_t.t_cez_r = t_cez * 1000;
-	dev_t.t_cez_w = dev_t.t_cez_r;
-	dev_t.t_wpl = t_wpl * 1000;
-	dev_t.t_wph = t_wph * 1000;
-
-	gpmc_calc_timings(t, &onenand_async, &dev_t);
-}
-
-static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
-{
-	u32 reg;
-
-	/* Ensure sync read and sync write are disabled */
-	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
-	reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
-	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
-}
-
-static void set_onenand_cfg(void __iomem *onenand_base)
-{
-	u32 reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
-
-	reg |=	(latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
-		ONENAND_SYS_CFG1_BL_16;
-	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
-		reg |= ONENAND_SYS_CFG1_SYNC_READ;
-	else
-		reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
-	if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
-		reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
-	else
-		reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
-	if (onenand_flags & ONENAND_FLAG_HF)
-		reg |= ONENAND_SYS_CFG1_HF;
-	else
-		reg &= ~ONENAND_SYS_CFG1_HF;
-	if (onenand_flags & ONENAND_FLAG_VHF)
-		reg |= ONENAND_SYS_CFG1_VHF;
-	else
-		reg &= ~ONENAND_SYS_CFG1_VHF;
-
-	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
-}
-
-static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
-				  void __iomem *onenand_base)
-{
-	u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
-	int freq;
-
-	switch ((ver >> 4) & 0xf) {
-	case 0:
-		freq = 40;
-		break;
-	case 1:
-		freq = 54;
-		break;
-	case 2:
-		freq = 66;
-		break;
-	case 3:
-		freq = 83;
-		break;
-	case 4:
-		freq = 104;
-		break;
-	default:
-		pr_err("onenand rate not detected, bad GPMC async timings?\n");
-		freq = 0;
-	}
-
-	return freq;
-}
-
-static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
-					    unsigned int flags,
-					    int freq)
-{
-	struct gpmc_device_timings dev_t;
-	const int t_cer  = 15;
-	const int t_avdp = 12;
-	const int t_cez  = 20; /* max of t_cez, t_oez */
-	const int t_wpl  = 40;
-	const int t_wph  = 30;
-	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
-	int div, gpmc_clk_ns;
-
-	if (flags & ONENAND_SYNC_READ)
-		onenand_flags = ONENAND_FLAG_SYNCREAD;
-	else if (flags & ONENAND_SYNC_READWRITE)
-		onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
-
-	switch (freq) {
-	case 104:
-		min_gpmc_clk_period = 9600; /* 104 MHz */
-		t_ces   = 3;
-		t_avds  = 4;
-		t_avdh  = 2;
-		t_ach   = 3;
-		t_aavdh = 6;
-		t_rdyo  = 6;
-		break;
-	case 83:
-		min_gpmc_clk_period = 12000; /* 83 MHz */
-		t_ces   = 5;
-		t_avds  = 4;
-		t_avdh  = 2;
-		t_ach   = 6;
-		t_aavdh = 6;
-		t_rdyo  = 9;
-		break;
-	case 66:
-		min_gpmc_clk_period = 15000; /* 66 MHz */
-		t_ces   = 6;
-		t_avds  = 5;
-		t_avdh  = 2;
-		t_ach   = 6;
-		t_aavdh = 6;
-		t_rdyo  = 11;
-		break;
-	default:
-		min_gpmc_clk_period = 18500; /* 54 MHz */
-		t_ces   = 7;
-		t_avds  = 7;
-		t_avdh  = 7;
-		t_ach   = 9;
-		t_aavdh = 7;
-		t_rdyo  = 15;
-		onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
-		break;
-	}
-
-	div = gpmc_calc_divider(min_gpmc_clk_period);
-	gpmc_clk_ns = gpmc_ticks_to_ns(div);
-	if (gpmc_clk_ns < 15) /* >66MHz */
-		onenand_flags |= ONENAND_FLAG_HF;
-	else
-		onenand_flags &= ~ONENAND_FLAG_HF;
-	if (gpmc_clk_ns < 12) /* >83MHz */
-		onenand_flags |= ONENAND_FLAG_VHF;
-	else
-		onenand_flags &= ~ONENAND_FLAG_VHF;
-	if (onenand_flags & ONENAND_FLAG_VHF)
-		latency = 8;
-	else if (onenand_flags & ONENAND_FLAG_HF)
-		latency = 6;
-	else if (gpmc_clk_ns >= 25) /* 40 MHz*/
-		latency = 3;
-	else
-		latency = 4;
-
-	/* Set synchronous read timings */
-	memset(&dev_t, 0, sizeof(dev_t));
-
-	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
-		onenand_sync.sync_read = true;
-	if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
-		onenand_sync.sync_write = true;
-		onenand_sync.burst_write = true;
-	} else {
-		dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
-		dev_t.t_wpl = t_wpl * 1000;
-		dev_t.t_wph = t_wph * 1000;
-		dev_t.t_aavdh = t_aavdh * 1000;
-	}
-	dev_t.ce_xdelay = true;
-	dev_t.avd_xdelay = true;
-	dev_t.oe_xdelay = true;
-	dev_t.we_xdelay = true;
-	dev_t.clk = min_gpmc_clk_period;
-	dev_t.t_bacc = dev_t.clk;
-	dev_t.t_ces = t_ces * 1000;
-	dev_t.t_avds = t_avds * 1000;
-	dev_t.t_avdh = t_avdh * 1000;
-	dev_t.t_ach = t_ach * 1000;
-	dev_t.cyc_iaa = (latency + 1);
-	dev_t.t_cez_r = t_cez * 1000;
-	dev_t.t_cez_w = dev_t.t_cez_r;
-	dev_t.cyc_aavdh_oe = 1;
-	dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
-
-	gpmc_calc_timings(t, &onenand_sync, &dev_t);
-}
-
-static int omap2_onenand_setup_async(void __iomem *onenand_base)
-{
-	struct gpmc_timings t;
-	int ret;
-
-	/*
-	 * Note that we need to keep sync_write set for the call to
-	 * omap2_onenand_set_async_mode() to work to detect the onenand
-	 * supported clock rate for the sync timings.
-	 */
-	if (gpmc_onenand_data->of_node) {
-		gpmc_read_settings_dt(gpmc_onenand_data->of_node,
-				      &onenand_async);
-		if (onenand_async.sync_read || onenand_async.sync_write) {
-			if (onenand_async.sync_write)
-				gpmc_onenand_data->flags |=
-					ONENAND_SYNC_READWRITE;
-			else
-				gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
-			onenand_async.sync_read = false;
-		}
-	}
-
-	onenand_async.sync_write = true;
-	omap2_onenand_calc_async_timings(&t);
-
-	ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
-	if (ret < 0)
-		return ret;
-
-	ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_async);
-	if (ret < 0)
-		return ret;
-
-	omap2_onenand_set_async_mode(onenand_base);
-
-	return 0;
-}
-
-static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
-{
-	int ret, freq = *freq_ptr;
-	struct gpmc_timings t;
-
-	if (!freq) {
-		/* Very first call freq is not known */
-		freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
-		if (!freq)
-			return -ENODEV;
-		set_onenand_cfg(onenand_base);
-	}
-
-	if (gpmc_onenand_data->of_node) {
-		gpmc_read_settings_dt(gpmc_onenand_data->of_node,
-				      &onenand_sync);
-	} else {
-		/*
-		 * FIXME: Appears to be legacy code from initial ONENAND commit.
-		 * Unclear what boards this is for and if this can be removed.
-		 */
-		if (!cpu_is_omap34xx())
-			onenand_sync.wait_on_read = true;
-	}
-
-	omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
-
-	ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
-	if (ret < 0)
-		return ret;
-
-	ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_sync);
-	if (ret < 0)
-		return ret;
-
-	set_onenand_cfg(onenand_base);
-
-	*freq_ptr = freq;
-
-	return 0;
-}
-
-static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
-{
-	struct device *dev = &gpmc_onenand_device.dev;
-	unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
-	int ret;
-
-	ret = omap2_onenand_setup_async(onenand_base);
-	if (ret) {
-		dev_err(dev, "unable to set to async mode\n");
-		return ret;
-	}
-
-	if (!(gpmc_onenand_data->flags & l))
-		return 0;
-
-	ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
-	if (ret)
-		dev_err(dev, "unable to set to sync mode\n");
-	return ret;
-}
-
-int gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
-{
-	int err;
-	struct device *dev = &gpmc_onenand_device.dev;
-
-	gpmc_onenand_data = _onenand_data;
-	gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
-	gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
-
-	if (cpu_is_omap24xx() &&
-			(gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
-		dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
-		gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
-		gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
-	}
-
-	if (cpu_is_omap34xx())
-		gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
-	else
-		gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
-
-	err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
-				(unsigned long *)&gpmc_onenand_resource.start);
-	if (err < 0) {
-		dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
-			gpmc_onenand_data->cs, err);
-		return err;
-	}
-
-	gpmc_onenand_resource.end = gpmc_onenand_resource.start +
-							ONENAND_IO_SIZE - 1;
-
-	err = platform_device_register(&gpmc_onenand_device);
-	if (err) {
-		dev_err(dev, "Unable to register OneNAND device\n");
-		gpmc_cs_free(gpmc_onenand_data->cs);
-	}
-
-	return err;
-}
diff --git a/include/linux/platform_data/mtd-onenand-omap2.h b/include/linux/platform_data/mtd-onenand-omap2.h
deleted file mode 100644
index 56ff0e6f5ad1..000000000000
--- a/include/linux/platform_data/mtd-onenand-omap2.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (C) 2006 Nokia Corporation
- * Author: Juha Yrjola
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef	__MTD_ONENAND_OMAP2_H
-#define	__MTD_ONENAND_OMAP2_H
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
-#define ONENAND_SYNC_READ	(1 << 0)
-#define ONENAND_SYNC_READWRITE	(1 << 1)
-#define	ONENAND_IN_OMAP34XX	(1 << 2)
-
-struct omap_onenand_platform_data {
-	int			cs;
-	int			gpio_irq;
-	struct mtd_partition	*parts;
-	int			nr_parts;
-	int			(*onenand_setup)(void __iomem *, int *freq_ptr);
-	int			dma_channel;
-	u8			flags;
-	u8			regulator_can_sleep;
-	u8			skip_initial_unlocking;
-
-	/* for passing the partitions */
-	struct device_node	*of_node;
-};
-#endif
-- 
2.11.0

[PATCH v5 16/16] ARM: dts: Nokia: Use OneNAND INT pin

[Ladislav Michl]

Enable use of INT pin to wait for command completion. This is just
experimental placeholder patch as it lacks pinmux settings.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
---

Changes in v5:
- pin name is INT

Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/omap2420-n8x0-common.dtsi | 4 +---
 arch/arm/boot/dts/omap3-n900.dts            | 2 +-
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
index 843f6a2f5e29..7b1983214417 100644
--- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
+++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
@@ -42,14 +42,12 @@
 
 &gpmc {
 	ranges = <0 0 0x04000000 0x1000000>;	/* CS0: 16MB for OneNAND */
-
-	/* gpio-irq for dma: 26 */
-
 	onenand@0,0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "ti,omap2-onenand";
 		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
+		int-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; /* gpio_26 for INT */
 
 		gpmc,sync-read;
 		gpmc,burst-length = <16>;
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index aa5b1a439564..4fff3c466e81 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -834,12 +834,12 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&gpmc_pins>;
 
-	/* sys_ndmareq1 could be used by the driver, not as gpio65 though */
 	onenand@0,0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "ti,omap2-onenand";
 		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
+		int-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; /* gpio_65 for INT */
 
 		gpmc,sync-read;
 		gpmc,sync-write;
-- 
2.11.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v5 16/16] ARM: dts: Nokia: Use OneNAND INT pin

[Ladislav Michl]

Enable use of INT pin to wait for command completion. This is just
experimental placeholder patch as it lacks pinmux settings.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
---

Changes in v5:
- pin name is INT

Changes in v4:
- new patch

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/omap2420-n8x0-common.dtsi | 4 +---
 arch/arm/boot/dts/omap3-n900.dts            | 2 +-
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
index 843f6a2f5e29..7b1983214417 100644
--- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
+++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
@@ -42,14 +42,12 @@
 
 &gpmc {
 	ranges = <0 0 0x04000000 0x1000000>;	/* CS0: 16MB for OneNAND */
-
-	/* gpio-irq for dma: 26 */
-
 	onenand@0,0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "ti,omap2-onenand";
 		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
+		int-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; /* gpio_26 for INT */
 
 		gpmc,sync-read;
 		gpmc,burst-length = <16>;
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index aa5b1a439564..4fff3c466e81 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -834,12 +834,12 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&gpmc_pins>;
 
-	/* sys_ndmareq1 could be used by the driver, not as gpio65 though */
 	onenand@0,0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "ti,omap2-onenand";
 		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
+		int-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; /* gpio_65 for INT */
 
 		gpmc,sync-read;
 		gpmc,sync-write;
-- 
2.11.0

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Boris Brezillon]

Hello Ladislav,

On Wed, 15 Nov 2017 17:23:06 +0100
Ladislav Michl <ladis@linux-mips.org> wrote:

> this patch serie updates OMAP2+ OneNAND driver to the present times, making
> it fully DT configurable, using libgpio and dmaengine apis - those are
> optional, driver will work without them.
> 
> Please note that unlike previous driver version, which basically ignored
> DT specified timings, this one relies on it, so it is important to get
> it right in your DT (dumping it from previous kernel version).
> 
> In case synchronous timings is requested, it is okay to specify timings
> for the slowest chip ever used for you board as it is evetually optimized
> after chip probe.
> 
> Original driver used DMA only if user specified INT gpio in platform
> data, now DMA is used unconditionally and PIO mode is used as fallback.
> 
> In case anyone wants to give it a try, few DT related changes are needed:
> - onenand node needs 'ti,omap2-onenand' compatible (for mailine boards this is
>   done in patch 2)
> - to use INT pin, int-gpios needs to be specified (for n900 and n8x0 this is
>   done in patch 16, however patch lacks pinmux configuration.
> 
> Most notable changes from v3:
> - added dmaengine patches by Peter Ujfalusi
> - added dt bindings documentation
> - added cleanup patches
> - DMA enabled by default
> 
> Most notable changes from v4:
> - collected tags
> - used INT pin name properly
> - hopefully all comments taken into account
> 
> Also note that driver will fail probe OneNAND chip after patch 13 and start
> working again after patch 14.

Well, breaking bisectability is never a good thing, this being said, I
won't complain if TI maintainers are okay with that.

> 
> Testing and benchmarking very welcome.

Let me know when you think this series is ready to be merged.

> 
> Depends on "memory: omap-gpmc: Make 'bank-width' property optional"
> https://patchwork.kernel.org/patch/10043259/

Hm, I see this patch has been applied to the omap tree, so maybe it's
simpler if everything goes through this tree. I don't plan to modify
onenand related stuff in this release anyway.

> 
> Ladislav Michl (14):
>   dt-bindings: mtd: gpmc-onenand: Update properties description
>   ARM: dts: OMAP2+: Add compatible property to onenand node
>   ARM: dts: omap3-igep: Update onenand node timings
>   mtd: onenand: omap2: Remove regulator support
>   mtd: onenand: omap2: Remove skip initial unlocking support
>   mtd: onenand: omap2: Remove partitioning support from platform data
>   mtd: onenand: omap2: Account waiting time as waiting on IO
>   mtd: onenand: omap2: Unify OMAP2 and OMAP3 DMA implementation
>   mtd: onenand: omap2: Do not make delay for GPIO OMAP3 specific
>   mtd: onenand: omap2: Decouple DMA enabling from INT pin availability
>   memory: omap-gpmc: Refactor OneNAND support
>   mtd: onenand: omap2: Configure driver from DT
>   ARM: OMAP2+: Remove gpmc-onenand
>   ARM: dts: Nokia: Use OneNAND INT pin
> 
> Peter Ujfalusi (2):
>   mtd: onenand: omap2: Simplify the DMA setup for various paths
>   mtd: onenand: omap2: Convert to use dmaengine for memcpy
> 
>  .../devicetree/bindings/mtd/gpmc-onenand.txt       |   6 +-
>  arch/arm/boot/dts/omap2420-n8x0-common.dtsi        |   5 +-
>  arch/arm/boot/dts/omap3-igep.dtsi                  |  30 +-
>  arch/arm/boot/dts/omap3-n900.dts                   |   3 +-
>  arch/arm/boot/dts/omap3-n950-n9.dtsi               |   1 +
>  arch/arm/boot/dts/omap3430-sdp.dts                 |   1 +
>  arch/arm/mach-omap2/Makefile                       |   3 -
>  arch/arm/mach-omap2/gpmc-onenand.c                 | 409 ---------------
>  drivers/memory/omap-gpmc.c                         | 158 ++++--
>  drivers/mtd/onenand/Kconfig                        |   3 +-
>  drivers/mtd/onenand/omap2.c                        | 576 ++++++++-------------
>  include/linux/omap-gpmc.h                          |  28 +
>  include/linux/platform_data/mtd-onenand-omap2.h    |  34 --
>  13 files changed, 387 insertions(+), 870 deletions(-)
>  delete mode 100644 arch/arm/mach-omap2/gpmc-onenand.c
>  delete mode 100644 include/linux/platform_data/mtd-onenand-omap2.h
> 


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Boris Brezillon]

Hello Ladislav,

On Wed, 15 Nov 2017 17:23:06 +0100
Ladislav Michl <ladis@linux-mips.org> wrote:

> this patch serie updates OMAP2+ OneNAND driver to the present times, making
> it fully DT configurable, using libgpio and dmaengine apis - those are
> optional, driver will work without them.
> 
> Please note that unlike previous driver version, which basically ignored
> DT specified timings, this one relies on it, so it is important to get
> it right in your DT (dumping it from previous kernel version).
> 
> In case synchronous timings is requested, it is okay to specify timings
> for the slowest chip ever used for you board as it is evetually optimized
> after chip probe.
> 
> Original driver used DMA only if user specified INT gpio in platform
> data, now DMA is used unconditionally and PIO mode is used as fallback.
> 
> In case anyone wants to give it a try, few DT related changes are needed:
> - onenand node needs 'ti,omap2-onenand' compatible (for mailine boards this is
>   done in patch 2)
> - to use INT pin, int-gpios needs to be specified (for n900 and n8x0 this is
>   done in patch 16, however patch lacks pinmux configuration.
> 
> Most notable changes from v3:
> - added dmaengine patches by Peter Ujfalusi
> - added dt bindings documentation
> - added cleanup patches
> - DMA enabled by default
> 
> Most notable changes from v4:
> - collected tags
> - used INT pin name properly
> - hopefully all comments taken into account
> 
> Also note that driver will fail probe OneNAND chip after patch 13 and start
> working again after patch 14.

Well, breaking bisectability is never a good thing, this being said, I
won't complain if TI maintainers are okay with that.

> 
> Testing and benchmarking very welcome.

Let me know when you think this series is ready to be merged.

> 
> Depends on "memory: omap-gpmc: Make 'bank-width' property optional"
> https://patchwork.kernel.org/patch/10043259/

Hm, I see this patch has been applied to the omap tree, so maybe it's
simpler if everything goes through this tree. I don't plan to modify
onenand related stuff in this release anyway.

> 
> Ladislav Michl (14):
>   dt-bindings: mtd: gpmc-onenand: Update properties description
>   ARM: dts: OMAP2+: Add compatible property to onenand node
>   ARM: dts: omap3-igep: Update onenand node timings
>   mtd: onenand: omap2: Remove regulator support
>   mtd: onenand: omap2: Remove skip initial unlocking support
>   mtd: onenand: omap2: Remove partitioning support from platform data
>   mtd: onenand: omap2: Account waiting time as waiting on IO
>   mtd: onenand: omap2: Unify OMAP2 and OMAP3 DMA implementation
>   mtd: onenand: omap2: Do not make delay for GPIO OMAP3 specific
>   mtd: onenand: omap2: Decouple DMA enabling from INT pin availability
>   memory: omap-gpmc: Refactor OneNAND support
>   mtd: onenand: omap2: Configure driver from DT
>   ARM: OMAP2+: Remove gpmc-onenand
>   ARM: dts: Nokia: Use OneNAND INT pin
> 
> Peter Ujfalusi (2):
>   mtd: onenand: omap2: Simplify the DMA setup for various paths
>   mtd: onenand: omap2: Convert to use dmaengine for memcpy
> 
>  .../devicetree/bindings/mtd/gpmc-onenand.txt       |   6 +-
>  arch/arm/boot/dts/omap2420-n8x0-common.dtsi        |   5 +-
>  arch/arm/boot/dts/omap3-igep.dtsi                  |  30 +-
>  arch/arm/boot/dts/omap3-n900.dts                   |   3 +-
>  arch/arm/boot/dts/omap3-n950-n9.dtsi               |   1 +
>  arch/arm/boot/dts/omap3430-sdp.dts                 |   1 +
>  arch/arm/mach-omap2/Makefile                       |   3 -
>  arch/arm/mach-omap2/gpmc-onenand.c                 | 409 ---------------
>  drivers/memory/omap-gpmc.c                         | 158 ++++--
>  drivers/mtd/onenand/Kconfig                        |   3 +-
>  drivers/mtd/onenand/omap2.c                        | 576 ++++++++-------------
>  include/linux/omap-gpmc.h                          |  28 +
>  include/linux/platform_data/mtd-onenand-omap2.h    |  34 --
>  13 files changed, 387 insertions(+), 870 deletions(-)
>  delete mode 100644 arch/arm/mach-omap2/gpmc-onenand.c
>  delete mode 100644 include/linux/platform_data/mtd-onenand-omap2.h
> 

Re: [PATCH v5 01/16] dt-bindings: mtd: gpmc-onenand: Update properties description

[Boris Brezillon]

+Rob and the DT ML

On Wed, 15 Nov 2017 17:24:58 +0100
Ladislav Michl <ladis-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org> wrote:

> Compatible property is required for OMAP2+ mtd driver. Also
> add INT pin gpio description and delete unused dma-channel
> property.
> 
> Signed-off-by: Ladislav Michl <ladis-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>
> Reviewed-by: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
> Acked-by: Roger Quadros <rogerq-l0cyMroinI0@public.gmane.org>
> ---
> 
> Changes in v5:
> - renamed R/B pin to INT pin
> 
> Changes in v4:
> - new patch
> 
> Changes in v3: None
> Changes in v2: None
> 
>  Documentation/devicetree/bindings/mtd/gpmc-onenand.txt | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> index b6e8bfd024f4..e9f01a963a0a 100644
> --- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> +++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> @@ -9,13 +9,14 @@ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
>  
>  Required properties:
>  
> + - compatible:		"ti,omap2-onenand"

Don't you break backward compat by adding this new requirement?

>   - reg:			The CS line the peripheral is connected to
> - - gpmc,device-width	Width of the ONENAND device connected to the GPMC
> + - gpmc,device-width:	Width of the ONENAND device connected to the GPMC
>  			in bytes. Must be 1 or 2.
>  
>  Optional properties:
>  
> - - dma-channel:		DMA Channel index
> + - int-gpios:		GPIO specifier for the INT pin.
>  
>  For inline partition table parsing (optional):
>  
> @@ -35,6 +36,7 @@ Example for an OMAP3430 board:
>  		#size-cells = <1>;
>  
>  		onenand@0 {
> +			compatible = "ti,omap2-onenand";
>  			reg = <0 0 0>; /* CS0, offset 0 */
>  			gpmc,device-width = <2>;
>  

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Re: [PATCH v5 01/16] dt-bindings: mtd: gpmc-onenand: Update properties description

[Boris Brezillon]

+Rob and the DT ML

On Wed, 15 Nov 2017 17:24:58 +0100
Ladislav Michl <ladis@linux-mips.org> wrote:

> Compatible property is required for OMAP2+ mtd driver. Also
> add INT pin gpio description and delete unused dma-channel
> property.
> 
> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> Acked-by: Roger Quadros <rogerq@ti.com>
> ---
> 
> Changes in v5:
> - renamed R/B pin to INT pin
> 
> Changes in v4:
> - new patch
> 
> Changes in v3: None
> Changes in v2: None
> 
>  Documentation/devicetree/bindings/mtd/gpmc-onenand.txt | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> index b6e8bfd024f4..e9f01a963a0a 100644
> --- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> +++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> @@ -9,13 +9,14 @@ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
>  
>  Required properties:
>  
> + - compatible:		"ti,omap2-onenand"

Don't you break backward compat by adding this new requirement?

>   - reg:			The CS line the peripheral is connected to
> - - gpmc,device-width	Width of the ONENAND device connected to the GPMC
> + - gpmc,device-width:	Width of the ONENAND device connected to the GPMC
>  			in bytes. Must be 1 or 2.
>  
>  Optional properties:
>  
> - - dma-channel:		DMA Channel index
> + - int-gpios:		GPIO specifier for the INT pin.
>  
>  For inline partition table parsing (optional):
>  
> @@ -35,6 +36,7 @@ Example for an OMAP3430 board:
>  		#size-cells = <1>;
>  
>  		onenand@0 {
> +			compatible = "ti,omap2-onenand";
>  			reg = <0 0 0>; /* CS0, offset 0 */
>  			gpmc,device-width = <2>;
>  

Re: [PATCH v5 01/16] dt-bindings: mtd: gpmc-onenand: Update properties description

[Ladislav Michl]

On Thu, Nov 30, 2017 at 11:25:44AM +0100, Boris Brezillon wrote:
> +Rob and the DT ML
> 
> On Wed, 15 Nov 2017 17:24:58 +0100
> Ladislav Michl <ladis@linux-mips.org> wrote:
> 
> > Compatible property is required for OMAP2+ mtd driver. Also
> > add INT pin gpio description and delete unused dma-channel
> > property.
> > 
> > Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
> > Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> > Acked-by: Roger Quadros <rogerq@ti.com>
> > ---
> > 
> > Changes in v5:
> > - renamed R/B pin to INT pin
> > 
> > Changes in v4:
> > - new patch
> > 
> > Changes in v3: None
> > Changes in v2: None
> > 
> >  Documentation/devicetree/bindings/mtd/gpmc-onenand.txt | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> > index b6e8bfd024f4..e9f01a963a0a 100644
> > --- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> > +++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> > @@ -9,13 +9,14 @@ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
> >  
> >  Required properties:
> >  
> > + - compatible:		"ti,omap2-onenand"
> 
> Don't you break backward compat by adding this new requirement?

I was told it is okay in this case as OneNAND conversion to DT is unfinished.
There was compat fixup code in earlier versions of patchset and it was dropped
later. If others see it opposite way I can add it back.

> >   - reg:			The CS line the peripheral is connected to
> > - - gpmc,device-width	Width of the ONENAND device connected to the GPMC
> > + - gpmc,device-width:	Width of the ONENAND device connected to the GPMC
> >  			in bytes. Must be 1 or 2.
> >  
> >  Optional properties:
> >  
> > - - dma-channel:		DMA Channel index
> > + - int-gpios:		GPIO specifier for the INT pin.
> >  
> >  For inline partition table parsing (optional):
> >  
> > @@ -35,6 +36,7 @@ Example for an OMAP3430 board:
> >  		#size-cells = <1>;
> >  
> >  		onenand@0 {
> > +			compatible = "ti,omap2-onenand";
> >  			reg = <0 0 0>; /* CS0, offset 0 */
> >  			gpmc,device-width = <2>;
> >  

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Re: [PATCH v5 01/16] dt-bindings: mtd: gpmc-onenand: Update properties description

[Ladislav Michl]

On Thu, Nov 30, 2017 at 11:25:44AM +0100, Boris Brezillon wrote:
> +Rob and the DT ML
> 
> On Wed, 15 Nov 2017 17:24:58 +0100
> Ladislav Michl <ladis@linux-mips.org> wrote:
> 
> > Compatible property is required for OMAP2+ mtd driver. Also
> > add INT pin gpio description and delete unused dma-channel
> > property.
> > 
> > Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
> > Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> > Acked-by: Roger Quadros <rogerq@ti.com>
> > ---
> > 
> > Changes in v5:
> > - renamed R/B pin to INT pin
> > 
> > Changes in v4:
> > - new patch
> > 
> > Changes in v3: None
> > Changes in v2: None
> > 
> >  Documentation/devicetree/bindings/mtd/gpmc-onenand.txt | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> > index b6e8bfd024f4..e9f01a963a0a 100644
> > --- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> > +++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> > @@ -9,13 +9,14 @@ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
> >  
> >  Required properties:
> >  
> > + - compatible:		"ti,omap2-onenand"
> 
> Don't you break backward compat by adding this new requirement?

I was told it is okay in this case as OneNAND conversion to DT is unfinished.
There was compat fixup code in earlier versions of patchset and it was dropped
later. If others see it opposite way I can add it back.

> >   - reg:			The CS line the peripheral is connected to
> > - - gpmc,device-width	Width of the ONENAND device connected to the GPMC
> > + - gpmc,device-width:	Width of the ONENAND device connected to the GPMC
> >  			in bytes. Must be 1 or 2.
> >  
> >  Optional properties:
> >  
> > - - dma-channel:		DMA Channel index
> > + - int-gpios:		GPIO specifier for the INT pin.
> >  
> >  For inline partition table parsing (optional):
> >  
> > @@ -35,6 +36,7 @@ Example for an OMAP3430 board:
> >  		#size-cells = <1>;
> >  
> >  		onenand@0 {
> > +			compatible = "ti,omap2-onenand";
> >  			reg = <0 0 0>; /* CS0, offset 0 */
> >  			gpmc,device-width = <2>;
> >  

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Ladislav Michl]

Hi Boris,

On Thu, Nov 30, 2017 at 11:18:40AM +0100, Boris Brezillon wrote:
> Hello Ladislav,
> 
> On Wed, 15 Nov 2017 17:23:06 +0100
> Ladislav Michl <ladis@linux-mips.org> wrote:
> 
> > this patch serie updates OMAP2+ OneNAND driver to the present times, making
> > it fully DT configurable, using libgpio and dmaengine apis - those are
> > optional, driver will work without them.
> > 
> > Please note that unlike previous driver version, which basically ignored
> > DT specified timings, this one relies on it, so it is important to get
> > it right in your DT (dumping it from previous kernel version).
> > 
> > In case synchronous timings is requested, it is okay to specify timings
> > for the slowest chip ever used for you board as it is evetually optimized
> > after chip probe.
> > 
> > Original driver used DMA only if user specified INT gpio in platform
> > data, now DMA is used unconditionally and PIO mode is used as fallback.
> > 
> > In case anyone wants to give it a try, few DT related changes are needed:
> > - onenand node needs 'ti,omap2-onenand' compatible (for mailine boards this is
> >   done in patch 2)
> > - to use INT pin, int-gpios needs to be specified (for n900 and n8x0 this is
> >   done in patch 16, however patch lacks pinmux configuration.
> > 
> > Most notable changes from v3:
> > - added dmaengine patches by Peter Ujfalusi
> > - added dt bindings documentation
> > - added cleanup patches
> > - DMA enabled by default
> > 
> > Most notable changes from v4:
> > - collected tags
> > - used INT pin name properly
> > - hopefully all comments taken into account
> > 
> > Also note that driver will fail probe OneNAND chip after patch 13 and start
> > working again after patch 14.
> 
> Well, breaking bisectability is never a good thing, this being said, I
> won't complain if TI maintainers are okay with that.

I agree.

> > Testing and benchmarking very welcome.
> 
> Let me know when you think this series is ready to be merged.

I'm still waiting for some OMAP2 users to show up. So far it is tested
on OMAP3 only (And I'm using this patchset in production).

> > Depends on "memory: omap-gpmc: Make 'bank-width' property optional"
> > https://patchwork.kernel.org/patch/10043259/
> 
> Hm, I see this patch has been applied to the omap tree, so maybe it's
> simpler if everything goes through this tree. I don't plan to modify
> onenand related stuff in this release anyway.

It is intended for 4.16, so if Tony is fine with your proposal, I can
modify patches not to break bisecting...

> > Ladislav Michl (14):
> >   dt-bindings: mtd: gpmc-onenand: Update properties description
> >   ARM: dts: OMAP2+: Add compatible property to onenand node
> >   ARM: dts: omap3-igep: Update onenand node timings
> >   mtd: onenand: omap2: Remove regulator support
> >   mtd: onenand: omap2: Remove skip initial unlocking support
> >   mtd: onenand: omap2: Remove partitioning support from platform data
> >   mtd: onenand: omap2: Account waiting time as waiting on IO
> >   mtd: onenand: omap2: Unify OMAP2 and OMAP3 DMA implementation
> >   mtd: onenand: omap2: Do not make delay for GPIO OMAP3 specific
> >   mtd: onenand: omap2: Decouple DMA enabling from INT pin availability
> >   memory: omap-gpmc: Refactor OneNAND support
> >   mtd: onenand: omap2: Configure driver from DT
> >   ARM: OMAP2+: Remove gpmc-onenand
> >   ARM: dts: Nokia: Use OneNAND INT pin
> > 
> > Peter Ujfalusi (2):
> >   mtd: onenand: omap2: Simplify the DMA setup for various paths
> >   mtd: onenand: omap2: Convert to use dmaengine for memcpy
> > 
> >  .../devicetree/bindings/mtd/gpmc-onenand.txt       |   6 +-
> >  arch/arm/boot/dts/omap2420-n8x0-common.dtsi        |   5 +-
> >  arch/arm/boot/dts/omap3-igep.dtsi                  |  30 +-
> >  arch/arm/boot/dts/omap3-n900.dts                   |   3 +-
> >  arch/arm/boot/dts/omap3-n950-n9.dtsi               |   1 +
> >  arch/arm/boot/dts/omap3430-sdp.dts                 |   1 +
> >  arch/arm/mach-omap2/Makefile                       |   3 -
> >  arch/arm/mach-omap2/gpmc-onenand.c                 | 409 ---------------
> >  drivers/memory/omap-gpmc.c                         | 158 ++++--
> >  drivers/mtd/onenand/Kconfig                        |   3 +-
> >  drivers/mtd/onenand/omap2.c                        | 576 ++++++++-------------
> >  include/linux/omap-gpmc.h                          |  28 +
> >  include/linux/platform_data/mtd-onenand-omap2.h    |  34 --
> >  13 files changed, 387 insertions(+), 870 deletions(-)
> >  delete mode 100644 arch/arm/mach-omap2/gpmc-onenand.c
> >  delete mode 100644 include/linux/platform_data/mtd-onenand-omap2.h
> > 

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Ladislav Michl]

Hi Boris,

On Thu, Nov 30, 2017 at 11:18:40AM +0100, Boris Brezillon wrote:
> Hello Ladislav,
> 
> On Wed, 15 Nov 2017 17:23:06 +0100
> Ladislav Michl <ladis@linux-mips.org> wrote:
> 
> > this patch serie updates OMAP2+ OneNAND driver to the present times, making
> > it fully DT configurable, using libgpio and dmaengine apis - those are
> > optional, driver will work without them.
> > 
> > Please note that unlike previous driver version, which basically ignored
> > DT specified timings, this one relies on it, so it is important to get
> > it right in your DT (dumping it from previous kernel version).
> > 
> > In case synchronous timings is requested, it is okay to specify timings
> > for the slowest chip ever used for you board as it is evetually optimized
> > after chip probe.
> > 
> > Original driver used DMA only if user specified INT gpio in platform
> > data, now DMA is used unconditionally and PIO mode is used as fallback.
> > 
> > In case anyone wants to give it a try, few DT related changes are needed:
> > - onenand node needs 'ti,omap2-onenand' compatible (for mailine boards this is
> >   done in patch 2)
> > - to use INT pin, int-gpios needs to be specified (for n900 and n8x0 this is
> >   done in patch 16, however patch lacks pinmux configuration.
> > 
> > Most notable changes from v3:
> > - added dmaengine patches by Peter Ujfalusi
> > - added dt bindings documentation
> > - added cleanup patches
> > - DMA enabled by default
> > 
> > Most notable changes from v4:
> > - collected tags
> > - used INT pin name properly
> > - hopefully all comments taken into account
> > 
> > Also note that driver will fail probe OneNAND chip after patch 13 and start
> > working again after patch 14.
> 
> Well, breaking bisectability is never a good thing, this being said, I
> won't complain if TI maintainers are okay with that.

I agree.

> > Testing and benchmarking very welcome.
> 
> Let me know when you think this series is ready to be merged.

I'm still waiting for some OMAP2 users to show up. So far it is tested
on OMAP3 only (And I'm using this patchset in production).

> > Depends on "memory: omap-gpmc: Make 'bank-width' property optional"
> > https://patchwork.kernel.org/patch/10043259/
> 
> Hm, I see this patch has been applied to the omap tree, so maybe it's
> simpler if everything goes through this tree. I don't plan to modify
> onenand related stuff in this release anyway.

It is intended for 4.16, so if Tony is fine with your proposal, I can
modify patches not to break bisecting...

> > Ladislav Michl (14):
> >   dt-bindings: mtd: gpmc-onenand: Update properties description
> >   ARM: dts: OMAP2+: Add compatible property to onenand node
> >   ARM: dts: omap3-igep: Update onenand node timings
> >   mtd: onenand: omap2: Remove regulator support
> >   mtd: onenand: omap2: Remove skip initial unlocking support
> >   mtd: onenand: omap2: Remove partitioning support from platform data
> >   mtd: onenand: omap2: Account waiting time as waiting on IO
> >   mtd: onenand: omap2: Unify OMAP2 and OMAP3 DMA implementation
> >   mtd: onenand: omap2: Do not make delay for GPIO OMAP3 specific
> >   mtd: onenand: omap2: Decouple DMA enabling from INT pin availability
> >   memory: omap-gpmc: Refactor OneNAND support
> >   mtd: onenand: omap2: Configure driver from DT
> >   ARM: OMAP2+: Remove gpmc-onenand
> >   ARM: dts: Nokia: Use OneNAND INT pin
> > 
> > Peter Ujfalusi (2):
> >   mtd: onenand: omap2: Simplify the DMA setup for various paths
> >   mtd: onenand: omap2: Convert to use dmaengine for memcpy
> > 
> >  .../devicetree/bindings/mtd/gpmc-onenand.txt       |   6 +-
> >  arch/arm/boot/dts/omap2420-n8x0-common.dtsi        |   5 +-
> >  arch/arm/boot/dts/omap3-igep.dtsi                  |  30 +-
> >  arch/arm/boot/dts/omap3-n900.dts                   |   3 +-
> >  arch/arm/boot/dts/omap3-n950-n9.dtsi               |   1 +
> >  arch/arm/boot/dts/omap3430-sdp.dts                 |   1 +
> >  arch/arm/mach-omap2/Makefile                       |   3 -
> >  arch/arm/mach-omap2/gpmc-onenand.c                 | 409 ---------------
> >  drivers/memory/omap-gpmc.c                         | 158 ++++--
> >  drivers/mtd/onenand/Kconfig                        |   3 +-
> >  drivers/mtd/onenand/omap2.c                        | 576 ++++++++-------------
> >  include/linux/omap-gpmc.h                          |  28 +
> >  include/linux/platform_data/mtd-onenand-omap2.h    |  34 --
> >  13 files changed, 387 insertions(+), 870 deletions(-)
> >  delete mode 100644 arch/arm/mach-omap2/gpmc-onenand.c
> >  delete mode 100644 include/linux/platform_data/mtd-onenand-omap2.h
> > 

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Tony Lindgren]

* Boris Brezillon <boris.brezillon@free-electrons.com> [171130 10:21]:
> On Wed, 15 Nov 2017 17:23:06 +0100
> Ladislav Michl <ladis@linux-mips.org> wrote:
> 
> > this patch serie updates OMAP2+ OneNAND driver to the present times, making
> > it fully DT configurable, using libgpio and dmaengine apis - those are
> > optional, driver will work without them.
> > 
> > Please note that unlike previous driver version, which basically ignored
> > DT specified timings, this one relies on it, so it is important to get
> > it right in your DT (dumping it from previous kernel version).
> > 
> > In case synchronous timings is requested, it is okay to specify timings
> > for the slowest chip ever used for you board as it is evetually optimized
> > after chip probe.
> > 
> > Original driver used DMA only if user specified INT gpio in platform
> > data, now DMA is used unconditionally and PIO mode is used as fallback.
> > 
> > In case anyone wants to give it a try, few DT related changes are needed:
> > - onenand node needs 'ti,omap2-onenand' compatible (for mailine boards this is
> >   done in patch 2)
> > - to use INT pin, int-gpios needs to be specified (for n900 and n8x0 this is
> >   done in patch 16, however patch lacks pinmux configuration.
> > 
> > Most notable changes from v3:
> > - added dmaengine patches by Peter Ujfalusi
> > - added dt bindings documentation
> > - added cleanup patches
> > - DMA enabled by default
> > 
> > Most notable changes from v4:
> > - collected tags
> > - used INT pin name properly
> > - hopefully all comments taken into account
> > 
> > Also note that driver will fail probe OneNAND chip after patch 13 and start
> > working again after patch 14.
> 
> Well, breaking bisectability is never a good thing, this being said, I
> won't complain if TI maintainers are okay with that.

There should not be any reason to break git bisect for booting at all,
what exactly is the issue here?

> > Testing and benchmarking very welcome.
> 
> Let me know when you think this series is ready to be merged.

Well we need Aaro to test this on n8x0 as my n800 is currently not
booting at all.

> > Depends on "memory: omap-gpmc: Make 'bank-width' property optional"
> > https://patchwork.kernel.org/patch/10043259/
> 
> Hm, I see this patch has been applied to the omap tree, so maybe it's
> simpler if everything goes through this tree. I don't plan to modify
> onenand related stuff in this release anyway.

Maybe Roger can provide you with an immutable commit with just that
patch?

Regards,

Tony

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Tony Lindgren]

* Boris Brezillon <boris.brezillon@free-electrons.com> [171130 10:21]:
> On Wed, 15 Nov 2017 17:23:06 +0100
> Ladislav Michl <ladis@linux-mips.org> wrote:
> 
> > this patch serie updates OMAP2+ OneNAND driver to the present times, making
> > it fully DT configurable, using libgpio and dmaengine apis - those are
> > optional, driver will work without them.
> > 
> > Please note that unlike previous driver version, which basically ignored
> > DT specified timings, this one relies on it, so it is important to get
> > it right in your DT (dumping it from previous kernel version).
> > 
> > In case synchronous timings is requested, it is okay to specify timings
> > for the slowest chip ever used for you board as it is evetually optimized
> > after chip probe.
> > 
> > Original driver used DMA only if user specified INT gpio in platform
> > data, now DMA is used unconditionally and PIO mode is used as fallback.
> > 
> > In case anyone wants to give it a try, few DT related changes are needed:
> > - onenand node needs 'ti,omap2-onenand' compatible (for mailine boards this is
> >   done in patch 2)
> > - to use INT pin, int-gpios needs to be specified (for n900 and n8x0 this is
> >   done in patch 16, however patch lacks pinmux configuration.
> > 
> > Most notable changes from v3:
> > - added dmaengine patches by Peter Ujfalusi
> > - added dt bindings documentation
> > - added cleanup patches
> > - DMA enabled by default
> > 
> > Most notable changes from v4:
> > - collected tags
> > - used INT pin name properly
> > - hopefully all comments taken into account
> > 
> > Also note that driver will fail probe OneNAND chip after patch 13 and start
> > working again after patch 14.
> 
> Well, breaking bisectability is never a good thing, this being said, I
> won't complain if TI maintainers are okay with that.

There should not be any reason to break git bisect for booting at all,
what exactly is the issue here?

> > Testing and benchmarking very welcome.
> 
> Let me know when you think this series is ready to be merged.

Well we need Aaro to test this on n8x0 as my n800 is currently not
booting at all.

> > Depends on "memory: omap-gpmc: Make 'bank-width' property optional"
> > https://patchwork.kernel.org/patch/10043259/
> 
> Hm, I see this patch has been applied to the omap tree, so maybe it's
> simpler if everything goes through this tree. I don't plan to modify
> onenand related stuff in this release anyway.

Maybe Roger can provide you with an immutable commit with just that
patch?

Regards,

Tony

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Roger Quadros]

On 30/11/17 18:09, Tony Lindgren wrote:
> * Boris Brezillon <boris.brezillon@free-electrons.com> [171130 10:21]:
>> On Wed, 15 Nov 2017 17:23:06 +0100
>> Ladislav Michl <ladis@linux-mips.org> wrote:
>>
>>> this patch serie updates OMAP2+ OneNAND driver to the present times, making
>>> it fully DT configurable, using libgpio and dmaengine apis - those are
>>> optional, driver will work without them.
>>>
>>> Please note that unlike previous driver version, which basically ignored
>>> DT specified timings, this one relies on it, so it is important to get
>>> it right in your DT (dumping it from previous kernel version).
>>>
>>> In case synchronous timings is requested, it is okay to specify timings
>>> for the slowest chip ever used for you board as it is evetually optimized
>>> after chip probe.
>>>
>>> Original driver used DMA only if user specified INT gpio in platform
>>> data, now DMA is used unconditionally and PIO mode is used as fallback.
>>>
>>> In case anyone wants to give it a try, few DT related changes are needed:
>>> - onenand node needs 'ti,omap2-onenand' compatible (for mailine boards this is
>>>   done in patch 2)
>>> - to use INT pin, int-gpios needs to be specified (for n900 and n8x0 this is
>>>   done in patch 16, however patch lacks pinmux configuration.
>>>
>>> Most notable changes from v3:
>>> - added dmaengine patches by Peter Ujfalusi
>>> - added dt bindings documentation
>>> - added cleanup patches
>>> - DMA enabled by default
>>>
>>> Most notable changes from v4:
>>> - collected tags
>>> - used INT pin name properly
>>> - hopefully all comments taken into account
>>>
>>> Also note that driver will fail probe OneNAND chip after patch 13 and start
>>> working again after patch 14.
>>
>> Well, breaking bisectability is never a good thing, this being said, I
>> won't complain if TI maintainers are okay with that.
> 
> There should not be any reason to break git bisect for booting at all,
> what exactly is the issue here?
> 
>>> Testing and benchmarking very welcome.
>>
>> Let me know when you think this series is ready to be merged.
> 
> Well we need Aaro to test this on n8x0 as my n800 is currently not
> booting at all.
> 
>>> Depends on "memory: omap-gpmc: Make 'bank-width' property optional"
>>> https://patchwork.kernel.org/patch/10043259/
>>
>> Hm, I see this patch has been applied to the omap tree, so maybe it's
>> simpler if everything goes through this tree. I don't plan to modify
>> onenand related stuff in this release anyway.
> 
> Maybe Roger can provide you with an immutable commit with just that
> patch?

Here you go

The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:

  Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)

are available in the git repository at:

  https://github.com/rogerq/linux.git for-v4.16/gpmc-omap-immutable

for you to fetch changes up to c18a7ac3398d0cef29749f9568666db8321aa4c9:

  memory: omap-gpmc: Make 'bank-width' property optional (2017-12-01 15:37:49 +0200)

----------------------------------------------------------------
Ladislav Michl (1):
      memory: omap-gpmc: Make 'bank-width' property optional

 drivers/memory/omap-gpmc.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

-- 
cheers,
-roger

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Roger Quadros]

On 30/11/17 18:09, Tony Lindgren wrote:
> * Boris Brezillon <boris.brezillon@free-electrons.com> [171130 10:21]:
>> On Wed, 15 Nov 2017 17:23:06 +0100
>> Ladislav Michl <ladis@linux-mips.org> wrote:
>>
>>> this patch serie updates OMAP2+ OneNAND driver to the present times, making
>>> it fully DT configurable, using libgpio and dmaengine apis - those are
>>> optional, driver will work without them.
>>>
>>> Please note that unlike previous driver version, which basically ignored
>>> DT specified timings, this one relies on it, so it is important to get
>>> it right in your DT (dumping it from previous kernel version).
>>>
>>> In case synchronous timings is requested, it is okay to specify timings
>>> for the slowest chip ever used for you board as it is evetually optimized
>>> after chip probe.
>>>
>>> Original driver used DMA only if user specified INT gpio in platform
>>> data, now DMA is used unconditionally and PIO mode is used as fallback.
>>>
>>> In case anyone wants to give it a try, few DT related changes are needed:
>>> - onenand node needs 'ti,omap2-onenand' compatible (for mailine boards this is
>>>   done in patch 2)
>>> - to use INT pin, int-gpios needs to be specified (for n900 and n8x0 this is
>>>   done in patch 16, however patch lacks pinmux configuration.
>>>
>>> Most notable changes from v3:
>>> - added dmaengine patches by Peter Ujfalusi
>>> - added dt bindings documentation
>>> - added cleanup patches
>>> - DMA enabled by default
>>>
>>> Most notable changes from v4:
>>> - collected tags
>>> - used INT pin name properly
>>> - hopefully all comments taken into account
>>>
>>> Also note that driver will fail probe OneNAND chip after patch 13 and start
>>> working again after patch 14.
>>
>> Well, breaking bisectability is never a good thing, this being said, I
>> won't complain if TI maintainers are okay with that.
> 
> There should not be any reason to break git bisect for booting at all,
> what exactly is the issue here?
> 
>>> Testing and benchmarking very welcome.
>>
>> Let me know when you think this series is ready to be merged.
> 
> Well we need Aaro to test this on n8x0 as my n800 is currently not
> booting at all.
> 
>>> Depends on "memory: omap-gpmc: Make 'bank-width' property optional"
>>> https://patchwork.kernel.org/patch/10043259/
>>
>> Hm, I see this patch has been applied to the omap tree, so maybe it's
>> simpler if everything goes through this tree. I don't plan to modify
>> onenand related stuff in this release anyway.
> 
> Maybe Roger can provide you with an immutable commit with just that
> patch?

Here you go

The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:

  Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)

are available in the git repository at:

  https://github.com/rogerq/linux.git for-v4.16/gpmc-omap-immutable

for you to fetch changes up to c18a7ac3398d0cef29749f9568666db8321aa4c9:

  memory: omap-gpmc: Make 'bank-width' property optional (2017-12-01 15:37:49 +0200)

----------------------------------------------------------------
Ladislav Michl (1):
      memory: omap-gpmc: Make 'bank-width' property optional

 drivers/memory/omap-gpmc.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

-- 
cheers,
-roger

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Re: [PATCH v5 01/16] dt-bindings: mtd: gpmc-onenand: Update properties description

[Roger Quadros]

Ladislav,

On 30/11/17 15:09, Ladislav Michl wrote:
> On Thu, Nov 30, 2017 at 11:25:44AM +0100, Boris Brezillon wrote:
>> +Rob and the DT ML
>>
>> On Wed, 15 Nov 2017 17:24:58 +0100
>> Ladislav Michl <ladis@linux-mips.org> wrote:
>>
>>> Compatible property is required for OMAP2+ mtd driver. Also
>>> add INT pin gpio description and delete unused dma-channel
>>> property.
>>>
>>> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
>>> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
>>> Acked-by: Roger Quadros <rogerq@ti.com>
>>> ---
>>>
>>> Changes in v5:
>>> - renamed R/B pin to INT pin
>>>
>>> Changes in v4:
>>> - new patch
>>>
>>> Changes in v3: None
>>> Changes in v2: None
>>>
>>>  Documentation/devicetree/bindings/mtd/gpmc-onenand.txt | 6 ++++--
>>>  1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
>>> index b6e8bfd024f4..e9f01a963a0a 100644
>>> --- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
>>> +++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
>>> @@ -9,13 +9,14 @@ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
>>>  
>>>  Required properties:
>>>  
>>> + - compatible:		"ti,omap2-onenand"
>>
>> Don't you break backward compat by adding this new requirement?
> 
> I was told it is okay in this case as OneNAND conversion to DT is unfinished.
> There was compat fixup code in earlier versions of patchset and it was dropped
> later. If others see it opposite way I can add it back.
> 

If it is possible not to break backward compatibility then we shouldn't.
Only if things are getting real messy because of the poor way the earlier DT
implementation was done we can consider it as an exception.

I thought we rely on GPMC timings entirely from the DT now and so things don't
work with older DT nodes?

>>>   - reg:			The CS line the peripheral is connected to
>>> - - gpmc,device-width	Width of the ONENAND device connected to the GPMC
>>> + - gpmc,device-width:	Width of the ONENAND device connected to the GPMC
>>>  			in bytes. Must be 1 or 2.
>>>  
>>>  Optional properties:
>>>  
>>> - - dma-channel:		DMA Channel index
>>> + - int-gpios:		GPIO specifier for the INT pin.
>>>  
>>>  For inline partition table parsing (optional):
>>>  
>>> @@ -35,6 +36,7 @@ Example for an OMAP3430 board:
>>>  		#size-cells = <1>;
>>>  
>>>  		onenand@0 {
>>> +			compatible = "ti,omap2-onenand";
>>>  			reg = <0 0 0>; /* CS0, offset 0 */
>>>  			gpmc,device-width = <2>;
>>>  

-- 
cheers,
-roger

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH v5 01/16] dt-bindings: mtd: gpmc-onenand: Update properties description

[Roger Quadros]

Ladislav,

On 30/11/17 15:09, Ladislav Michl wrote:
> On Thu, Nov 30, 2017 at 11:25:44AM +0100, Boris Brezillon wrote:
>> +Rob and the DT ML
>>
>> On Wed, 15 Nov 2017 17:24:58 +0100
>> Ladislav Michl <ladis@linux-mips.org> wrote:
>>
>>> Compatible property is required for OMAP2+ mtd driver. Also
>>> add INT pin gpio description and delete unused dma-channel
>>> property.
>>>
>>> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
>>> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
>>> Acked-by: Roger Quadros <rogerq@ti.com>
>>> ---
>>>
>>> Changes in v5:
>>> - renamed R/B pin to INT pin
>>>
>>> Changes in v4:
>>> - new patch
>>>
>>> Changes in v3: None
>>> Changes in v2: None
>>>
>>>  Documentation/devicetree/bindings/mtd/gpmc-onenand.txt | 6 ++++--
>>>  1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
>>> index b6e8bfd024f4..e9f01a963a0a 100644
>>> --- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
>>> +++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
>>> @@ -9,13 +9,14 @@ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
>>>  
>>>  Required properties:
>>>  
>>> + - compatible:		"ti,omap2-onenand"
>>
>> Don't you break backward compat by adding this new requirement?
> 
> I was told it is okay in this case as OneNAND conversion to DT is unfinished.
> There was compat fixup code in earlier versions of patchset and it was dropped
> later. If others see it opposite way I can add it back.
> 

If it is possible not to break backward compatibility then we shouldn't.
Only if things are getting real messy because of the poor way the earlier DT
implementation was done we can consider it as an exception.

I thought we rely on GPMC timings entirely from the DT now and so things don't
work with older DT nodes?

>>>   - reg:			The CS line the peripheral is connected to
>>> - - gpmc,device-width	Width of the ONENAND device connected to the GPMC
>>> + - gpmc,device-width:	Width of the ONENAND device connected to the GPMC
>>>  			in bytes. Must be 1 or 2.
>>>  
>>>  Optional properties:
>>>  
>>> - - dma-channel:		DMA Channel index
>>> + - int-gpios:		GPIO specifier for the INT pin.
>>>  
>>>  For inline partition table parsing (optional):
>>>  
>>> @@ -35,6 +36,7 @@ Example for an OMAP3430 board:
>>>  		#size-cells = <1>;
>>>  
>>>  		onenand@0 {
>>> +			compatible = "ti,omap2-onenand";
>>>  			reg = <0 0 0>; /* CS0, offset 0 */
>>>  			gpmc,device-width = <2>;
>>>  

-- 
cheers,
-roger

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Re: [PATCH v5 01/16] dt-bindings: mtd: gpmc-onenand: Update properties description

[Ladislav Michl]

Roger,

On Fri, Dec 15, 2017 at 12:18:59PM +0200, Roger Quadros wrote:
> Ladislav,
> 
> On 30/11/17 15:09, Ladislav Michl wrote:
> > On Thu, Nov 30, 2017 at 11:25:44AM +0100, Boris Brezillon wrote:
> >> +Rob and the DT ML
> >>
> >> On Wed, 15 Nov 2017 17:24:58 +0100
> >> Ladislav Michl <ladis-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org> wrote:
> >>
> >>> Compatible property is required for OMAP2+ mtd driver. Also
> >>> add INT pin gpio description and delete unused dma-channel
> >>> property.
> >>>
> >>> Signed-off-by: Ladislav Michl <ladis-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>
> >>> Reviewed-by: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
> >>> Acked-by: Roger Quadros <rogerq-l0cyMroinI0@public.gmane.org>
> >>> ---
> >>>
> >>> Changes in v5:
> >>> - renamed R/B pin to INT pin
> >>>
> >>> Changes in v4:
> >>> - new patch
> >>>
> >>> Changes in v3: None
> >>> Changes in v2: None
> >>>
> >>>  Documentation/devicetree/bindings/mtd/gpmc-onenand.txt | 6 ++++--
> >>>  1 file changed, 4 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> >>> index b6e8bfd024f4..e9f01a963a0a 100644
> >>> --- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> >>> +++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> >>> @@ -9,13 +9,14 @@ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
> >>>  
> >>>  Required properties:
> >>>  
> >>> + - compatible:		"ti,omap2-onenand"
> >>
> >> Don't you break backward compat by adding this new requirement?
> > 
> > I was told it is okay in this case as OneNAND conversion to DT is unfinished.
> > There was compat fixup code in earlier versions of patchset and it was dropped
> > later. If others see it opposite way I can add it back.
> > 
> 
> If it is possible not to break backward compatibility then we shouldn't.
> Only if things are getting real messy because of the poor way the earlier DT
> implementation was done we can consider it as an exception.

Well, it is possible to reintroduce fixup. Based on other posts on linux-omap
mailing list, it seems that n900, etc. support is still under heavy development,
so people are updating both kernel and dtb. That's why I happily agreed on
removing fixup.

Of course I'd like to hear opinion from n8x0 and n900 people and also would be
very happy if someone could finally test on OMAP2 device.

> I thought we rely on GPMC timings entirely from the DT now and so things don't
> work with older DT nodes?

Well, they do work as long as DT contains correct timings. Mainline driver just
ignores them a does calculations on its own, so it works even with wrong DT
timings as long as bootloader configured something reasonable (otherwise it
doe not work at all).

This is no longer the case. Now, driver is expecting reasonable timings, enough
good to get device probed. Driver then calculates optimized timings based on
actual OneNAND chip ised.

Thank you,
	ladis
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Re: [PATCH v5 01/16] dt-bindings: mtd: gpmc-onenand: Update properties description

[Ladislav Michl]

Roger,

On Fri, Dec 15, 2017 at 12:18:59PM +0200, Roger Quadros wrote:
> Ladislav,
> 
> On 30/11/17 15:09, Ladislav Michl wrote:
> > On Thu, Nov 30, 2017 at 11:25:44AM +0100, Boris Brezillon wrote:
> >> +Rob and the DT ML
> >>
> >> On Wed, 15 Nov 2017 17:24:58 +0100
> >> Ladislav Michl <ladis@linux-mips.org> wrote:
> >>
> >>> Compatible property is required for OMAP2+ mtd driver. Also
> >>> add INT pin gpio description and delete unused dma-channel
> >>> property.
> >>>
> >>> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
> >>> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> >>> Acked-by: Roger Quadros <rogerq@ti.com>
> >>> ---
> >>>
> >>> Changes in v5:
> >>> - renamed R/B pin to INT pin
> >>>
> >>> Changes in v4:
> >>> - new patch
> >>>
> >>> Changes in v3: None
> >>> Changes in v2: None
> >>>
> >>>  Documentation/devicetree/bindings/mtd/gpmc-onenand.txt | 6 ++++--
> >>>  1 file changed, 4 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> >>> index b6e8bfd024f4..e9f01a963a0a 100644
> >>> --- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> >>> +++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
> >>> @@ -9,13 +9,14 @@ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
> >>>  
> >>>  Required properties:
> >>>  
> >>> + - compatible:		"ti,omap2-onenand"
> >>
> >> Don't you break backward compat by adding this new requirement?
> > 
> > I was told it is okay in this case as OneNAND conversion to DT is unfinished.
> > There was compat fixup code in earlier versions of patchset and it was dropped
> > later. If others see it opposite way I can add it back.
> > 
> 
> If it is possible not to break backward compatibility then we shouldn't.
> Only if things are getting real messy because of the poor way the earlier DT
> implementation was done we can consider it as an exception.

Well, it is possible to reintroduce fixup. Based on other posts on linux-omap
mailing list, it seems that n900, etc. support is still under heavy development,
so people are updating both kernel and dtb. That's why I happily agreed on
removing fixup.

Of course I'd like to hear opinion from n8x0 and n900 people and also would be
very happy if someone could finally test on OMAP2 device.

> I thought we rely on GPMC timings entirely from the DT now and so things don't
> work with older DT nodes?

Well, they do work as long as DT contains correct timings. Mainline driver just
ignores them a does calculations on its own, so it works even with wrong DT
timings as long as bootloader configured something reasonable (otherwise it
doe not work at all).

This is no longer the case. Now, driver is expecting reasonable timings, enough
good to get device probed. Driver then calculates optimized timings based on
actual OneNAND chip ised.

Thank you,
	ladis

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Ladislav Michl]

Just a very gentle ping, more bellow...

On Fri, Dec 01, 2017 at 03:43:55PM +0200, Roger Quadros wrote:
> On 30/11/17 18:09, Tony Lindgren wrote:
> > * Boris Brezillon <boris.brezillon@free-electrons.com> [171130 10:21]:
> >> On Wed, 15 Nov 2017 17:23:06 +0100
> >> Ladislav Michl <ladis@linux-mips.org> wrote:
> >>
> >>> this patch serie updates OMAP2+ OneNAND driver to the present times, making
> >>> it fully DT configurable, using libgpio and dmaengine apis - those are
> >>> optional, driver will work without them.
> >>>
> >>> Please note that unlike previous driver version, which basically ignored
> >>> DT specified timings, this one relies on it, so it is important to get
> >>> it right in your DT (dumping it from previous kernel version).
> >>>
> >>> In case synchronous timings is requested, it is okay to specify timings
> >>> for the slowest chip ever used for you board as it is evetually optimized
> >>> after chip probe.
> >>>
> >>> Original driver used DMA only if user specified INT gpio in platform
> >>> data, now DMA is used unconditionally and PIO mode is used as fallback.
> >>>
> >>> In case anyone wants to give it a try, few DT related changes are needed:
> >>> - onenand node needs 'ti,omap2-onenand' compatible (for mailine boards this is
> >>>   done in patch 2)
> >>> - to use INT pin, int-gpios needs to be specified (for n900 and n8x0 this is
> >>>   done in patch 16, however patch lacks pinmux configuration.
> >>>
> >>> Most notable changes from v3:
> >>> - added dmaengine patches by Peter Ujfalusi
> >>> - added dt bindings documentation
> >>> - added cleanup patches
> >>> - DMA enabled by default
> >>>
> >>> Most notable changes from v4:
> >>> - collected tags
> >>> - used INT pin name properly
> >>> - hopefully all comments taken into account
> >>>
> >>> Also note that driver will fail probe OneNAND chip after patch 13 and start
> >>> working again after patch 14.
> >>
> >> Well, breaking bisectability is never a good thing, this being said, I
> >> won't complain if TI maintainers are okay with that.
> > 
> > There should not be any reason to break git bisect for booting at all,
> > what exactly is the issue here?
> > 
> >>> Testing and benchmarking very welcome.
> >>
> >> Let me know when you think this series is ready to be merged.
> > 
> > Well we need Aaro to test this on n8x0 as my n800 is currently not
> > booting at all.
> > 
> >>> Depends on "memory: omap-gpmc: Make 'bank-width' property optional"
> >>> https://patchwork.kernel.org/patch/10043259/
> >>
> >> Hm, I see this patch has been applied to the omap tree, so maybe it's
> >> simpler if everything goes through this tree. I don't plan to modify
> >> onenand related stuff in this release anyway.
> > 
> > Maybe Roger can provide you with an immutable commit with just that
> > patch?
> 
> Here you go

Thank you :)

Merge window is really close now and patches seems still to be untested on
n8x0. So unless someone is going to test it soon, I'll pick used N800 on
ebay :-/

I would also appreciate final statement which tree will used to merge this
patchset. So far everyone seems to agree this patchset will enter via single
tree, right? If that is the case I'm proposing to squash patches 13 and 14
into single patch, so we do not break bisecting.

> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
> 
>   Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
> 
> are available in the git repository at:
> 
>   https://github.com/rogerq/linux.git for-v4.16/gpmc-omap-immutable
> 
> for you to fetch changes up to c18a7ac3398d0cef29749f9568666db8321aa4c9:
> 
>   memory: omap-gpmc: Make 'bank-width' property optional (2017-12-01 15:37:49 +0200)
> 
> ----------------------------------------------------------------
> Ladislav Michl (1):
>       memory: omap-gpmc: Make 'bank-width' property optional
> 
>  drivers/memory/omap-gpmc.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> -- 
> cheers,
> -roger
> 
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

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Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Ladislav Michl]

Just a very gentle ping, more bellow...

On Fri, Dec 01, 2017 at 03:43:55PM +0200, Roger Quadros wrote:
> On 30/11/17 18:09, Tony Lindgren wrote:
> > * Boris Brezillon <boris.brezillon@free-electrons.com> [171130 10:21]:
> >> On Wed, 15 Nov 2017 17:23:06 +0100
> >> Ladislav Michl <ladis@linux-mips.org> wrote:
> >>
> >>> this patch serie updates OMAP2+ OneNAND driver to the present times, making
> >>> it fully DT configurable, using libgpio and dmaengine apis - those are
> >>> optional, driver will work without them.
> >>>
> >>> Please note that unlike previous driver version, which basically ignored
> >>> DT specified timings, this one relies on it, so it is important to get
> >>> it right in your DT (dumping it from previous kernel version).
> >>>
> >>> In case synchronous timings is requested, it is okay to specify timings
> >>> for the slowest chip ever used for you board as it is evetually optimized
> >>> after chip probe.
> >>>
> >>> Original driver used DMA only if user specified INT gpio in platform
> >>> data, now DMA is used unconditionally and PIO mode is used as fallback.
> >>>
> >>> In case anyone wants to give it a try, few DT related changes are needed:
> >>> - onenand node needs 'ti,omap2-onenand' compatible (for mailine boards this is
> >>>   done in patch 2)
> >>> - to use INT pin, int-gpios needs to be specified (for n900 and n8x0 this is
> >>>   done in patch 16, however patch lacks pinmux configuration.
> >>>
> >>> Most notable changes from v3:
> >>> - added dmaengine patches by Peter Ujfalusi
> >>> - added dt bindings documentation
> >>> - added cleanup patches
> >>> - DMA enabled by default
> >>>
> >>> Most notable changes from v4:
> >>> - collected tags
> >>> - used INT pin name properly
> >>> - hopefully all comments taken into account
> >>>
> >>> Also note that driver will fail probe OneNAND chip after patch 13 and start
> >>> working again after patch 14.
> >>
> >> Well, breaking bisectability is never a good thing, this being said, I
> >> won't complain if TI maintainers are okay with that.
> > 
> > There should not be any reason to break git bisect for booting at all,
> > what exactly is the issue here?
> > 
> >>> Testing and benchmarking very welcome.
> >>
> >> Let me know when you think this series is ready to be merged.
> > 
> > Well we need Aaro to test this on n8x0 as my n800 is currently not
> > booting at all.
> > 
> >>> Depends on "memory: omap-gpmc: Make 'bank-width' property optional"
> >>> https://patchwork.kernel.org/patch/10043259/
> >>
> >> Hm, I see this patch has been applied to the omap tree, so maybe it's
> >> simpler if everything goes through this tree. I don't plan to modify
> >> onenand related stuff in this release anyway.
> > 
> > Maybe Roger can provide you with an immutable commit with just that
> > patch?
> 
> Here you go

Thank you :)

Merge window is really close now and patches seems still to be untested on
n8x0. So unless someone is going to test it soon, I'll pick used N800 on
ebay :-/

I would also appreciate final statement which tree will used to merge this
patchset. So far everyone seems to agree this patchset will enter via single
tree, right? If that is the case I'm proposing to squash patches 13 and 14
into single patch, so we do not break bisecting.

> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
> 
>   Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
> 
> are available in the git repository at:
> 
>   https://github.com/rogerq/linux.git for-v4.16/gpmc-omap-immutable
> 
> for you to fetch changes up to c18a7ac3398d0cef29749f9568666db8321aa4c9:
> 
>   memory: omap-gpmc: Make 'bank-width' property optional (2017-12-01 15:37:49 +0200)
> 
> ----------------------------------------------------------------
> Ladislav Michl (1):
>       memory: omap-gpmc: Make 'bank-width' property optional
> 
>  drivers/memory/omap-gpmc.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> -- 
> cheers,
> -roger
> 
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Aaro Koskinen]

Hi,

On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
> Merge window is really close now and patches seems still to be untested on
> n8x0. So unless someone is going to test it soon, I'll pick used N800 on
> ebay :-/

Today I tried to test them on Nokia N810, and I get:

[    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
[    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
[    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22

With plain v4.15-rc7+ it probes fine.

A.

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Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Aaro Koskinen]

Hi,

On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
> Merge window is really close now and patches seems still to be untested on
> n8x0. So unless someone is going to test it soon, I'll pick used N800 on
> ebay :-/

Today I tried to test them on Nokia N810, and I get:

[    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
[    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
[    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22

With plain v4.15-rc7+ it probes fine.

A.

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Ladislav Michl]

Aaro,

On Tue, Jan 09, 2018 at 11:01:14PM +0200, Aaro Koskinen wrote:
> Hi,
> 
> On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
> > Merge window is really close now and patches seems still to be untested on
> > n8x0. So unless someone is going to test it soon, I'll pick used N800 on
> > ebay :-/
> 
> Today I tried to test them on Nokia N810, and I get:
> 
> [    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> [    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> [    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
> [    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> 
> With plain v4.15-rc7+ it probes fine.

Thank you for testing. As stated in cover letter, you need also
https://patchwork.kernel.org/patch/10043259/
which can be also found in Roger's branch
https://github.com/rogerq/linux/commits/for-v4.16/gpmc-omap-immutable
(see previous replies in this thread and also discussion about OneNAND
DT node)

Thank you,
	ladis

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Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Ladislav Michl]

Aaro,

On Tue, Jan 09, 2018 at 11:01:14PM +0200, Aaro Koskinen wrote:
> Hi,
> 
> On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
> > Merge window is really close now and patches seems still to be untested on
> > n8x0. So unless someone is going to test it soon, I'll pick used N800 on
> > ebay :-/
> 
> Today I tried to test them on Nokia N810, and I get:
> 
> [    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> [    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> [    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
> [    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> 
> With plain v4.15-rc7+ it probes fine.

Thank you for testing. As stated in cover letter, you need also
https://patchwork.kernel.org/patch/10043259/
which can be also found in Roger's branch
https://github.com/rogerq/linux/commits/for-v4.16/gpmc-omap-immutable
(see previous replies in this thread and also discussion about OneNAND
DT node)

Thank you,
	ladis

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Aaro Koskinen]

Hi,

On Wed, Jan 10, 2018 at 10:20:58AM +0100, Ladislav Michl wrote:
> On Tue, Jan 09, 2018 at 11:01:14PM +0200, Aaro Koskinen wrote:
> > On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
> > > Merge window is really close now and patches seems still to be untested on
> > > n8x0. So unless someone is going to test it soon, I'll pick used N800 on
> > > ebay :-/
> > 
> > Today I tried to test them on Nokia N810, and I get:
> > 
> > [    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> > [    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> > [    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
> > [    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> > 
> > With plain v4.15-rc7+ it probes fine.
> 
> Thank you for testing. As stated in cover letter, you need also
> https://patchwork.kernel.org/patch/10043259/
> which can be also found in Roger's branch
> https://github.com/rogerq/linux/commits/for-v4.16/gpmc-omap-immutable
> (see previous replies in this thread and also discussion about OneNAND
> DT node)

I applied it, and now get:

[    0.174987] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
[    0.175048] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[    0.177703] omap-gpmc 6800a000.gpmc: Incompatible OneNAND node: missing compatible
[    0.177764] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22

A.

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Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Aaro Koskinen]

Hi,

On Wed, Jan 10, 2018 at 10:20:58AM +0100, Ladislav Michl wrote:
> On Tue, Jan 09, 2018 at 11:01:14PM +0200, Aaro Koskinen wrote:
> > On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
> > > Merge window is really close now and patches seems still to be untested on
> > > n8x0. So unless someone is going to test it soon, I'll pick used N800 on
> > > ebay :-/
> > 
> > Today I tried to test them on Nokia N810, and I get:
> > 
> > [    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> > [    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> > [    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
> > [    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> > 
> > With plain v4.15-rc7+ it probes fine.
> 
> Thank you for testing. As stated in cover letter, you need also
> https://patchwork.kernel.org/patch/10043259/
> which can be also found in Roger's branch
> https://github.com/rogerq/linux/commits/for-v4.16/gpmc-omap-immutable
> (see previous replies in this thread and also discussion about OneNAND
> DT node)

I applied it, and now get:

[    0.174987] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
[    0.175048] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[    0.177703] omap-gpmc 6800a000.gpmc: Incompatible OneNAND node: missing compatible
[    0.177764] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22

A.

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Ladislav Michl]

+Rob and the DT ML

On Wed, Jan 10, 2018 at 07:35:19PM +0200, Aaro Koskinen wrote:
> Hi,
> 
> On Wed, Jan 10, 2018 at 10:20:58AM +0100, Ladislav Michl wrote:
> > On Tue, Jan 09, 2018 at 11:01:14PM +0200, Aaro Koskinen wrote:
> > > On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
> > > > Merge window is really close now and patches seems still to be untested on
> > > > n8x0. So unless someone is going to test it soon, I'll pick used N800 on
> > > > ebay :-/
> > > 
> > > Today I tried to test them on Nokia N810, and I get:
> > > 
> > > [    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> > > [    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> > > [    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
> > > [    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> > > 
> > > With plain v4.15-rc7+ it probes fine.
> > 
> > Thank you for testing. As stated in cover letter, you need also
> > https://patchwork.kernel.org/patch/10043259/
> > which can be also found in Roger's branch
> > https://github.com/rogerq/linux/commits/for-v4.16/gpmc-omap-immutable
> > (see previous replies in this thread and also discussion about OneNAND
> > DT node)
> 
> I applied it, and now get:
> 
> [    0.174987] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> [    0.175048] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> [    0.177703] omap-gpmc 6800a000.gpmc: Incompatible OneNAND node: missing compatible
> [    0.177764] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22

As expected without reading discussion about OneNAND DT node :)

In short, this version expects "ti,omap2-onenand" compatible.

In earlier version of this patchset there was fixup present, so driver
worked even without compatible. Later on (17 Oct 2017 11:46:51 +0300)
Roger objected (https://www.spinics.net/lists/linux-omap/msg139576.html):
"I don't want to fixup broken DTs like this as they will go silently without
being fixed. Let's instead just error out after the dev_warn(). This will
force us to fix all DT nodes."
So fixup was removed. I know N900 support is under heavy development
in mainline, but if n8x0 is considered finished and stable, we should
reintroduce fixup. Thoughts?

Thank you for your patience,
	ladis
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Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Ladislav Michl]

+Rob and the DT ML

On Wed, Jan 10, 2018 at 07:35:19PM +0200, Aaro Koskinen wrote:
> Hi,
> 
> On Wed, Jan 10, 2018 at 10:20:58AM +0100, Ladislav Michl wrote:
> > On Tue, Jan 09, 2018 at 11:01:14PM +0200, Aaro Koskinen wrote:
> > > On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
> > > > Merge window is really close now and patches seems still to be untested on
> > > > n8x0. So unless someone is going to test it soon, I'll pick used N800 on
> > > > ebay :-/
> > > 
> > > Today I tried to test them on Nokia N810, and I get:
> > > 
> > > [    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> > > [    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> > > [    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
> > > [    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> > > 
> > > With plain v4.15-rc7+ it probes fine.
> > 
> > Thank you for testing. As stated in cover letter, you need also
> > https://patchwork.kernel.org/patch/10043259/
> > which can be also found in Roger's branch
> > https://github.com/rogerq/linux/commits/for-v4.16/gpmc-omap-immutable
> > (see previous replies in this thread and also discussion about OneNAND
> > DT node)
> 
> I applied it, and now get:
> 
> [    0.174987] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> [    0.175048] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> [    0.177703] omap-gpmc 6800a000.gpmc: Incompatible OneNAND node: missing compatible
> [    0.177764] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22

As expected without reading discussion about OneNAND DT node :)

In short, this version expects "ti,omap2-onenand" compatible.

In earlier version of this patchset there was fixup present, so driver
worked even without compatible. Later on (17 Oct 2017 11:46:51 +0300)
Roger objected (https://www.spinics.net/lists/linux-omap/msg139576.html):
"I don't want to fixup broken DTs like this as they will go silently without
being fixed. Let's instead just error out after the dev_warn(). This will
force us to fix all DT nodes."
So fixup was removed. I know N900 support is under heavy development
in mainline, but if n8x0 is considered finished and stable, we should
reintroduce fixup. Thoughts?

Thank you for your patience,
	ladis

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Aaro Koskinen]

Hi,

On Wed, Jan 10, 2018 at 07:35:19PM +0200, Aaro Koskinen wrote:
> On Wed, Jan 10, 2018 at 10:20:58AM +0100, Ladislav Michl wrote:
> > On Tue, Jan 09, 2018 at 11:01:14PM +0200, Aaro Koskinen wrote:
> > > On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
> > > > Merge window is really close now and patches seems still to be untested on
> > > > n8x0. So unless someone is going to test it soon, I'll pick used N800 on
> > > > ebay :-/
> > > 
> > > Today I tried to test them on Nokia N810, and I get:
> > > 
> > > [    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> > > [    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> > > [    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
> > > [    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> > > 
> > > With plain v4.15-rc7+ it probes fine.
> > 
> > Thank you for testing. As stated in cover letter, you need also
> > https://patchwork.kernel.org/patch/10043259/
> > which can be also found in Roger's branch
> > https://github.com/rogerq/linux/commits/for-v4.16/gpmc-omap-immutable
> > (see previous replies in this thread and also discussion about OneNAND
> > DT node)
> 
> I applied it, and now get:
> 
> [    0.174987] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> [    0.175048] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> [    0.177703] omap-gpmc 6800a000.gpmc: Incompatible OneNAND node: missing compatible
> [    0.177764] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22

Crap, I think something is wrong in my kexec. It seems to pass the DTB from an
old kernel, although the new kernel has a new appended DTB... Need to
investigate, sorry for noise.

A.

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Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Aaro Koskinen]

Hi,

On Wed, Jan 10, 2018 at 07:35:19PM +0200, Aaro Koskinen wrote:
> On Wed, Jan 10, 2018 at 10:20:58AM +0100, Ladislav Michl wrote:
> > On Tue, Jan 09, 2018 at 11:01:14PM +0200, Aaro Koskinen wrote:
> > > On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
> > > > Merge window is really close now and patches seems still to be untested on
> > > > n8x0. So unless someone is going to test it soon, I'll pick used N800 on
> > > > ebay :-/
> > > 
> > > Today I tried to test them on Nokia N810, and I get:
> > > 
> > > [    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> > > [    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> > > [    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
> > > [    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> > > 
> > > With plain v4.15-rc7+ it probes fine.
> > 
> > Thank you for testing. As stated in cover letter, you need also
> > https://patchwork.kernel.org/patch/10043259/
> > which can be also found in Roger's branch
> > https://github.com/rogerq/linux/commits/for-v4.16/gpmc-omap-immutable
> > (see previous replies in this thread and also discussion about OneNAND
> > DT node)
> 
> I applied it, and now get:
> 
> [    0.174987] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> [    0.175048] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> [    0.177703] omap-gpmc 6800a000.gpmc: Incompatible OneNAND node: missing compatible
> [    0.177764] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22

Crap, I think something is wrong in my kexec. It seems to pass the DTB from an
old kernel, although the new kernel has a new appended DTB... Need to
investigate, sorry for noise.

A.

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Roger Quadros]

On 10/01/18 23:27, Aaro Koskinen wrote:
> Hi,
> 
> On Wed, Jan 10, 2018 at 07:35:19PM +0200, Aaro Koskinen wrote:
>> On Wed, Jan 10, 2018 at 10:20:58AM +0100, Ladislav Michl wrote:
>>> On Tue, Jan 09, 2018 at 11:01:14PM +0200, Aaro Koskinen wrote:
>>>> On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
>>>>> Merge window is really close now and patches seems still to be untested on
>>>>> n8x0. So unless someone is going to test it soon, I'll pick used N800 on
>>>>> ebay :-/
>>>>
>>>> Today I tried to test them on Nokia N810, and I get:
>>>>
>>>> [    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
>>>> [    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
>>>> [    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
>>>> [    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
>>>>
>>>> With plain v4.15-rc7+ it probes fine.
>>>
>>> Thank you for testing. As stated in cover letter, you need also
>>> https://patchwork.kernel.org/patch/10043259/
>>> which can be also found in Roger's branch
>>> https://github.com/rogerq/linux/commits/for-v4.16/gpmc-omap-immutable
>>> (see previous replies in this thread and also discussion about OneNAND
>>> DT node)
>>
>> I applied it, and now get:
>>
>> [    0.174987] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
>> [    0.175048] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
>> [    0.177703] omap-gpmc 6800a000.gpmc: Incompatible OneNAND node: missing compatible
>> [    0.177764] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> 
> Crap, I think something is wrong in my kexec. It seems to pass the DTB from an
> old kernel, although the new kernel has a new appended DTB... Need to
> investigate, sorry for noise.
> 
> A.
> 

Aaro,

You will still need to add "ti,omap2-onenand" compatible property to the n800/810 onenand node for it to work.

-- 
cheers,
-roger

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Roger Quadros]

On 10/01/18 23:27, Aaro Koskinen wrote:
> Hi,
> 
> On Wed, Jan 10, 2018 at 07:35:19PM +0200, Aaro Koskinen wrote:
>> On Wed, Jan 10, 2018 at 10:20:58AM +0100, Ladislav Michl wrote:
>>> On Tue, Jan 09, 2018 at 11:01:14PM +0200, Aaro Koskinen wrote:
>>>> On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
>>>>> Merge window is really close now and patches seems still to be untested on
>>>>> n8x0. So unless someone is going to test it soon, I'll pick used N800 on
>>>>> ebay :-/
>>>>
>>>> Today I tried to test them on Nokia N810, and I get:
>>>>
>>>> [    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
>>>> [    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
>>>> [    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
>>>> [    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
>>>>
>>>> With plain v4.15-rc7+ it probes fine.
>>>
>>> Thank you for testing. As stated in cover letter, you need also
>>> https://patchwork.kernel.org/patch/10043259/
>>> which can be also found in Roger's branch
>>> https://github.com/rogerq/linux/commits/for-v4.16/gpmc-omap-immutable
>>> (see previous replies in this thread and also discussion about OneNAND
>>> DT node)
>>
>> I applied it, and now get:
>>
>> [    0.174987] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
>> [    0.175048] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
>> [    0.177703] omap-gpmc 6800a000.gpmc: Incompatible OneNAND node: missing compatible
>> [    0.177764] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> 
> Crap, I think something is wrong in my kexec. It seems to pass the DTB from an
> old kernel, although the new kernel has a new appended DTB... Need to
> investigate, sorry for noise.
> 
> A.
> 

Aaro,

You will still need to add "ti,omap2-onenand" compatible property to the n800/810 onenand node for it to work.

-- 
cheers,
-roger

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Aaro Koskinen]

Hi,

On Wed, Jan 10, 2018 at 10:13:25PM +0100, Ladislav Michl wrote:
> On Wed, Jan 10, 2018 at 07:35:19PM +0200, Aaro Koskinen wrote:
> > On Wed, Jan 10, 2018 at 10:20:58AM +0100, Ladislav Michl wrote:
> > > On Tue, Jan 09, 2018 at 11:01:14PM +0200, Aaro Koskinen wrote:
> > > > On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
> > > > > Merge window is really close now and patches seems still to be untested on
> > > > > n8x0. So unless someone is going to test it soon, I'll pick used N800 on
> > > > > ebay :-/
> > > > 
> > > > Today I tried to test them on Nokia N810, and I get:
> > > > 
> > > > [    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> > > > [    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> > > > [    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
> > > > [    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> > > > 
> > > > With plain v4.15-rc7+ it probes fine.
> > > 
> > > Thank you for testing. As stated in cover letter, you need also
> > > https://patchwork.kernel.org/patch/10043259/
> > > which can be also found in Roger's branch
> > > https://github.com/rogerq/linux/commits/for-v4.16/gpmc-omap-immutable
> > > (see previous replies in this thread and also discussion about OneNAND
> > > DT node)
> > 
> > I applied it, and now get:
> > 
> > [    0.174987] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> > [    0.175048] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> > [    0.177703] omap-gpmc 6800a000.gpmc: Incompatible OneNAND node: missing compatible
> > [    0.177764] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> 
> As expected without reading discussion about OneNAND DT node :)
> 
> In short, this version expects "ti,omap2-onenand" compatible.

Right. I didn't realize by bootloader was passing the DTB from an old
kernel.

So after fixing my boot I got the patches working N800 and N810: I was
able to read and write on old JFFS2 file systems without any issues. So
you can add for the series:

Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>

> In earlier version of this patchset there was fixup present, so driver
> worked even without compatible. Later on (17 Oct 2017 11:46:51 +0300)
> Roger objected (https://www.spinics.net/lists/linux-omap/msg139576.html):
> "I don't want to fixup broken DTs like this as they will go silently without
> being fixed. Let's instead just error out after the dev_warn(). This will
> force us to fix all DT nodes."
> So fixup was removed. I know N900 support is under heavy development
> in mainline, but if n8x0 is considered finished and stable, we should
> reintroduce fixup. Thoughts?

N8x0 support is also "under development", and we are fine with updating
and always using latest in-tree DTs.

A.

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Aaro Koskinen]

Hi,

On Wed, Jan 10, 2018 at 10:13:25PM +0100, Ladislav Michl wrote:
> On Wed, Jan 10, 2018 at 07:35:19PM +0200, Aaro Koskinen wrote:
> > On Wed, Jan 10, 2018 at 10:20:58AM +0100, Ladislav Michl wrote:
> > > On Tue, Jan 09, 2018 at 11:01:14PM +0200, Aaro Koskinen wrote:
> > > > On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
> > > > > Merge window is really close now and patches seems still to be untested on
> > > > > n8x0. So unless someone is going to test it soon, I'll pick used N800 on
> > > > > ebay :-/
> > > > 
> > > > Today I tried to test them on Nokia N810, and I get:
> > > > 
> > > > [    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> > > > [    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> > > > [    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
> > > > [    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> > > > 
> > > > With plain v4.15-rc7+ it probes fine.
> > > 
> > > Thank you for testing. As stated in cover letter, you need also
> > > https://patchwork.kernel.org/patch/10043259/
> > > which can be also found in Roger's branch
> > > https://github.com/rogerq/linux/commits/for-v4.16/gpmc-omap-immutable
> > > (see previous replies in this thread and also discussion about OneNAND
> > > DT node)
> > 
> > I applied it, and now get:
> > 
> > [    0.174987] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> > [    0.175048] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> > [    0.177703] omap-gpmc 6800a000.gpmc: Incompatible OneNAND node: missing compatible
> > [    0.177764] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> 
> As expected without reading discussion about OneNAND DT node :)
> 
> In short, this version expects "ti,omap2-onenand" compatible.

Right. I didn't realize by bootloader was passing the DTB from an old
kernel.

So after fixing my boot I got the patches working N800 and N810: I was
able to read and write on old JFFS2 file systems without any issues. So
you can add for the series:

Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>

> In earlier version of this patchset there was fixup present, so driver
> worked even without compatible. Later on (17 Oct 2017 11:46:51 +0300)
> Roger objected (https://www.spinics.net/lists/linux-omap/msg139576.html):
> "I don't want to fixup broken DTs like this as they will go silently without
> being fixed. Let's instead just error out after the dev_warn(). This will
> force us to fix all DT nodes."
> So fixup was removed. I know N900 support is under heavy development
> in mainline, but if n8x0 is considered finished and stable, we should
> reintroduce fixup. Thoughts?

N8x0 support is also "under development", and we are fine with updating
and always using latest in-tree DTs.

A.

Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Ladislav Michl]

On Thu, Jan 11, 2018 at 09:29:31PM +0200, Aaro Koskinen wrote:
> Hi,
> 
> On Wed, Jan 10, 2018 at 10:13:25PM +0100, Ladislav Michl wrote:
> > On Wed, Jan 10, 2018 at 07:35:19PM +0200, Aaro Koskinen wrote:
> > > On Wed, Jan 10, 2018 at 10:20:58AM +0100, Ladislav Michl wrote:
> > > > On Tue, Jan 09, 2018 at 11:01:14PM +0200, Aaro Koskinen wrote:
> > > > > On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
> > > > > > Merge window is really close now and patches seems still to be untested on
> > > > > > n8x0. So unless someone is going to test it soon, I'll pick used N800 on
> > > > > > ebay :-/
> > > > > 
> > > > > Today I tried to test them on Nokia N810, and I get:
> > > > > 
> > > > > [    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> > > > > [    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> > > > > [    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
> > > > > [    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> > > > > 
> > > > > With plain v4.15-rc7+ it probes fine.
> > > > 
> > > > Thank you for testing. As stated in cover letter, you need also
> > > > https://patchwork.kernel.org/patch/10043259/
> > > > which can be also found in Roger's branch
> > > > https://github.com/rogerq/linux/commits/for-v4.16/gpmc-omap-immutable
> > > > (see previous replies in this thread and also discussion about OneNAND
> > > > DT node)
> > > 
> > > I applied it, and now get:
> > > 
> > > [    0.174987] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> > > [    0.175048] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> > > [    0.177703] omap-gpmc 6800a000.gpmc: Incompatible OneNAND node: missing compatible
> > > [    0.177764] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> > 
> > As expected without reading discussion about OneNAND DT node :)
> > 
> > In short, this version expects "ti,omap2-onenand" compatible.
> 
> Right. I didn't realize by bootloader was passing the DTB from an old
> kernel.
> 
> So after fixing my boot I got the patches working N800 and N810: I was
> able to read and write on old JFFS2 file systems without any issues. So
> you can add for the series:
> 
> Tested-by: Aaro Koskinen <aaro.koskinen-X3B1VOXEql0@public.gmane.org>

Thank you!

> > In earlier version of this patchset there was fixup present, so driver
> > worked even without compatible. Later on (17 Oct 2017 11:46:51 +0300)
> > Roger objected (https://www.spinics.net/lists/linux-omap/msg139576.html):
> > "I don't want to fixup broken DTs like this as they will go silently without
> > being fixed. Let's instead just error out after the dev_warn(). This will
> > force us to fix all DT nodes."
> > So fixup was removed. I know N900 support is under heavy development
> > in mainline, but if n8x0 is considered finished and stable, we should
> > reintroduce fixup. Thoughts?
> 
> N8x0 support is also "under development", and we are fine with updating
> and always using latest in-tree DTs.

That makes things simpler :) I'll post v6 based on -next with patches 13 and
14 squashed.

Thanks to everyone involved for cooperation,
	ladis
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Re: [PATCH v5 00/16] OMAP2+ OneNAND driver update

[Ladislav Michl]

On Thu, Jan 11, 2018 at 09:29:31PM +0200, Aaro Koskinen wrote:
> Hi,
> 
> On Wed, Jan 10, 2018 at 10:13:25PM +0100, Ladislav Michl wrote:
> > On Wed, Jan 10, 2018 at 07:35:19PM +0200, Aaro Koskinen wrote:
> > > On Wed, Jan 10, 2018 at 10:20:58AM +0100, Ladislav Michl wrote:
> > > > On Tue, Jan 09, 2018 at 11:01:14PM +0200, Aaro Koskinen wrote:
> > > > > On Tue, Jan 09, 2018 at 02:08:12PM +0100, Ladislav Michl wrote:
> > > > > > Merge window is really close now and patches seems still to be untested on
> > > > > > n8x0. So unless someone is going to test it soon, I'll pick used N800 on
> > > > > > ebay :-/
> > > > > 
> > > > > Today I tried to test them on Nokia N810, and I get:
> > > > > 
> > > > > [    0.174804] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> > > > > [    0.174865] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> > > > > [    0.177459] omap-gpmc 6800a000.gpmc: /ocp/gpmc@6800a000/onenand@0,0 has no 'bank-width' property
> > > > > [    0.177612] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> > > > > 
> > > > > With plain v4.15-rc7+ it probes fine.
> > > > 
> > > > Thank you for testing. As stated in cover letter, you need also
> > > > https://patchwork.kernel.org/patch/10043259/
> > > > which can be also found in Roger's branch
> > > > https://github.com/rogerq/linux/commits/for-v4.16/gpmc-omap-immutable
> > > > (see previous replies in this thread and also discussion about OneNAND
> > > > DT node)
> > > 
> > > I applied it, and now get:
> > > 
> > > [    0.174987] omap-gpmc 6800a000.gpmc: GPMC revision 2.0
> > > [    0.175048] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
> > > [    0.177703] omap-gpmc 6800a000.gpmc: Incompatible OneNAND node: missing compatible
> > > [    0.177764] omap-gpmc 6800a000.gpmc: failed to probe DT child 'onenand': -22
> > 
> > As expected without reading discussion about OneNAND DT node :)
> > 
> > In short, this version expects "ti,omap2-onenand" compatible.
> 
> Right. I didn't realize by bootloader was passing the DTB from an old
> kernel.
> 
> So after fixing my boot I got the patches working N800 and N810: I was
> able to read and write on old JFFS2 file systems without any issues. So
> you can add for the series:
> 
> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>

Thank you!

> > In earlier version of this patchset there was fixup present, so driver
> > worked even without compatible. Later on (17 Oct 2017 11:46:51 +0300)
> > Roger objected (https://www.spinics.net/lists/linux-omap/msg139576.html):
> > "I don't want to fixup broken DTs like this as they will go silently without
> > being fixed. Let's instead just error out after the dev_warn(). This will
> > force us to fix all DT nodes."
> > So fixup was removed. I know N900 support is under heavy development
> > in mainline, but if n8x0 is considered finished and stable, we should
> > reintroduce fixup. Thoughts?
> 
> N8x0 support is also "under development", and we are fine with updating
> and always using latest in-tree DTs.

That makes things simpler :) I'll post v6 based on -next with patches 13 and
14 squashed.

Thanks to everyone involved for cooperation,
	ladis