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From: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
To: Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <kernel@pengutronix.de>,
	Fabio Estevam <fabio.estevam@nxp.com>,
	Will Deacon <will.deacon@arm.com>,
	Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@armlinux.org.uk>, Ian Ray <ian.ray@ge.com>,
	Nandor Han <nandor.han@ge.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@collabora.com,
	Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Subject: [PATCHv4 1/2] ARM: imx53: add secure-reg-access support for PMU
Date: Mon, 12 Feb 2018 13:39:44 +0100	[thread overview]
Message-ID: <20180212123945.15732-2-sebastian.reichel@collabora.co.uk> (raw)
In-Reply-To: <20180212123945.15732-1-sebastian.reichel@collabora.co.uk>

On i.MX53 it is necessary to set the DBG_EN bit in the
platform GPC register to enable access to PMU counters
other than the cycle counter.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
 arch/arm/mach-imx/mach-imx53.c | 39 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 07c2e8dca494..658e28604dca 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -28,10 +28,47 @@ static void __init imx53_init_early(void)
 	mxc_set_cpu_type(MXC_CPU_MX53);
 }
 
+#define MXC_CORTEXA8_PLAT_GPC 0x63fa0004
+#define GPC_DBG_EN BIT(16)
+
+/*
+ * This enables the DBGEN bit in ARM_GPC register, which is
+ * required for accessing some performance counter features.
+ * Technically it is only required while perf is used, but to
+ * keep the source code simple we just enable it all the time
+ * when the kernel configuration allows using the feature.
+ */
+static void imx53_pmu_init(void)
+{
+	void __iomem *gpc_reg;
+	struct device_node *node;
+	u32 gpc;
+
+	if (!IS_ENABLED(CONFIG_ARM_PMU))
+		return;
+
+	node = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu");
+	if (!node)
+		return;
+
+	if (!of_property_read_bool(node, "secure-reg-access"))
+		return;
+
+	gpc_reg = ioremap(MXC_CORTEXA8_PLAT_GPC, 4);
+	if (!gpc_reg) {
+		pr_warning("unable to map GPC to enable perf\n");
+		return;
+	}
+
+	gpc = readl_relaxed(gpc_reg);
+	gpc |= GPC_DBG_EN;
+	writel_relaxed(gpc, gpc_reg);
+}
+
 static void __init imx53_dt_init(void)
 {
 	imx_src_init();
-
+	imx53_pmu_init();
 	imx_aips_allow_unprivileged_access("fsl,imx53-aipstz");
 }
 
-- 
2.15.1

WARNING: multiple messages have this Message-ID (diff)
From: sebastian.reichel@collabora.co.uk (Sebastian Reichel)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv4 1/2] ARM: imx53: add secure-reg-access support for PMU
Date: Mon, 12 Feb 2018 13:39:44 +0100	[thread overview]
Message-ID: <20180212123945.15732-2-sebastian.reichel@collabora.co.uk> (raw)
In-Reply-To: <20180212123945.15732-1-sebastian.reichel@collabora.co.uk>

On i.MX53 it is necessary to set the DBG_EN bit in the
platform GPC register to enable access to PMU counters
other than the cycle counter.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
 arch/arm/mach-imx/mach-imx53.c | 39 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 07c2e8dca494..658e28604dca 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -28,10 +28,47 @@ static void __init imx53_init_early(void)
 	mxc_set_cpu_type(MXC_CPU_MX53);
 }
 
+#define MXC_CORTEXA8_PLAT_GPC 0x63fa0004
+#define GPC_DBG_EN BIT(16)
+
+/*
+ * This enables the DBGEN bit in ARM_GPC register, which is
+ * required for accessing some performance counter features.
+ * Technically it is only required while perf is used, but to
+ * keep the source code simple we just enable it all the time
+ * when the kernel configuration allows using the feature.
+ */
+static void imx53_pmu_init(void)
+{
+	void __iomem *gpc_reg;
+	struct device_node *node;
+	u32 gpc;
+
+	if (!IS_ENABLED(CONFIG_ARM_PMU))
+		return;
+
+	node = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu");
+	if (!node)
+		return;
+
+	if (!of_property_read_bool(node, "secure-reg-access"))
+		return;
+
+	gpc_reg = ioremap(MXC_CORTEXA8_PLAT_GPC, 4);
+	if (!gpc_reg) {
+		pr_warning("unable to map GPC to enable perf\n");
+		return;
+	}
+
+	gpc = readl_relaxed(gpc_reg);
+	gpc |= GPC_DBG_EN;
+	writel_relaxed(gpc, gpc_reg);
+}
+
 static void __init imx53_dt_init(void)
 {
 	imx_src_init();
-
+	imx53_pmu_init();
 	imx_aips_allow_unprivileged_access("fsl,imx53-aipstz");
 }
 
-- 
2.15.1

  reply	other threads:[~2018-02-12 12:39 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-12 12:39 [PATCHv4 0/2] Improved perf support for imx53/ppd Sebastian Reichel
2018-02-12 12:39 ` Sebastian Reichel
2018-02-12 12:39 ` Sebastian Reichel [this message]
2018-02-12 12:39   ` [PATCHv4 1/2] ARM: imx53: add secure-reg-access support for PMU Sebastian Reichel
2018-02-12 12:48   ` Fabio Estevam
2018-02-12 12:48     ` Fabio Estevam
2018-02-24  7:45   ` Shawn Guo
2018-02-24  7:45     ` Shawn Guo
2018-02-26 13:47     ` Sebastian Reichel
2018-02-26 13:47       ` Sebastian Reichel
2018-02-27  1:10       ` Shawn Guo
2018-02-27  1:10         ` Shawn Guo
2018-02-27 10:17         ` Sebastian Reichel
2018-02-27 10:17           ` Sebastian Reichel
2018-05-25 15:45           ` Sebastian Reichel
2018-05-25 15:45             ` Sebastian Reichel
2018-05-28  2:26           ` Shawn Guo
2018-05-28  2:26             ` Shawn Guo
2018-05-28  6:41             ` Sebastian Reichel
2018-05-28  6:41               ` Sebastian Reichel
2018-05-28  7:20               ` Shawn Guo
2018-05-28  7:20                 ` Shawn Guo
2018-05-28 15:50                 ` Sebastian Reichel
2018-05-28 15:50                   ` Sebastian Reichel
2018-06-18  4:00       ` Fabio Estevam
2018-06-18  4:00         ` Fabio Estevam
2018-02-12 12:39 ` [PATCHv4 2/2] ARM: dts: imx53: PPD: Enable secure-reg-access Sebastian Reichel
2018-02-12 12:39   ` Sebastian Reichel

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