From: Sebastian Reichel <sebastian.reichel@collabora.co.uk> To: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de>, Fabio Estevam <fabio.estevam@nxp.com>, Will Deacon <will.deacon@arm.com>, Mark Rutland <mark.rutland@arm.com>, Russell King <linux@armlinux.org.uk>, Ian Ray <ian.ray@ge.com>, Nandor Han <nandor.han@ge.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: Re: [PATCHv4 1/2] ARM: imx53: add secure-reg-access support for PMU Date: Mon, 26 Feb 2018 14:47:41 +0100 [thread overview] Message-ID: <20180226134741.neqkpge33zo3pfzt@earth.universe> (raw) In-Reply-To: <20180224074543.GF3217@dragon> [-- Attachment #1: Type: text/plain, Size: 2520 bytes --] Hi Shawn, On Sat, Feb 24, 2018 at 03:45:44PM +0800, Shawn Guo wrote: > On Mon, Feb 12, 2018 at 01:39:44PM +0100, Sebastian Reichel wrote: > > On i.MX53 it is necessary to set the DBG_EN bit in the > > platform GPC register to enable access to PMU counters > > other than the cycle counter. > > > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> > > --- > > arch/arm/mach-imx/mach-imx53.c | 39 ++++++++++++++++++++++++++++++++++++++- > > 1 file changed, 38 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c > > index 07c2e8dca494..658e28604dca 100644 > > --- a/arch/arm/mach-imx/mach-imx53.c > > +++ b/arch/arm/mach-imx/mach-imx53.c > > @@ -28,10 +28,47 @@ static void __init imx53_init_early(void) > > mxc_set_cpu_type(MXC_CPU_MX53); > > } > > > > +#define MXC_CORTEXA8_PLAT_GPC 0x63fa0004 > > The base address should be retrieved from device tree. DT has no entry for 0x63fa0000-0x63fa3fff. iMX53 TRM lists it as "ARM Platform" with 8 platform specific 32 bit registers. Do you think it's worth the trouble adding a new binding? Do you have a suggestion for a compatible value? -- Sebastian > > Shawn > > > +#define GPC_DBG_EN BIT(16) > > + > > +/* > > + * This enables the DBGEN bit in ARM_GPC register, which is > > + * required for accessing some performance counter features. > > + * Technically it is only required while perf is used, but to > > + * keep the source code simple we just enable it all the time > > + * when the kernel configuration allows using the feature. > > + */ > > +static void imx53_pmu_init(void) > > +{ > > + void __iomem *gpc_reg; > > + struct device_node *node; > > + u32 gpc; > > + > > + if (!IS_ENABLED(CONFIG_ARM_PMU)) > > + return; > > + > > + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); > > + if (!node) > > + return; > > + > > + if (!of_property_read_bool(node, "secure-reg-access")) > > + return; > > + > > + gpc_reg = ioremap(MXC_CORTEXA8_PLAT_GPC, 4); > > + if (!gpc_reg) { > > + pr_warning("unable to map GPC to enable perf\n"); > > + return; > > + } > > + > > + gpc = readl_relaxed(gpc_reg); > > + gpc |= GPC_DBG_EN; > > + writel_relaxed(gpc, gpc_reg); > > +} > > + > > static void __init imx53_dt_init(void) > > { > > imx_src_init(); > > - > > + imx53_pmu_init(); > > imx_aips_allow_unprivileged_access("fsl,imx53-aipstz"); > > } > > > > -- > > 2.15.1 > > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: sebastian.reichel@collabora.co.uk (Sebastian Reichel) To: linux-arm-kernel@lists.infradead.org Subject: [PATCHv4 1/2] ARM: imx53: add secure-reg-access support for PMU Date: Mon, 26 Feb 2018 14:47:41 +0100 [thread overview] Message-ID: <20180226134741.neqkpge33zo3pfzt@earth.universe> (raw) In-Reply-To: <20180224074543.GF3217@dragon> Hi Shawn, On Sat, Feb 24, 2018 at 03:45:44PM +0800, Shawn Guo wrote: > On Mon, Feb 12, 2018 at 01:39:44PM +0100, Sebastian Reichel wrote: > > On i.MX53 it is necessary to set the DBG_EN bit in the > > platform GPC register to enable access to PMU counters > > other than the cycle counter. > > > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> > > --- > > arch/arm/mach-imx/mach-imx53.c | 39 ++++++++++++++++++++++++++++++++++++++- > > 1 file changed, 38 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c > > index 07c2e8dca494..658e28604dca 100644 > > --- a/arch/arm/mach-imx/mach-imx53.c > > +++ b/arch/arm/mach-imx/mach-imx53.c > > @@ -28,10 +28,47 @@ static void __init imx53_init_early(void) > > mxc_set_cpu_type(MXC_CPU_MX53); > > } > > > > +#define MXC_CORTEXA8_PLAT_GPC 0x63fa0004 > > The base address should be retrieved from device tree. DT has no entry for 0x63fa0000-0x63fa3fff. iMX53 TRM lists it as "ARM Platform" with 8 platform specific 32 bit registers. Do you think it's worth the trouble adding a new binding? Do you have a suggestion for a compatible value? -- Sebastian > > Shawn > > > +#define GPC_DBG_EN BIT(16) > > + > > +/* > > + * This enables the DBGEN bit in ARM_GPC register, which is > > + * required for accessing some performance counter features. > > + * Technically it is only required while perf is used, but to > > + * keep the source code simple we just enable it all the time > > + * when the kernel configuration allows using the feature. > > + */ > > +static void imx53_pmu_init(void) > > +{ > > + void __iomem *gpc_reg; > > + struct device_node *node; > > + u32 gpc; > > + > > + if (!IS_ENABLED(CONFIG_ARM_PMU)) > > + return; > > + > > + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); > > + if (!node) > > + return; > > + > > + if (!of_property_read_bool(node, "secure-reg-access")) > > + return; > > + > > + gpc_reg = ioremap(MXC_CORTEXA8_PLAT_GPC, 4); > > + if (!gpc_reg) { > > + pr_warning("unable to map GPC to enable perf\n"); > > + return; > > + } > > + > > + gpc = readl_relaxed(gpc_reg); > > + gpc |= GPC_DBG_EN; > > + writel_relaxed(gpc, gpc_reg); > > +} > > + > > static void __init imx53_dt_init(void) > > { > > imx_src_init(); > > - > > + imx53_pmu_init(); > > imx_aips_allow_unprivileged_access("fsl,imx53-aipstz"); > > } > > > > -- > > 2.15.1 > > -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 833 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20180226/9f113406/attachment.sig>
next prev parent reply other threads:[~2018-02-26 13:47 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-02-12 12:39 [PATCHv4 0/2] Improved perf support for imx53/ppd Sebastian Reichel 2018-02-12 12:39 ` Sebastian Reichel 2018-02-12 12:39 ` [PATCHv4 1/2] ARM: imx53: add secure-reg-access support for PMU Sebastian Reichel 2018-02-12 12:39 ` Sebastian Reichel 2018-02-12 12:48 ` Fabio Estevam 2018-02-12 12:48 ` Fabio Estevam 2018-02-24 7:45 ` Shawn Guo 2018-02-24 7:45 ` Shawn Guo 2018-02-26 13:47 ` Sebastian Reichel [this message] 2018-02-26 13:47 ` Sebastian Reichel 2018-02-27 1:10 ` Shawn Guo 2018-02-27 1:10 ` Shawn Guo 2018-02-27 10:17 ` Sebastian Reichel 2018-02-27 10:17 ` Sebastian Reichel 2018-05-25 15:45 ` Sebastian Reichel 2018-05-25 15:45 ` Sebastian Reichel 2018-05-28 2:26 ` Shawn Guo 2018-05-28 2:26 ` Shawn Guo 2018-05-28 6:41 ` Sebastian Reichel 2018-05-28 6:41 ` Sebastian Reichel 2018-05-28 7:20 ` Shawn Guo 2018-05-28 7:20 ` Shawn Guo 2018-05-28 15:50 ` Sebastian Reichel 2018-05-28 15:50 ` Sebastian Reichel 2018-06-18 4:00 ` Fabio Estevam 2018-06-18 4:00 ` Fabio Estevam 2018-02-12 12:39 ` [PATCHv4 2/2] ARM: dts: imx53: PPD: Enable secure-reg-access Sebastian Reichel 2018-02-12 12:39 ` Sebastian Reichel
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