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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH 12/12] drm/i915/debugfs: Print how many blocks were sent in a selective update
Date: Thu, 22 Mar 2018 14:48:48 -0700	[thread overview]
Message-ID: <20180322214848.28022-12-jose.souza@intel.com> (raw)
In-Reply-To: <20180322214848.28022-1-jose.souza@intel.com>

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 40 ++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h     | 17 ++++++++++++++++
 2 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3182e9a7cc5d..20985584cc0f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2678,6 +2678,43 @@ static void psr_event_exit_sprintf(struct seq_file *m, u32 val,
 		seq_puts(m, "\tPSR disabled\n");
 }
 
+static void psr2_su_blocks_sprintf(struct seq_file *m,
+				   struct drm_i915_private *dev_priv)
+{
+	u32 val;
+	u16 su;
+
+	val = I915_READ(EDP_PSR2_SU_STATUS);
+	su = val >> EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_FRAME_N_SHIFT;
+	su &= EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_MASK;
+	seq_printf(m, "\tSU blocks in frame N: %d\n", su);
+	su = val >> EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_FRAME_N_MINUS_1_SHIFT;
+	su &= EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_MASK;
+	seq_printf(m, "\tSU blocks in frame N-1: %d\n", su);
+	su = val >> EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_FRAME_N_MINUS_2_SHIFT;
+	su &= EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_MASK;
+	seq_printf(m, "\tSU blocks in frame N-2: %d\n", su);
+
+	val = I915_READ(EDP_PSR2_SU_STATUS2);
+	su = val >> EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_FRAME_N_MINUS_3_SHIFT;
+	su &= EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_MASK;
+	seq_printf(m, "\tSU blocks in frame N-3: %d\n", su);
+	su = val >> EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_FRAME_N_MINUS_4_SHIFT;
+	su &= EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_MASK;
+	seq_printf(m, "\tSU blocks in frame N-4: %d\n", su);
+	su = val >> EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_FRAME_N_MINUS_5_SHIFT;
+	su &= EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_MASK;
+	seq_printf(m, "\tSU blocks in frame N-5: %d\n", su);
+
+	val = I915_READ(EDP_PSR2_SU_STATUS3);
+	su = val >> EDP_PSR2_SU_STATUS3_NUM_SU_BLOCKS_FRAME_N_MINUS_6_SHIFT;
+	su &= EDP_PSR2_SU_STATUS3_NUM_SU_BLOCKS_MASK;
+	seq_printf(m, "\tSU blocks in frame N-6: %d\n", su);
+	su = val >> EDP_PSR2_SU_STATUS3_NUM_SU_BLOCKS_FRAME_N_MINUS_7_SHIFT;
+	su &= EDP_PSR2_SU_STATUS3_NUM_SU_BLOCKS_MASK;
+	seq_printf(m, "\tSU blocks in frame N-7: %d\n", su);
+}
+
 static int i915_edp_psr_status(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -2766,8 +2803,9 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 	if (dev_priv->psr.psr2_enabled) {
 		u32 psr2 = I915_READ(EDP_PSR2_STATUS);
 
-		seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
+		seq_printf(m, "EDP_PSR2_STATUS: 0x%x [%s]\n",
 			   psr2, psr2_live_status(psr2));
+		psr2_su_blocks_sprintf(m, dev_priv);
 	}
 
 	if (dev_priv->psr.enabled) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 45f7703a9ee6..18af3e8fd4b6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3929,6 +3929,23 @@ enum {
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
 #define EDP_PSR2_STATUS_STATE_SHIFT    28
 
+#define EDP_PSR2_SU_STATUS					  _MMIO(0x6F914)
+#define  EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_MASK			  0x3FF
+#define  EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_FRAME_N_SHIFT		  0
+#define  EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_FRAME_N_MINUS_1_SHIFT	  10
+#define  EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_FRAME_N_MINUS_2_SHIFT	  20
+
+#define EDP_PSR2_SU_STATUS2					  _MMIO(0x6F918)
+#define  EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_MASK			  0x3FF
+#define  EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_FRAME_N_MINUS_3_SHIFT  0
+#define  EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_FRAME_N_MINUS_4_SHIFT  10
+#define  EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_FRAME_N_MINUS_5_SHIFT  20
+
+#define EDP_PSR2_SU_STATUS3					  _MMIO(0x6F91C)
+#define  EDP_PSR2_SU_STATUS3_NUM_SU_BLOCKS_MASK			  0x3FF
+#define  EDP_PSR2_SU_STATUS3_NUM_SU_BLOCKS_FRAME_N_MINUS_6_SHIFT  0
+#define  EDP_PSR2_SU_STATUS3_NUM_SU_BLOCKS_FRAME_N_MINUS_7_SHIFT  10
+
 /* VGA port control */
 #define ADPA			_MMIO(0x61100)
 #define PCH_ADPA                _MMIO(0xe1100)
-- 
2.16.2

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  parent reply	other threads:[~2018-03-22 21:52 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-22 21:48 [PATCH 01/12] drm: Add DP PSR2 sink enable bit José Roberto de Souza
2018-03-22 21:48 ` [PATCH 02/12] drm: Add DP last received PSR SDP VSC register and bits José Roberto de Souza
2018-03-22 23:23   ` Rodrigo Vivi
2018-03-23  0:59     ` Souza, Jose
2018-03-23  5:40       ` Rodrigo Vivi
2018-03-22 21:48 ` [PATCH 03/12] drm/i915/psr: Nuke aux frame sync José Roberto de Souza
2018-03-22 22:57   ` Rodrigo Vivi
2018-03-23  0:53     ` Souza, Jose
2018-03-23 22:14     ` Pandiyan, Dhinakaran
2018-03-23 23:49       ` Souza, Jose
2018-03-24  2:16         ` Pandiyan, Dhinakaran
2018-03-27  0:11           ` Souza, Jose
2018-03-22 21:48 ` [PATCH 04/12] drm/i915/psr: Tie PSR2 support to Y coordinate requirement José Roberto de Souza
2018-03-22 23:09   ` Rodrigo Vivi
2018-03-22 23:16     ` Souza, Jose
2018-03-23 22:59   ` Pandiyan, Dhinakaran
2018-03-23 23:51     ` Souza, Jose
2018-03-24  2:34       ` Pandiyan, Dhinakaran
2018-03-27 21:36         ` Rodrigo Vivi
2018-03-28  3:35           ` Nagaraju, Vathsala
2018-03-22 21:48 ` [PATCH 05/12] drm/i915/psr/cnl: Enable Y-coordinate support in source José Roberto de Souza
2018-03-22 21:48 ` [PATCH 06/12] drm/i915/psr: Do not override PSR2 sink support José Roberto de Souza
2018-03-22 21:48 ` [PATCH 07/12] drm/i915/psr: Use PSR2 macro for PSR2 José Roberto de Souza
2018-03-22 23:12   ` Rodrigo Vivi
2018-03-22 21:48 ` [PATCH 08/12] drm/i915/psr: Cache sink synchronization latency José Roberto de Souza
2018-03-22 23:15   ` Rodrigo Vivi
2018-03-23  0:21     ` Souza, Jose
2018-03-22 21:48 ` [PATCH 09/12] drm/i915/psr: Set DPCD PSR2 enable bit when needed José Roberto de Souza
2018-03-22 23:20   ` Rodrigo Vivi
2018-03-22 21:48 ` [PATCH 10/12] drm/i915/debugfs: Print sink PSR state and debug info José Roberto de Souza
2018-03-22 23:31   ` Rodrigo Vivi
2018-03-23  0:06     ` Souza, Jose
2018-03-23  0:11       ` Rodrigo Vivi
2018-03-24  3:23       ` Pandiyan, Dhinakaran
2018-03-22 21:48 ` [PATCH 11/12] drm/i915/debugfs: Print information about what caused a PSR exit José Roberto de Souza
2018-03-22 23:27   ` Rodrigo Vivi
2018-03-22 23:43     ` Pandiyan, Dhinakaran
2018-03-23  0:16       ` Souza, Jose
2018-03-23  0:22         ` Pandiyan, Dhinakaran
2018-03-22 21:48 ` José Roberto de Souza [this message]
2018-03-22 23:46   ` [PATCH 12/12] drm/i915/debugfs: Print how many blocks were sent in a selective update Rodrigo Vivi
2018-03-23  0:52     ` Souza, Jose
2018-03-22 21:56 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/12] drm: Add DP PSR2 sink enable bit Patchwork
2018-03-22 22:14 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-03-22 23:19 ` [PATCH 01/12] " Rodrigo Vivi

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