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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: [PATCH 05/12] drm/i915/psr/cnl: Enable Y-coordinate support in source
Date: Thu, 22 Mar 2018 14:48:41 -0700	[thread overview]
Message-ID: <20180322214848.28022-5-jose.souza@intel.com> (raw)
In-Reply-To: <20180322214848.28022-1-jose.souza@intel.com>

From: "Souza, Jose" <jose.souza@intel.com>

For Geminilake and Cannonlake+ the Y-coordinate support must be
enabled in PSR2_CTL too.

Spec: 7713 and 7720

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  3 +++
 drivers/gpu/drm/i915/intel_psr.c | 16 ++++++++++++----
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index da2f6c623ab2..9c4be6bcd1ef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3892,6 +3892,8 @@ enum {
 #define EDP_PSR2_CTL			_MMIO(0x6f900)
 #define   EDP_PSR2_ENABLE		(1<<31)
 #define   EDP_SU_TRACK_ENABLE		(1<<30)
+#define   EDP_Y_COORDINATE_VALID	(1<<26) /* GLK and CNL+ */
+#define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
 #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
 #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
 #define   EDP_PSR2_TP2_TIME_500		(0<<8)
@@ -6898,6 +6900,7 @@ enum {
 #define CHICKEN_TRANS_A         0x420c0
 #define CHICKEN_TRANS_B         0x420c4
 #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
+#define  VSC_DATA_SEL_SOFTWARE_CONTROL	(1<<25) /* GLK and CNL+ */
 #define  DDI_TRAINING_OVERRIDE_ENABLE	(1<<19)
 #define  DDI_TRAINING_OVERRIDE_VALUE	(1<<18)
 #define  DDIE_TRAINING_OVERRIDE_ENABLE	(1<<17) /* CHICKEN_TRANS_A only */
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 23f38ab10636..76e021428e57 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -387,8 +387,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	/* FIXME: selective update is probably totally broken because it doesn't
 	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
 	 * good enough. */
-	val |= EDP_PSR2_ENABLE |
-		EDP_SU_TRACK_ENABLE;
+	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
+	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+		val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE;
+	}
 
 	if (drm_dp_dpcd_readb(&intel_dp->aux,
 				DP_SYNCHRONIZATION_LATENCY_IN_SINK,
@@ -570,8 +572,14 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
 		hsw_psr_setup_aux(intel_dp);
 
 	if (dev_priv->psr.psr2_support) {
-		u32 chicken = PSR2_VSC_ENABLE_PROG_HEADER
-			      | PSR2_ADD_VERTICAL_LINE_COUNT;
+		u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
+
+		if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
+			chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
+				   | PSR2_ADD_VERTICAL_LINE_COUNT);
+
+		else
+			chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
 		I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
 
 		I915_WRITE(EDP_PSR_DEBUG,
-- 
2.16.2

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  parent reply	other threads:[~2018-03-22 21:51 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-22 21:48 [PATCH 01/12] drm: Add DP PSR2 sink enable bit José Roberto de Souza
2018-03-22 21:48 ` [PATCH 02/12] drm: Add DP last received PSR SDP VSC register and bits José Roberto de Souza
2018-03-22 23:23   ` Rodrigo Vivi
2018-03-23  0:59     ` Souza, Jose
2018-03-23  5:40       ` Rodrigo Vivi
2018-03-22 21:48 ` [PATCH 03/12] drm/i915/psr: Nuke aux frame sync José Roberto de Souza
2018-03-22 22:57   ` Rodrigo Vivi
2018-03-23  0:53     ` Souza, Jose
2018-03-23 22:14     ` Pandiyan, Dhinakaran
2018-03-23 23:49       ` Souza, Jose
2018-03-24  2:16         ` Pandiyan, Dhinakaran
2018-03-27  0:11           ` Souza, Jose
2018-03-22 21:48 ` [PATCH 04/12] drm/i915/psr: Tie PSR2 support to Y coordinate requirement José Roberto de Souza
2018-03-22 23:09   ` Rodrigo Vivi
2018-03-22 23:16     ` Souza, Jose
2018-03-23 22:59   ` Pandiyan, Dhinakaran
2018-03-23 23:51     ` Souza, Jose
2018-03-24  2:34       ` Pandiyan, Dhinakaran
2018-03-27 21:36         ` Rodrigo Vivi
2018-03-28  3:35           ` Nagaraju, Vathsala
2018-03-22 21:48 ` José Roberto de Souza [this message]
2018-03-22 21:48 ` [PATCH 06/12] drm/i915/psr: Do not override PSR2 sink support José Roberto de Souza
2018-03-22 21:48 ` [PATCH 07/12] drm/i915/psr: Use PSR2 macro for PSR2 José Roberto de Souza
2018-03-22 23:12   ` Rodrigo Vivi
2018-03-22 21:48 ` [PATCH 08/12] drm/i915/psr: Cache sink synchronization latency José Roberto de Souza
2018-03-22 23:15   ` Rodrigo Vivi
2018-03-23  0:21     ` Souza, Jose
2018-03-22 21:48 ` [PATCH 09/12] drm/i915/psr: Set DPCD PSR2 enable bit when needed José Roberto de Souza
2018-03-22 23:20   ` Rodrigo Vivi
2018-03-22 21:48 ` [PATCH 10/12] drm/i915/debugfs: Print sink PSR state and debug info José Roberto de Souza
2018-03-22 23:31   ` Rodrigo Vivi
2018-03-23  0:06     ` Souza, Jose
2018-03-23  0:11       ` Rodrigo Vivi
2018-03-24  3:23       ` Pandiyan, Dhinakaran
2018-03-22 21:48 ` [PATCH 11/12] drm/i915/debugfs: Print information about what caused a PSR exit José Roberto de Souza
2018-03-22 23:27   ` Rodrigo Vivi
2018-03-22 23:43     ` Pandiyan, Dhinakaran
2018-03-23  0:16       ` Souza, Jose
2018-03-23  0:22         ` Pandiyan, Dhinakaran
2018-03-22 21:48 ` [PATCH 12/12] drm/i915/debugfs: Print how many blocks were sent in a selective update José Roberto de Souza
2018-03-22 23:46   ` Rodrigo Vivi
2018-03-23  0:52     ` Souza, Jose
2018-03-22 21:56 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/12] drm: Add DP PSR2 sink enable bit Patchwork
2018-03-22 22:14 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-03-22 23:19 ` [PATCH 01/12] " Rodrigo Vivi

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