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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: [PATCH 06/12] drm/i915/psr: Do not override PSR2 sink support
Date: Thu, 22 Mar 2018 14:48:42 -0700	[thread overview]
Message-ID: <20180322214848.28022-6-jose.souza@intel.com> (raw)
In-Reply-To: <20180322214848.28022-1-jose.souza@intel.com>

Sink can support our PSR2 requirements but userspace can request
a resolution that PSR2 hardware do not support, in this case it
was overwritten the PSR2 sink support.
Adding another flag here, this way if requested resolution changed
to a value that PSR2 hardware can handle, PSR2 can be enabled.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  4 ++--
 drivers/gpu/drm/i915/i915_drv.h     |  3 ++-
 drivers/gpu/drm/i915/intel_psr.c    | 33 +++++++++++++++++----------------
 3 files changed, 21 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7816cd53100a..16f9977995df 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2630,7 +2630,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 		   yesno(work_busy(&dev_priv->psr.work.work)));
 
 	if (HAS_DDI(dev_priv)) {
-		if (dev_priv->psr.psr2_support)
+		if (dev_priv->psr.psr2_enabled)
 			enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
 		else
 			enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
@@ -2678,7 +2678,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 
 		seq_printf(m, "Performance_Counter: %u\n", psrperf);
 	}
-	if (dev_priv->psr.psr2_support) {
+	if (dev_priv->psr.psr2_enabled) {
 		u32 psr2 = I915_READ(EDP_PSR2_STATUS);
 
 		seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cce32686fd75..a367fe5538ae 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -601,11 +601,12 @@ struct i915_psr {
 	bool active;
 	struct delayed_work work;
 	unsigned busy_frontbuffer_bits;
-	bool psr2_support;
+	bool sink_psr2_support;
 	bool link_standby;
 	bool colorimetry_support;
 	bool alpm;
 	bool has_hw_tracking;
+	bool psr2_enabled;
 
 	void (*enable_source)(struct intel_dp *,
 			      const struct intel_crtc_state *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 76e021428e57..f73e2734a859 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -148,11 +148,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 		 * Y-coordinate requirement panels we would need to enable
 		 * GTC first.
 		 */
-		dev_priv->psr.psr2_support = intel_dp_get_y_coord_required(intel_dp);
-		DRM_DEBUG_KMS("PSR2 %s on sink",
-			      dev_priv->psr.psr2_support ? "supported" : "not supported");
+		dev_priv->psr.sink_psr2_support =
+				intel_dp_get_y_coord_required(intel_dp);
+		DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.sink_psr2_support
+			      ? "supported" : "not supported");
 
-		if (dev_priv->psr.psr2_support) {
+		if (dev_priv->psr.sink_psr2_support) {
 			dev_priv->psr.colorimetry_support =
 				intel_dp_get_colorimetry_status(intel_dp);
 			dev_priv->psr.alpm =
@@ -193,7 +194,7 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 	struct edp_vsc_psr psr_vsc;
 
-	if (dev_priv->psr.psr2_support) {
+	if (dev_priv->psr.psr2_enabled) {
 		/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
 		memset(&psr_vsc, 0, sizeof(psr_vsc));
 		psr_vsc.sdp_header.HB0 = 0;
@@ -266,7 +267,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 
 
 	/* Enable ALPM at sink for psr2 */
-	if (dev_priv->psr.psr2_support && dev_priv->psr.alpm)
+	if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm)
 		drm_dp_dpcd_writeb(&intel_dp->aux,
 				DP_RECEIVER_ALPM_CONFIG,
 				DP_ALPM_ENABLE);
@@ -425,7 +426,7 @@ static void hsw_psr_activate(struct intel_dp *intel_dp)
 	 */
 
 	/* psr1 and psr2 are mutually exclusive.*/
-	if (dev_priv->psr.psr2_support)
+	if (dev_priv->psr.psr2_enabled)
 		hsw_activate_psr2(intel_dp);
 	else
 		hsw_activate_psr1(intel_dp);
@@ -445,7 +446,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	 * dynamically during PSR enable, and extracted from sink
 	 * caps during eDP detection.
 	 */
-	if (!dev_priv->psr.psr2_support)
+	if (!dev_priv->psr.sink_psr2_support)
 		return false;
 
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
@@ -544,7 +545,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (dev_priv->psr.psr2_support)
+	if (dev_priv->psr.psr2_enabled)
 		WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
 	else
 		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
@@ -571,7 +572,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		hsw_psr_setup_aux(intel_dp);
 
-	if (dev_priv->psr.psr2_support) {
+	if (dev_priv->psr.psr2_enabled) {
 		u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
 
 		if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
@@ -630,7 +631,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
 		goto unlock;
 	}
 
-	dev_priv->psr.psr2_support = crtc_state->has_psr2;
+	dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
 	dev_priv->psr.busy_frontbuffer_bits = 0;
 
 	dev_priv->psr.setup_vsc(intel_dp, crtc_state);
@@ -700,7 +701,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
 		i915_reg_t psr_status;
 		u32 psr_status_mask;
 
-		if (dev_priv->psr.psr2_support) {
+		if (dev_priv->psr.psr2_enabled) {
 			psr_status = EDP_PSR2_STATUS;
 			psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
 
@@ -724,7 +725,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
 
 		dev_priv->psr.active = false;
 	} else {
-		if (dev_priv->psr.psr2_support)
+		if (dev_priv->psr.psr2_enabled)
 			WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
 		else
 			WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
@@ -784,7 +785,7 @@ static void intel_psr_work(struct work_struct *work)
 	 * and be ready for re-enable.
 	 */
 	if (HAS_DDI(dev_priv)) {
-		if (dev_priv->psr.psr2_support) {
+		if (dev_priv->psr.psr2_enabled) {
 			if (intel_wait_for_register(dev_priv,
 						    EDP_PSR2_STATUS,
 						    EDP_PSR2_STATUS_STATE_MASK,
@@ -843,7 +844,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
 		return;
 
 	if (HAS_DDI(dev_priv)) {
-		if (dev_priv->psr.psr2_support) {
+		if (dev_priv->psr.psr2_enabled) {
 			val = I915_READ(EDP_PSR2_CTL);
 			WARN_ON(!(val & EDP_PSR2_ENABLE));
 			I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
@@ -1012,7 +1013,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 
 	/* By definition flush = invalidate + flush */
 	if (frontbuffer_bits) {
-		if (dev_priv->psr.psr2_support ||
+		if (dev_priv->psr.psr2_enabled ||
 		    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 			intel_psr_exit(dev_priv);
 		} else {
-- 
2.16.2

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  parent reply	other threads:[~2018-03-22 21:51 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-22 21:48 [PATCH 01/12] drm: Add DP PSR2 sink enable bit José Roberto de Souza
2018-03-22 21:48 ` [PATCH 02/12] drm: Add DP last received PSR SDP VSC register and bits José Roberto de Souza
2018-03-22 23:23   ` Rodrigo Vivi
2018-03-23  0:59     ` Souza, Jose
2018-03-23  5:40       ` Rodrigo Vivi
2018-03-22 21:48 ` [PATCH 03/12] drm/i915/psr: Nuke aux frame sync José Roberto de Souza
2018-03-22 22:57   ` Rodrigo Vivi
2018-03-23  0:53     ` Souza, Jose
2018-03-23 22:14     ` Pandiyan, Dhinakaran
2018-03-23 23:49       ` Souza, Jose
2018-03-24  2:16         ` Pandiyan, Dhinakaran
2018-03-27  0:11           ` Souza, Jose
2018-03-22 21:48 ` [PATCH 04/12] drm/i915/psr: Tie PSR2 support to Y coordinate requirement José Roberto de Souza
2018-03-22 23:09   ` Rodrigo Vivi
2018-03-22 23:16     ` Souza, Jose
2018-03-23 22:59   ` Pandiyan, Dhinakaran
2018-03-23 23:51     ` Souza, Jose
2018-03-24  2:34       ` Pandiyan, Dhinakaran
2018-03-27 21:36         ` Rodrigo Vivi
2018-03-28  3:35           ` Nagaraju, Vathsala
2018-03-22 21:48 ` [PATCH 05/12] drm/i915/psr/cnl: Enable Y-coordinate support in source José Roberto de Souza
2018-03-22 21:48 ` José Roberto de Souza [this message]
2018-03-22 21:48 ` [PATCH 07/12] drm/i915/psr: Use PSR2 macro for PSR2 José Roberto de Souza
2018-03-22 23:12   ` Rodrigo Vivi
2018-03-22 21:48 ` [PATCH 08/12] drm/i915/psr: Cache sink synchronization latency José Roberto de Souza
2018-03-22 23:15   ` Rodrigo Vivi
2018-03-23  0:21     ` Souza, Jose
2018-03-22 21:48 ` [PATCH 09/12] drm/i915/psr: Set DPCD PSR2 enable bit when needed José Roberto de Souza
2018-03-22 23:20   ` Rodrigo Vivi
2018-03-22 21:48 ` [PATCH 10/12] drm/i915/debugfs: Print sink PSR state and debug info José Roberto de Souza
2018-03-22 23:31   ` Rodrigo Vivi
2018-03-23  0:06     ` Souza, Jose
2018-03-23  0:11       ` Rodrigo Vivi
2018-03-24  3:23       ` Pandiyan, Dhinakaran
2018-03-22 21:48 ` [PATCH 11/12] drm/i915/debugfs: Print information about what caused a PSR exit José Roberto de Souza
2018-03-22 23:27   ` Rodrigo Vivi
2018-03-22 23:43     ` Pandiyan, Dhinakaran
2018-03-23  0:16       ` Souza, Jose
2018-03-23  0:22         ` Pandiyan, Dhinakaran
2018-03-22 21:48 ` [PATCH 12/12] drm/i915/debugfs: Print how many blocks were sent in a selective update José Roberto de Souza
2018-03-22 23:46   ` Rodrigo Vivi
2018-03-23  0:52     ` Souza, Jose
2018-03-22 21:56 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/12] drm: Add DP PSR2 sink enable bit Patchwork
2018-03-22 22:14 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-03-22 23:19 ` [PATCH 01/12] " Rodrigo Vivi

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