* [PATCH v3 02/10] drm: Add DP last received PSR SDP VSC register and bits
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
@ 2018-03-28 22:30 ` José Roberto de Souza
2018-03-28 22:30 ` [PATCH v3 03/10] drm/i915/psr: Nuke aux frame sync José Roberto de Souza
` (12 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: José Roberto de Souza @ 2018-03-28 22:30 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
This is a register to help debug what is in the last SDP VSC
packet revived by sink.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
v3: rebased
include/drm/drm_dp_helper.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 0bac0c7d0dec..91c9bcd4196f 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -795,6 +795,15 @@
# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
+#define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
+# define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
+# define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */
+# define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */
+# define DP_SU_VALID (1 << 3) /* eDP 1.4 */
+# define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */
+# define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */
+# define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */
+
#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
--
2.16.3
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 03/10] drm/i915/psr: Nuke aux frame sync
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
2018-03-28 22:30 ` [PATCH v3 02/10] drm: Add DP last received PSR SDP VSC register and bits José Roberto de Souza
@ 2018-03-28 22:30 ` José Roberto de Souza
2018-03-28 22:30 ` [PATCH v3 04/10] drm/i915/psr: Tie PSR2 support to Y coordinate requirement José Roberto de Souza
` (11 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: José Roberto de Souza @ 2018-03-28 22:30 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
eDP spec states that aux frame is required to do PSR2 selective
update but i915 don't fully implement it. It sends the aux frame
sync messages but the value is always zero as the GTC is not enabled
in driver.
Through tests was findout that pannels can do selective update when
the y-coordinate is also included in SDP, that is why it is required
to run PSR2 in i915.
A dummy value is not useful at all to sink, so removing everything
related to aux frame sync, if GTC is enabled we can bring this back.
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
v3: rebased
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_psr.c | 24 +-----------------------
2 files changed, 1 insertion(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 800230ba1c3b..fade9029b6f5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -603,7 +603,6 @@ struct i915_psr {
struct delayed_work work;
unsigned busy_frontbuffer_bits;
bool psr2_support;
- bool aux_frame_sync;
bool link_standby;
bool y_cord_support;
bool colorimetry_support;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b8e083e10029..c0a6f63b586f 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -137,16 +137,9 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
if (INTEL_GEN(dev_priv) >= 9 &&
(intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
- uint8_t frame_sync_cap;
dev_priv->psr.sink_support = true;
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
- &frame_sync_cap) != 1)
- frame_sync_cap = 0;
- dev_priv->psr.aux_frame_sync = frame_sync_cap & DP_AUX_FRAME_SYNC_CAP;
- /* PSR2 needs frame sync as well */
- dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
+ dev_priv->psr.psr2_support = true;
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not supported");
@@ -268,12 +261,6 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
-
- /* Enable AUX frame sync at sink */
- if (dev_priv->psr.aux_frame_sync)
- drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
- DP_AUX_FRAME_SYNC_ENABLE);
/* Enable ALPM at sink for psr2 */
if (dev_priv->psr.psr2_support && dev_priv->psr.alpm)
drm_dp_dpcd_writeb(&intel_dp->aux,
@@ -712,11 +699,6 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
i915_reg_t psr_status;
u32 psr_status_mask;
- if (dev_priv->psr.aux_frame_sync)
- drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
- 0);
-
if (dev_priv->psr.psr2_support) {
psr_status = EDP_PSR2_STATUS;
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
@@ -860,10 +842,6 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
return;
if (HAS_DDI(dev_priv)) {
- if (dev_priv->psr.aux_frame_sync)
- drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
- 0);
if (dev_priv->psr.psr2_support) {
val = I915_READ(EDP_PSR2_CTL);
WARN_ON(!(val & EDP_PSR2_ENABLE));
--
2.16.3
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 04/10] drm/i915/psr: Tie PSR2 support to Y coordinate requirement
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
2018-03-28 22:30 ` [PATCH v3 02/10] drm: Add DP last received PSR SDP VSC register and bits José Roberto de Souza
2018-03-28 22:30 ` [PATCH v3 03/10] drm/i915/psr: Nuke aux frame sync José Roberto de Souza
@ 2018-03-28 22:30 ` José Roberto de Souza
2018-03-28 22:30 ` [PATCH v3 05/10] drm/i915/psr/cnl: Enable Y-coordinate support in source José Roberto de Souza
` (10 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: José Roberto de Souza @ 2018-03-28 22:30 UTC (permalink / raw)
To: intel-gfx; +Cc: José Roberto de Souza, dri-devel, Rodrigo Vivi
Although i915 don't implement aux sync frame through tests was
findout that pannels can do selective update when the y-coordinate
is also included in SDP, that is why it is required to run PSR2 in
i915.
So moving to only one place the sink requirements that the actual
driver needs to enable PSR2.
Also intel_psr2_config_valid() is called every time the crtc config
is computed, wasting some time every time it was checking for
Y coordinate requirement.
This allow us to nuke y_cord_support and some of VSC setup code that
was handling a scenario that would never happen(PSR2 without Y
coordinate).
Also here renaming intel_dp_get_y_cord_status() to
intel_dp_get_y_coord_required() as it more accurate to the name and
function of bit according to eDP spec.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
v3: rebased
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_psr.c | 46 +++++++++++++++++-----------------------
2 files changed, 19 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fade9029b6f5..92cf6f4e9e00 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -604,7 +604,6 @@ struct i915_psr {
unsigned busy_frontbuffer_bits;
bool psr2_support;
bool link_standby;
- bool y_cord_support;
bool colorimetry_support;
bool alpm;
bool has_hw_tracking;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c0a6f63b586f..fb2d0fe7106b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -93,7 +93,7 @@ static void psr_aux_io_power_put(struct intel_dp *intel_dp)
intel_display_power_put(dev_priv, psr_aux_domain(intel_dp));
}
-static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
+static bool intel_dp_get_y_coord_required(struct intel_dp *intel_dp)
{
uint8_t psr_caps = 0;
@@ -130,22 +130,29 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
sizeof(intel_dp->psr_dpcd));
- if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
+ if (intel_dp->psr_dpcd[0]) {
dev_priv->psr.sink_support = true;
DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
}
if (INTEL_GEN(dev_priv) >= 9 &&
- (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
-
- dev_priv->psr.sink_support = true;
- dev_priv->psr.psr2_support = true;
+ (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
+ /*
+ * All panels that supports PSR version 03h (PSR2 +
+ * Y-coordinate) can handle Y-coordinates in VSC but we are
+ * only sure that it is going to be used when required by the
+ * panel. This way panel is capable to do selective update
+ * without a aux frame sync.
+ *
+ * To support PSR version 02h and PSR version 03h without
+ * Y-coordinate requirement panels we would need to enable
+ * GTC first.
+ */
+ dev_priv->psr.psr2_support = intel_dp_get_y_coord_required(intel_dp);
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not supported");
if (dev_priv->psr.psr2_support) {
- dev_priv->psr.y_cord_support =
- intel_dp_get_y_cord_status(intel_dp);
dev_priv->psr.colorimetry_support =
intel_dp_get_colorimetry_status(intel_dp);
dev_priv->psr.alpm =
@@ -191,16 +198,12 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
memset(&psr_vsc, 0, sizeof(psr_vsc));
psr_vsc.sdp_header.HB0 = 0;
psr_vsc.sdp_header.HB1 = 0x7;
- if (dev_priv->psr.colorimetry_support &&
- dev_priv->psr.y_cord_support) {
+ if (dev_priv->psr.colorimetry_support) {
psr_vsc.sdp_header.HB2 = 0x5;
psr_vsc.sdp_header.HB3 = 0x13;
- } else if (dev_priv->psr.y_cord_support) {
+ } else {
psr_vsc.sdp_header.HB2 = 0x4;
psr_vsc.sdp_header.HB3 = 0xe;
- } else {
- psr_vsc.sdp_header.HB2 = 0x3;
- psr_vsc.sdp_header.HB3 = 0xc;
}
} else {
/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
@@ -457,15 +460,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
- /*
- * FIXME:enable psr2 only for y-cordinate psr2 panels
- * After gtc implementation , remove this restriction.
- */
- if (!dev_priv->psr.y_cord_support) {
- DRM_DEBUG_KMS("PSR2 not enabled, panel does not support Y coordinate\n");
- return false;
- }
-
return true;
}
@@ -565,7 +559,6 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- u32 chicken;
psr_aux_io_power_get(intel_dp);
@@ -576,9 +569,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
hsw_psr_setup_aux(intel_dp);
if (dev_priv->psr.psr2_support) {
- chicken = PSR2_VSC_ENABLE_PROG_HEADER;
- if (dev_priv->psr.y_cord_support)
- chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
+ u32 chicken = PSR2_VSC_ENABLE_PROG_HEADER
+ | PSR2_ADD_VERTICAL_LINE_COUNT;
I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
I915_WRITE(EDP_PSR_DEBUG,
--
2.16.3
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 05/10] drm/i915/psr/cnl: Enable Y-coordinate support in source
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
` (2 preceding siblings ...)
2018-03-28 22:30 ` [PATCH v3 04/10] drm/i915/psr: Tie PSR2 support to Y coordinate requirement José Roberto de Souza
@ 2018-03-28 22:30 ` José Roberto de Souza
2018-03-30 17:36 ` Pandiyan, Dhinakaran
2018-03-28 22:30 ` [PATCH v3 06/10] drm/i915/psr: Do not override PSR2 sink support José Roberto de Souza
` (9 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: José Roberto de Souza @ 2018-03-28 22:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, dri-devel
For Geminilake and Cannonlake+ the Y-coordinate support must be
enabled in PSR2_CTL too.
Spec: 7713 and 7720
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
v3: rebased
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_psr.c | 16 ++++++++++++----
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 33e52cc98d99..9d61ab1288d3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4058,6 +4058,8 @@ enum {
#define EDP_PSR2_CTL _MMIO(0x6f900)
#define EDP_PSR2_ENABLE (1<<31)
#define EDP_SU_TRACK_ENABLE (1<<30)
+#define EDP_Y_COORDINATE_VALID (1<<26) /* GLK and CNL+ */
+#define EDP_Y_COORDINATE_ENABLE (1<<25) /* GLK and CNL+ */
#define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
#define EDP_PSR2_TP2_TIME_500 (0<<8)
@@ -7064,6 +7066,7 @@ enum {
#define CHICKEN_TRANS_A 0x420c0
#define CHICKEN_TRANS_B 0x420c4
#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
+#define VSC_DATA_SEL_SOFTWARE_CONTROL (1<<25) /* GLK and CNL+ */
#define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
#define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
#define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index fb2d0fe7106b..84e1f8be5c48 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -386,8 +386,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
/* FIXME: selective update is probably totally broken because it doesn't
* mesh at all with our frontbuffer tracking. And the hw alone isn't
* good enough. */
- val |= EDP_PSR2_ENABLE |
- EDP_SU_TRACK_ENABLE;
+ val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE;
+ }
if (drm_dp_dpcd_readb(&intel_dp->aux,
DP_SYNCHRONIZATION_LATENCY_IN_SINK,
@@ -569,8 +571,14 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
hsw_psr_setup_aux(intel_dp);
if (dev_priv->psr.psr2_support) {
- u32 chicken = PSR2_VSC_ENABLE_PROG_HEADER
- | PSR2_ADD_VERTICAL_LINE_COUNT;
+ u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
+
+ if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
+ chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
+ | PSR2_ADD_VERTICAL_LINE_COUNT);
+
+ else
+ chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
I915_WRITE(EDP_PSR_DEBUG,
--
2.16.3
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 05/10] drm/i915/psr/cnl: Enable Y-coordinate support in source
2018-03-28 22:30 ` [PATCH v3 05/10] drm/i915/psr/cnl: Enable Y-coordinate support in source José Roberto de Souza
@ 2018-03-30 17:36 ` Pandiyan, Dhinakaran
2018-03-30 17:49 ` Souza, Jose
0 siblings, 1 reply; 22+ messages in thread
From: Pandiyan, Dhinakaran @ 2018-03-30 17:36 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx, dri-devel
On Wed, 2018-03-28 at 15:30 -0700, José Roberto de Souza wrote:
> For Geminilake and Cannonlake+ the Y-coordinate support must be
> enabled in PSR2_CTL too.
>
> Spec: 7713 and 7720
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>
> v3: rebased
>
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_psr.c | 16 ++++++++++++----
> 2 files changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 33e52cc98d99..9d61ab1288d3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4058,6 +4058,8 @@ enum {
> #define EDP_PSR2_CTL _MMIO(0x6f900)
> #define EDP_PSR2_ENABLE (1<<31)
> #define EDP_SU_TRACK_ENABLE (1<<30)
> +#define EDP_Y_COORDINATE_VALID (1<<26) /* GLK and CNL+ */
> +#define EDP_Y_COORDINATE_ENABLE (1<<25) /* GLK and CNL+ */
> #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
> #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
> #define EDP_PSR2_TP2_TIME_500 (0<<8)
> @@ -7064,6 +7066,7 @@ enum {
> #define CHICKEN_TRANS_A 0x420c0
> #define CHICKEN_TRANS_B 0x420c4
> #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> +#define VSC_DATA_SEL_SOFTWARE_CONTROL (1<<25) /* GLK and CNL+ */
> #define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
> #define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index fb2d0fe7106b..84e1f8be5c48 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -386,8 +386,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> /* FIXME: selective update is probably totally broken because it doesn't
> * mesh at all with our frontbuffer tracking. And the hw alone isn't
> * good enough. */
> - val |= EDP_PSR2_ENABLE |
> - EDP_SU_TRACK_ENABLE;
> + val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> + val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE;
Bspecs says Bit 26 : Y-coordinate valid
1b stands for "Do not include Y-coordinate valid eDP 1.4".
Was "val |= EDP_Y_COORDINATE_VALID" intended?
> + }
>
> if (drm_dp_dpcd_readb(&intel_dp->aux,
> DP_SYNCHRONIZATION_LATENCY_IN_SINK,
> @@ -569,8 +571,14 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
> hsw_psr_setup_aux(intel_dp);
>
> if (dev_priv->psr.psr2_support) {
> - u32 chicken = PSR2_VSC_ENABLE_PROG_HEADER
> - | PSR2_ADD_VERTICAL_LINE_COUNT;
> + u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
> +
> + if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
> + chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
> + | PSR2_ADD_VERTICAL_LINE_COUNT);
> +
> + else
> + chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
> I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
>
> I915_WRITE(EDP_PSR_DEBUG,
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^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 05/10] drm/i915/psr/cnl: Enable Y-coordinate support in source
2018-03-30 17:36 ` Pandiyan, Dhinakaran
@ 2018-03-30 17:49 ` Souza, Jose
0 siblings, 0 replies; 22+ messages in thread
From: Souza, Jose @ 2018-03-30 17:49 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx, dri-devel
On Fri, 2018-03-30 at 10:36 -0700, Pandiyan, Dhinakaran wrote:
>
>
> On Wed, 2018-03-28 at 15:30 -0700, José Roberto de Souza wrote:
> > For Geminilake and Cannonlake+ the Y-coordinate support must be
> > enabled in PSR2_CTL too.
> >
> > Spec: 7713 and 7720
> >
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >
> > v3: rebased
> >
> > drivers/gpu/drm/i915/i915_reg.h | 3 +++
> > drivers/gpu/drm/i915/intel_psr.c | 16 ++++++++++++----
> > 2 files changed, 15 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 33e52cc98d99..9d61ab1288d3 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4058,6 +4058,8 @@ enum {
> > #define EDP_PSR2_CTL _MMIO(0x6f900)
> > #define EDP_PSR2_ENABLE (1<<31)
> > #define EDP_SU_TRACK_ENABLE (1<<30)
> > +#define EDP_Y_COORDINATE_VALID (1<<26) /* GLK and CNL+ */
> > +#define EDP_Y_COORDINATE_ENABLE (1<<25) /* GLK and CNL+
> > */
> > #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
> > #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
> > #define EDP_PSR2_TP2_TIME_500 (0<<8)
> > @@ -7064,6 +7066,7 @@ enum {
> > #define CHICKEN_TRANS_A 0x420c0
> > #define CHICKEN_TRANS_B 0x420c4
> > #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A,
> > CHICKEN_TRANS_B)
> > +#define VSC_DATA_SEL_SOFTWARE_CONTROL (1<<25) /* GLK and
> > CNL+ */
> > #define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
> > #define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
> > #define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /*
> > CHICKEN_TRANS_A only */
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index fb2d0fe7106b..84e1f8be5c48 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -386,8 +386,10 @@ static void hsw_activate_psr2(struct intel_dp
> > *intel_dp)
> > /* FIXME: selective update is probably totally broken
> > because it doesn't
> > * mesh at all with our frontbuffer tracking. And the hw
> > alone isn't
> > * good enough. */
> > - val |= EDP_PSR2_ENABLE |
> > - EDP_SU_TRACK_ENABLE;
> > + val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> > + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > {
> > + val |= EDP_Y_COORDINATE_VALID |
> > EDP_Y_COORDINATE_ENABLE;
>
> Bspecs says Bit 26 : Y-coordinate valid
> 1b stands for "Do not include Y-coordinate valid eDP 1.4".
>
> Was "val |= EDP_Y_COORDINATE_VALID" intended?
Hum not intended, I will send a patch fixing it.
Thanks
>
>
> > + }
> >
> > if (drm_dp_dpcd_readb(&intel_dp->aux,
> > DP_SYNCHRONIZATION_LATENCY_IN_SINK
> > ,
> > @@ -569,8 +571,14 @@ static void hsw_psr_enable_source(struct
> > intel_dp *intel_dp,
> > hsw_psr_setup_aux(intel_dp);
> >
> > if (dev_priv->psr.psr2_support) {
> > - u32 chicken = PSR2_VSC_ENABLE_PROG_HEADER
> > - | PSR2_ADD_VERTICAL_LINE_COUNT;
> > + u32 chicken =
> > I915_READ(CHICKEN_TRANS(cpu_transcoder));
> > +
> > + if (INTEL_GEN(dev_priv) == 9 &&
> > !IS_GEMINILAKE(dev_priv))
> > + chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
> > + |
> > PSR2_ADD_VERTICAL_LINE_COUNT);
> > +
> > + else
> > + chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
> > I915_WRITE(CHICKEN_TRANS(cpu_transcoder),
> > chicken);
> >
> > I915_WRITE(EDP_PSR_DEBUG,
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 06/10] drm/i915/psr: Do not override PSR2 sink support
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
` (3 preceding siblings ...)
2018-03-28 22:30 ` [PATCH v3 05/10] drm/i915/psr/cnl: Enable Y-coordinate support in source José Roberto de Souza
@ 2018-03-28 22:30 ` José Roberto de Souza
2018-03-28 22:30 ` [PATCH v3 07/10] drm/i915/psr: Use PSR2 macro for PSR2 José Roberto de Souza
` (8 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: José Roberto de Souza @ 2018-03-28 22:30 UTC (permalink / raw)
To: intel-gfx; +Cc: José Roberto de Souza, Dhinakaran Pandiyan, dri-devel
Sink can support our PSR2 requirements but userspace can request
a resolution that PSR2 hardware do not support, in this case it
was overwritten the PSR2 sink support.
Adding another flag here, this way if requested resolution changed
to a value that PSR2 hardware can handle, PSR2 can be enabled.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
v3: rebased
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_psr.c | 33 +++++++++++++++++----------------
3 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ff90577da450..1dba2c451255 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2630,7 +2630,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
yesno(work_busy(&dev_priv->psr.work.work)));
if (HAS_DDI(dev_priv)) {
- if (dev_priv->psr.psr2_support)
+ if (dev_priv->psr.psr2_enabled)
enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
else
enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
@@ -2678,7 +2678,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
seq_printf(m, "Performance_Counter: %u\n", psrperf);
}
- if (dev_priv->psr.psr2_support) {
+ if (dev_priv->psr.psr2_enabled) {
u32 psr2 = I915_READ(EDP_PSR2_STATUS);
seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 92cf6f4e9e00..46cae097201c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -602,11 +602,12 @@ struct i915_psr {
bool active;
struct delayed_work work;
unsigned busy_frontbuffer_bits;
- bool psr2_support;
+ bool sink_psr2_support;
bool link_standby;
bool colorimetry_support;
bool alpm;
bool has_hw_tracking;
+ bool psr2_enabled;
void (*enable_source)(struct intel_dp *,
const struct intel_crtc_state *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 84e1f8be5c48..5efddd920681 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -148,11 +148,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
* Y-coordinate requirement panels we would need to enable
* GTC first.
*/
- dev_priv->psr.psr2_support = intel_dp_get_y_coord_required(intel_dp);
- DRM_DEBUG_KMS("PSR2 %s on sink",
- dev_priv->psr.psr2_support ? "supported" : "not supported");
+ dev_priv->psr.sink_psr2_support =
+ intel_dp_get_y_coord_required(intel_dp);
+ DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.sink_psr2_support
+ ? "supported" : "not supported");
- if (dev_priv->psr.psr2_support) {
+ if (dev_priv->psr.sink_psr2_support) {
dev_priv->psr.colorimetry_support =
intel_dp_get_colorimetry_status(intel_dp);
dev_priv->psr.alpm =
@@ -193,7 +194,7 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
struct edp_vsc_psr psr_vsc;
- if (dev_priv->psr.psr2_support) {
+ if (dev_priv->psr.psr2_enabled) {
/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
memset(&psr_vsc, 0, sizeof(psr_vsc));
psr_vsc.sdp_header.HB0 = 0;
@@ -265,7 +266,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = to_i915(dev);
/* Enable ALPM at sink for psr2 */
- if (dev_priv->psr.psr2_support && dev_priv->psr.alpm)
+ if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm)
drm_dp_dpcd_writeb(&intel_dp->aux,
DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE);
@@ -424,7 +425,7 @@ static void hsw_psr_activate(struct intel_dp *intel_dp)
*/
/* psr1 and psr2 are mutually exclusive.*/
- if (dev_priv->psr.psr2_support)
+ if (dev_priv->psr.psr2_enabled)
hsw_activate_psr2(intel_dp);
else
hsw_activate_psr1(intel_dp);
@@ -444,7 +445,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
* dynamically during PSR enable, and extracted from sink
* caps during eDP detection.
*/
- if (!dev_priv->psr.psr2_support)
+ if (!dev_priv->psr.sink_psr2_support)
return false;
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
@@ -543,7 +544,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- if (dev_priv->psr.psr2_support)
+ if (dev_priv->psr.psr2_enabled)
WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
else
WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
@@ -570,7 +571,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
hsw_psr_setup_aux(intel_dp);
- if (dev_priv->psr.psr2_support) {
+ if (dev_priv->psr.psr2_enabled) {
u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
@@ -629,7 +630,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
goto unlock;
}
- dev_priv->psr.psr2_support = crtc_state->has_psr2;
+ dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
dev_priv->psr.busy_frontbuffer_bits = 0;
dev_priv->psr.setup_vsc(intel_dp, crtc_state);
@@ -699,7 +700,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
i915_reg_t psr_status;
u32 psr_status_mask;
- if (dev_priv->psr.psr2_support) {
+ if (dev_priv->psr.psr2_enabled) {
psr_status = EDP_PSR2_STATUS;
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
@@ -723,7 +724,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
dev_priv->psr.active = false;
} else {
- if (dev_priv->psr.psr2_support)
+ if (dev_priv->psr.psr2_enabled)
WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
else
WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
@@ -783,7 +784,7 @@ static void intel_psr_work(struct work_struct *work)
* and be ready for re-enable.
*/
if (HAS_DDI(dev_priv)) {
- if (dev_priv->psr.psr2_support) {
+ if (dev_priv->psr.psr2_enabled) {
if (intel_wait_for_register(dev_priv,
EDP_PSR2_STATUS,
EDP_PSR2_STATUS_STATE_MASK,
@@ -842,7 +843,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
return;
if (HAS_DDI(dev_priv)) {
- if (dev_priv->psr.psr2_support) {
+ if (dev_priv->psr.psr2_enabled) {
val = I915_READ(EDP_PSR2_CTL);
WARN_ON(!(val & EDP_PSR2_ENABLE));
I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
@@ -1011,7 +1012,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
/* By definition flush = invalidate + flush */
if (frontbuffer_bits) {
- if (dev_priv->psr.psr2_support ||
+ if (dev_priv->psr.psr2_enabled ||
IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_psr_exit(dev_priv);
} else {
--
2.16.3
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 07/10] drm/i915/psr: Use PSR2 macro for PSR2
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
` (4 preceding siblings ...)
2018-03-28 22:30 ` [PATCH v3 06/10] drm/i915/psr: Do not override PSR2 sink support José Roberto de Souza
@ 2018-03-28 22:30 ` José Roberto de Souza
2018-03-28 22:30 ` [PATCH v3 08/10] drm/i915/psr: Cache sink synchronization latency José Roberto de Souza
` (7 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: José Roberto de Souza @ 2018-03-28 22:30 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Cosmetic change.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
v3: rebased
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
drivers/gpu/drm/i915/intel_psr.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9d61ab1288d3..dad0e4b82aab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4069,8 +4069,9 @@ enum {
#define EDP_PSR2_TP2_TIME_MASK (3<<8)
#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
-#define EDP_PSR2_IDLE_MASK 0xf
#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a)<<4)
+#define EDP_PSR2_IDLE_FRAME_MASK 0xf
+#define EDP_PSR2_IDLE_FRAME_SHIFT 0
#define EDP_PSR2_STATUS _MMIO(0x6f940)
#define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 5efddd920681..bec455e28943 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -382,7 +382,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
uint32_t val;
uint8_t sink_latency;
- val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
+ val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
/* FIXME: selective update is probably totally broken because it doesn't
* mesh at all with our frontbuffer tracking. And the hw alone isn't
--
2.16.3
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 08/10] drm/i915/psr: Cache sink synchronization latency
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
` (5 preceding siblings ...)
2018-03-28 22:30 ` [PATCH v3 07/10] drm/i915/psr: Use PSR2 macro for PSR2 José Roberto de Souza
@ 2018-03-28 22:30 ` José Roberto de Souza
2018-03-28 22:30 ` [PATCH v3 09/10] drm/i915/psr: Set DPCD PSR2 enable bit when needed José Roberto de Souza
` (6 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: José Roberto de Souza @ 2018-03-28 22:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, dri-devel
This value do not change overtime so better cache it than
fetch it every PSR enable.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
v3: rebased
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 28 ++++++++++++++++------------
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 46cae097201c..5373b171bb96 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -608,6 +608,7 @@ struct i915_psr {
bool alpm;
bool has_hw_tracking;
bool psr2_enabled;
+ u8 sink_sync_latency;
void (*enable_source)(struct intel_dp *,
const struct intel_crtc_state *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index bec455e28943..d079cf0b034c 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -122,6 +122,18 @@ static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
return alpm_caps & DP_ALPM_CAP;
}
+static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
+{
+ u8 val = 0;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux,
+ DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
+ val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
+ else
+ DRM_ERROR("Unable to get sink synchronization latency\n");
+ return val;
+}
+
void intel_psr_init_dpcd(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv =
@@ -158,6 +170,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
intel_dp_get_colorimetry_status(intel_dp);
dev_priv->psr.alpm =
intel_dp_get_alpm_status(intel_dp);
+ dev_priv->psr.sink_sync_latency =
+ intel_dp_get_sink_sync_latency(intel_dp);
}
}
}
@@ -379,10 +393,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
* with the 5 or 6 idle patterns.
*/
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
- uint32_t val;
- uint8_t sink_latency;
-
- val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
+ u32 val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
/* FIXME: selective update is probably totally broken because it doesn't
* mesh at all with our frontbuffer tracking. And the hw alone isn't
@@ -392,14 +403,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE;
}
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_SYNCHRONIZATION_LATENCY_IN_SINK,
- &sink_latency) == 1) {
- sink_latency &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
- } else {
- sink_latency = 0;
- }
- val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
+ val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR2_TP2_TIME_2500;
--
2.16.3
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 09/10] drm/i915/psr: Set DPCD PSR2 enable bit when needed
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
` (6 preceding siblings ...)
2018-03-28 22:30 ` [PATCH v3 08/10] drm/i915/psr: Cache sink synchronization latency José Roberto de Souza
@ 2018-03-28 22:30 ` José Roberto de Souza
2018-03-30 17:41 ` Rodrigo Vivi
2018-03-28 22:30 ` [PATCH v3 10/10] drm/i915/debugfs: Print sink PSR status José Roberto de Souza
` (5 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: José Roberto de Souza @ 2018-03-28 22:30 UTC (permalink / raw)
To: intel-gfx; +Cc: José Roberto de Souza, dri-devel, Dhinakaran Pandiyan
In the 2 eDP1.4a pannels tested set or not set bit have no effect
but is better set it and comply with specification.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
v3: rebased
drivers/gpu/drm/i915/intel_psr.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index d079cf0b034c..2d53f7398a6d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -278,18 +278,19 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
+ u8 dpcd_val = DP_PSR_ENABLE;
/* Enable ALPM at sink for psr2 */
if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm)
drm_dp_dpcd_writeb(&intel_dp->aux,
DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE);
+
+ if (dev_priv->psr.psr2_enabled)
+ dpcd_val |= DP_PSR_ENABLE_PSR2;
if (dev_priv->psr.link_standby)
- drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
- DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
- else
- drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
- DP_PSR_ENABLE);
+ dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
}
--
2.16.3
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 09/10] drm/i915/psr: Set DPCD PSR2 enable bit when needed
2018-03-28 22:30 ` [PATCH v3 09/10] drm/i915/psr: Set DPCD PSR2 enable bit when needed José Roberto de Souza
@ 2018-03-30 17:41 ` Rodrigo Vivi
2018-04-05 9:53 ` [Intel-gfx] " Chris Wilson
0 siblings, 1 reply; 22+ messages in thread
From: Rodrigo Vivi @ 2018-03-30 17:41 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Dhinakaran Pandiyan, dri-devel
On Wed, Mar 28, 2018 at 03:30:45PM -0700, José Roberto de Souza wrote:
> In the 2 eDP1.4a pannels tested set or not set bit have no effect
> but is better set it and comply with specification.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
patches 1-9 pushed to dinq. Thanks for patches and reviews.
> ---
>
> v3: rebased
>
> drivers/gpu/drm/i915/intel_psr.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index d079cf0b034c..2d53f7398a6d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -278,18 +278,19 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_device *dev = dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> + u8 dpcd_val = DP_PSR_ENABLE;
>
> /* Enable ALPM at sink for psr2 */
> if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm)
> drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_RECEIVER_ALPM_CONFIG,
> DP_ALPM_ENABLE);
> +
> + if (dev_priv->psr.psr2_enabled)
> + dpcd_val |= DP_PSR_ENABLE_PSR2;
> if (dev_priv->psr.link_standby)
> - drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
> - DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
> - else
> - drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
> - DP_PSR_ENABLE);
> + dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
>
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
> }
> --
> 2.16.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v3 09/10] drm/i915/psr: Set DPCD PSR2 enable bit when needed
2018-03-30 17:41 ` Rodrigo Vivi
@ 2018-04-05 9:53 ` Chris Wilson
0 siblings, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2018-04-05 9:53 UTC (permalink / raw)
To: Rodrigo Vivi, José Roberto de Souza
Cc: intel-gfx, Dhinakaran Pandiyan, dri-devel
Quoting Rodrigo Vivi (2018-03-30 18:41:08)
> On Wed, Mar 28, 2018 at 03:30:45PM -0700, José Roberto de Souza wrote:
> > In the 2 eDP1.4a pannels tested set or not set bit have no effect
> > but is better set it and comply with specification.
> >
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> patches 1-9 pushed to dinq. Thanks for patches and reviews.
Might be coincidental, but this GPF hasn't occurred before:
https://intel-gfx-ci.01.org/tree/drm-tip/kasan_26/fi-cfl-s3/dmesg15.log
<7>[ 40.159658] [drm:intel_enable_sagv [i915]] Enabling the SAGV
<0>[ 40.162715] kasan: CONFIG_KASAN_INLINE enabled
<0>[ 40.162884] kasan: GPF could be caused by NULL-ptr deref or user memory access
<4>[ 40.162910] general protection fault: 0000 [#1] PREEMPT SMP KASAN PTI
<4>[ 40.179985] Modules linked in: i915 cdc_ether usbnet x86_pkg_temp_thermal r8152 intel_powerclamp mii coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel e1000e mei_me mei prime_numbers
<4>[ 40.180000] CPU: 9 PID: 1395 Comm: kms_color Tainted: G U 4.16.0-rc7-g29940f138482-kasan_26+ #1
<4>[ 40.180002] Hardware name: Intel Corporation CoffeeLake Client Platform/CoffeeLake S UDIMM RVP, BIOS CNLSFWR1.R00.X118.B19.1802080131 02/08/2018
<4>[ 40.180055] RIP: 0010:intel_psr_flush+0x140/0x4b0 [i915]
<4>[ 40.180057] RSP: 0018:ffff880404fd7818 EFLAGS: 00010202
<4>[ 40.180060] RAX: dffffc0000000000 RBX: ffff8803b4820000 RCX: 0000000000000000
<4>[ 40.180062] RDX: 00000000000000bc RSI: 0000000000000000 RDI: 00000000000005e0
<4>[ 40.180076] RBP: ffff8803b482a5d8 R08: ffffffff8b02b360 R09: ffffffff8a32df20
<4>[ 40.180078] R10: ffff880404fd7818 R11: 0000000000000000 R12: 0000000000000100
<4>[ 40.180079] R13: 0000000000000000 R14: 0000000000000100 R15: 0000000000000000
<4>[ 40.180081] FS: 00007ff255bfe980(0000) GS:ffff88041dc40000(0000) knlGS:0000000000000000
<4>[ 40.180083] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
<4>[ 40.180085] CR2: 00007fdf372522f8 CR3: 0000000419d9a005 CR4: 00000000003606e0
<4>[ 40.180086] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
<4>[ 40.180088] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
<4>[ 40.180089] Call Trace:
<4>[ 40.180125] intel_frontbuffer_flush+0x8e/0xb0 [i915]
<4>[ 40.180161] intel_prepare_plane_fb+0x699/0xb20 [i915]
<4>[ 40.180167] drm_atomic_helper_prepare_planes+0x118/0x480
<4>[ 40.180202] ? haswell_crtc_compute_clock+0xc4/0xc4 [i915]
<4>[ 40.180237] intel_atomic_commit+0x215/0xcd0 [i915]
<4>[ 40.180242] set_property_atomic+0x1d5/0x250
<4>[ 40.180245] ? drm_object_property_get_value+0xe0/0xe0
<4>[ 40.180251] drm_mode_obj_set_property_ioctl+0x334/0x5b0
<4>[ 40.180254] ? drm_mode_obj_find_prop_id+0x180/0x180
<4>[ 40.180257] ? drm_is_current_master+0x5a/0x100
<4>[ 40.180260] ? drm_mode_obj_find_prop_id+0x180/0x180
<4>[ 40.180262] drm_ioctl_kernel+0x189/0x200
<4>[ 40.180265] ? drm_ioctl_permit+0x2b0/0x2b0
<4>[ 40.180269] drm_ioctl+0x662/0x880
<4>[ 40.180272] ? drm_mode_obj_find_prop_id+0x180/0x180
<4>[ 40.180274] ? drm_getstats+0x20/0x20
<4>[ 40.180277] ? lock_acquire+0x390/0x390
<4>[ 40.180281] ? debug_check_no_locks_freed+0x270/0x270
<4>[ 40.180284] ? __might_fault+0xea/0x1a0
<4>[ 40.180288] do_vfs_ioctl+0x171/0xe50
<4>[ 40.180292] ? ioctl_preallocate+0x170/0x170
<4>[ 40.180295] ? __task_pid_nr_ns+0x17b/0x3d0
<4>[ 40.180298] ? lock_acquire+0x390/0x390
<4>[ 40.180302] SyS_ioctl+0x36/0x70
<4>[ 40.180304] ? do_vfs_ioctl+0xe50/0xe50
<4>[ 40.180307] do_syscall_64+0x18a/0x5c0
<4>[ 40.180311] entry_SYSCALL_64_after_hwframe+0x42/0xb7
<4>[ 40.180313] RIP: 0033:0x7ff254cf65d7
<4>[ 40.180315] RSP: 002b:00007ffc2f0fca58 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
<4>[ 40.180317] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007ff254cf65d7
<4>[ 40.180319] RDX: 00007ffc2f0fca90 RSI: 00000000c01864ba RDI: 0000000000000003
<4>[ 40.180321] RBP: 00007ffc2f0fca90 R08: 0000000000000001 R09: 0000000000000000
<4>[ 40.180322] R10: 000055be9798e010 R11: 0000000000000246 R12: 00000000c01864ba
<4>[ 40.180324] R13: 0000000000000003 R14: 0000000000000000 R15: 0000000000000000
<4>[ 40.180328] Code: ea 03 80 3c 02 00 0f 85 4c 03 00 00 4d 8b ad 48 ff ff ff 48 b8 00 00 00 00 00 fc ff df 49 8d bd e0 05 00 00 48 89 fa 48 c1 ea 03 <0f> b6 04 02 84 c0 74 08 3c 03 0f 8e ee 01 00 00 4d 63 ad e0 05
<1>[ 40.180402] RIP: intel_psr_flush+0x140/0x4b0 [i915] RSP: ffff880404fd7818
<4>[ 40.180416] ---[ end trace 53653c4618c4b0b4 ]---
A null pointer in intel_psr_flush, probably crtc?
The code where we case the psr.enabled in the intel_psr_work preamble is
unlocked, and we do race there with intel_psr_disable() setting it to NULL
before cancelling the work. E.g.
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2d53f7398a6d..c0a7295920dd 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -758,6 +758,8 @@ void intel_psr_disable(struct intel_dp *intel_dp,
if (WARN_ON(!CAN_PSR(dev_priv)))
return;
+ cancel_delayed_work_sync(&dev_priv->psr.work);
+
mutex_lock(&dev_priv->psr.lock);
if (!dev_priv->psr.enabled) {
mutex_unlock(&dev_priv->psr.lock);
@@ -771,8 +773,6 @@ void intel_psr_disable(struct intel_dp *intel_dp,
dev_priv->psr.enabled = NULL;
mutex_unlock(&dev_priv->psr.lock);
-
- cancel_delayed_work_sync(&dev_priv->psr.work);
}
static void intel_psr_work(struct work_struct *work)
Haven't spotted the chain of events that leads to intel_psr_flush()
crashing though.
-Chris
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^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 10/10] drm/i915/debugfs: Print sink PSR status
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
` (7 preceding siblings ...)
2018-03-28 22:30 ` [PATCH v3 09/10] drm/i915/psr: Set DPCD PSR2 enable bit when needed José Roberto de Souza
@ 2018-03-28 22:30 ` José Roberto de Souza
2018-03-30 18:28 ` Pandiyan, Dhinakaran
2018-03-29 0:05 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit Patchwork
` (4 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: José Roberto de Souza @ 2018-03-28 22:30 UTC (permalink / raw)
To: intel-gfx
Cc: José Roberto de Souza, Dhinakaran Pandiyan, dri-devel, Rodrigo Vivi
IGT tests could be improved with sink status, knowing for sure that
hardware have activate or exit PSR.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
v3: rebased
drivers/gpu/drm/i915/i915_debugfs.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1dba2c451255..89dc5b05ec24 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2603,6 +2603,26 @@ static const char *psr2_live_status(u32 val)
return "unknown";
}
+static const char *psr_sink_self_refresh_status(u8 val)
+{
+ static const char * const sink_status[] = {
+ "inactive",
+ "transitioning to active",
+ "active",
+ "active receiving selective update",
+ "transitioning to inactive",
+ "reserved",
+ "reserved",
+ "sink internal error"
+ };
+
+ val &= DP_PSR_SINK_STATE_MASK;
+ if (val < ARRAY_SIZE(sink_status))
+ return sink_status[val];
+
+ return "unknown";
+}
+
static int i915_edp_psr_status(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -2684,6 +2704,15 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
psr2, psr2_live_status(psr2));
}
+
+ if (dev_priv->psr.enabled) {
+ struct drm_dp_aux *aux = &dev_priv->psr.enabled->aux;
+ u8 val;
+
+ if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, &val) == 1)
+ seq_printf(m, "Sink self refresh status: 0x%x [%s]\n",
+ val, psr_sink_self_refresh_status(val));
+ }
mutex_unlock(&dev_priv->psr.lock);
intel_runtime_pm_put(dev_priv);
--
2.16.3
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 10/10] drm/i915/debugfs: Print sink PSR status
2018-03-28 22:30 ` [PATCH v3 10/10] drm/i915/debugfs: Print sink PSR status José Roberto de Souza
@ 2018-03-30 18:28 ` Pandiyan, Dhinakaran
2018-03-30 19:19 ` [Intel-gfx] " Souza, Jose
0 siblings, 1 reply; 22+ messages in thread
From: Pandiyan, Dhinakaran @ 2018-03-30 18:28 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx, dri-devel, Vivi, Rodrigo
On Wed, 2018-03-28 at 15:30 -0700, José Roberto de Souza wrote:
> IGT tests could be improved with sink status, knowing for sure that
> hardware have activate or exit PSR.
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>
> v3: rebased
>
> drivers/gpu/drm/i915/i915_debugfs.c | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 1dba2c451255..89dc5b05ec24 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2603,6 +2603,26 @@ static const char *psr2_live_status(u32 val)
> return "unknown";
> }
>
> +static const char *psr_sink_self_refresh_status(u8 val)
nit: psr_sink_status() is concise, "psr_self_refresh" sounds
redundant.
> +{
> + static const char * const sink_status[] = {
> + "inactive",
> + "transitioning to active",
We muddle the meaning of these statuses by paraphrasing, it is better
write these strings exactly as the states are defined in the spec.
> + "active",
> + "active receiving selective update",
For example, this state corresponds to the capture of full static frame
too.
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> with
the nits addressed, thanks for the patch.
> + "transitioning to inactive",
> + "reserved",
> + "reserved",
> + "sink internal error"
> + };
> +
> + val &= DP_PSR_SINK_STATE_MASK;
> + if (val < ARRAY_SIZE(sink_status))
> + return sink_status[val];
> +
> + return "unknown";
> +}
> +
> static int i915_edp_psr_status(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> @@ -2684,6 +2704,15 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
> seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> psr2, psr2_live_status(psr2));
> }
> +
> + if (dev_priv->psr.enabled) {
> + struct drm_dp_aux *aux = &dev_priv->psr.enabled->aux;
> + u8 val;
> +
> + if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, &val) == 1)
> + seq_printf(m, "Sink self refresh status: 0x%x [%s]\n",
> + val, psr_sink_self_refresh_status(val));
> + }
> mutex_unlock(&dev_priv->psr.lock);
>
> intel_runtime_pm_put(dev_priv);
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH v3 10/10] drm/i915/debugfs: Print sink PSR status
2018-03-30 18:28 ` Pandiyan, Dhinakaran
@ 2018-03-30 19:19 ` Souza, Jose
2018-03-30 20:55 ` Pandiyan, Dhinakaran
0 siblings, 1 reply; 22+ messages in thread
From: Souza, Jose @ 2018-03-30 19:19 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx, dri-devel, Vivi, Rodrigo
On Fri, 2018-03-30 at 11:28 -0700, Pandiyan, Dhinakaran wrote:
> On Wed, 2018-03-28 at 15:30 -0700, José Roberto de Souza wrote:
> > IGT tests could be improved with sink status, knowing for sure that
> > hardware have activate or exit PSR.
> >
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >
> > v3: rebased
> >
> > drivers/gpu/drm/i915/i915_debugfs.c | 29
> > +++++++++++++++++++++++++++++
> > 1 file changed, 29 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 1dba2c451255..89dc5b05ec24 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2603,6 +2603,26 @@ static const char *psr2_live_status(u32 val)
> > return "unknown";
> > }
> >
> > +static const char *psr_sink_self_refresh_status(u8 val)
>
> nit: psr_sink_status() is concise,
> "psr_self_refresh" sounds
> redundant.
>
> > +{
> > + static const char * const sink_status[] = {
> > + "inactive",
> > + "transitioning to active",
>
> We muddle the meaning of these statuses by paraphrasing, it is better
> write these strings exactly as the states are defined in the spec.
>
> > + "active",
> > + "active receiving selective update",
>
> For example, this state corresponds to the capture of full static
> frame
> too.
It is fine this way?
static const char * const sink_status[] = {
"inactive",
"transition to active, capture and display",
"active, display from RFB",
"active, capture and display on sink device timings",
"transition to inactive, capture and display, timing
re-sync",
"reserved",
"reserved",
"sink internal error"
};
>
>
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> with
> the nits addressed, thanks for the patch.
>
> > + "transitioning to inactive",
> > + "reserved",
> > + "reserved",
> > + "sink internal error"
> > + };
> > +
> > + val &= DP_PSR_SINK_STATE_MASK;
> > + if (val < ARRAY_SIZE(sink_status))
> > + return sink_status[val];
> > +
> > + return "unknown";
> > +}
> > +
> > static int i915_edp_psr_status(struct seq_file *m, void *data)
> > {
> > struct drm_i915_private *dev_priv = node_to_i915(m-
> > >private);
> > @@ -2684,6 +2704,15 @@ static int i915_edp_psr_status(struct
> > seq_file *m, void *data)
> > seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> > psr2, psr2_live_status(psr2));
> > }
> > +
> > + if (dev_priv->psr.enabled) {
> > + struct drm_dp_aux *aux = &dev_priv->psr.enabled-
> > >aux;
> > + u8 val;
> > +
> > + if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, &val) ==
> > 1)
> > + seq_printf(m, "Sink self refresh status:
> > 0x%x [%s]\n",
> > + val,
> > psr_sink_self_refresh_status(val));
> > + }
> > mutex_unlock(&dev_priv->psr.lock);
> >
> > intel_runtime_pm_put(dev_priv);
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 10/10] drm/i915/debugfs: Print sink PSR status
2018-03-30 19:19 ` [Intel-gfx] " Souza, Jose
@ 2018-03-30 20:55 ` Pandiyan, Dhinakaran
0 siblings, 0 replies; 22+ messages in thread
From: Pandiyan, Dhinakaran @ 2018-03-30 20:55 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx, dri-devel, Vivi, Rodrigo
On Fri, 2018-03-30 at 19:19 +0000, Souza, Jose wrote:
> On Fri, 2018-03-30 at 11:28 -0700, Pandiyan, Dhinakaran wrote:
> > On Wed, 2018-03-28 at 15:30 -0700, José Roberto de Souza wrote:
> > > IGT tests could be improved with sink status, knowing for sure that
> > > hardware have activate or exit PSR.
> > >
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >
> > > v3: rebased
> > >
> > > drivers/gpu/drm/i915/i915_debugfs.c | 29
> > > +++++++++++++++++++++++++++++
> > > 1 file changed, 29 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index 1dba2c451255..89dc5b05ec24 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -2603,6 +2603,26 @@ static const char *psr2_live_status(u32 val)
> > > return "unknown";
> > > }
> > >
> > > +static const char *psr_sink_self_refresh_status(u8 val)
> >
> > nit: psr_sink_status() is concise,
> > "psr_self_refresh" sounds
> > redundant.
> >
> > > +{
> > > + static const char * const sink_status[] = {
> > > + "inactive",
> > > + "transitioning to active",
> >
> > We muddle the meaning of these statuses by paraphrasing, it is better
> > write these strings exactly as the states are defined in the spec.
> >
> > > + "active",
> > > + "active receiving selective update",
> >
> > For example, this state corresponds to the capture of full static
> > frame
> > too.
>
>
> It is fine this way?
>
> static const char * const sink_status[] = {
> "inactive",
> "transition to active, capture and display",
> "active, display from RFB",
> "active, capture and display on sink device timings",
> "transition to inactive, capture and display, timing
> re-sync",
> "reserved",
> "reserved",
> "sink internal error"
> };
>
>
Looks good.
> >
> >
> > Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> with
> > the nits addressed, thanks for the patch.
> >
> > > + "transitioning to inactive",
> > > + "reserved",
> > > + "reserved",
> > > + "sink internal error"
> > > + };
> > > +
> > > + val &= DP_PSR_SINK_STATE_MASK;
> > > + if (val < ARRAY_SIZE(sink_status))
> > > + return sink_status[val];
> > > +
> > > + return "unknown";
> > > +}
> > > +
> > > static int i915_edp_psr_status(struct seq_file *m, void *data)
> > > {
> > > struct drm_i915_private *dev_priv = node_to_i915(m-
> > > >private);
> > > @@ -2684,6 +2704,15 @@ static int i915_edp_psr_status(struct
> > > seq_file *m, void *data)
> > > seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> > > psr2, psr2_live_status(psr2));
> > > }
> > > +
> > > + if (dev_priv->psr.enabled) {
> > > + struct drm_dp_aux *aux = &dev_priv->psr.enabled-
> > > >aux;
> > > + u8 val;
> > > +
> > > + if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, &val) ==
> > > 1)
> > > + seq_printf(m, "Sink self refresh status:
> > > 0x%x [%s]\n",
> > > + val,
> > > psr_sink_self_refresh_status(val));
> > > + }
> > > mutex_unlock(&dev_priv->psr.lock);
> > >
> > > intel_runtime_pm_put(dev_priv);
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
` (8 preceding siblings ...)
2018-03-28 22:30 ` [PATCH v3 10/10] drm/i915/debugfs: Print sink PSR status José Roberto de Souza
@ 2018-03-29 0:05 ` Patchwork
2018-03-29 0:20 ` ✗ Fi.CI.BAT: " Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2018-03-29 0:05 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
URL : https://patchwork.freedesktop.org/series/40839/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
83dbb7136992 drm: Add DP PSR2 sink enable bit
36672bef768d drm: Add DP last received PSR SDP VSC register and bits
94b7edc3476d drm/i915/psr: Nuke aux frame sync
bbb38da76ef1 drm/i915/psr: Tie PSR2 support to Y coordinate requirement
1aed83cc161c drm/i915/psr/cnl: Enable Y-coordinate support in source
-:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:4061:
+#define EDP_Y_COORDINATE_VALID (1<<26) /* GLK and CNL+ */
^
-:27: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#27: FILE: drivers/gpu/drm/i915/i915_reg.h:4062:
+#define EDP_Y_COORDINATE_ENABLE (1<<25) /* GLK and CNL+ */
^
-:35: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:7069:
+#define VSC_DATA_SEL_SOFTWARE_CONTROL (1<<25) /* GLK and CNL+ */
^
total: 0 errors, 0 warnings, 3 checks, 43 lines checked
d4917260c5dc drm/i915/psr: Do not override PSR2 sink support
5a0735899e2a drm/i915/psr: Use PSR2 macro for PSR2
1c7cd16261ad drm/i915/psr: Cache sink synchronization latency
9cccb64694f4 drm/i915/psr: Set DPCD PSR2 enable bit when needed
b67c98399777 drm/i915/debugfs: Print sink PSR status
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Fi.CI.BAT: warning for series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
` (9 preceding siblings ...)
2018-03-29 0:05 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit Patchwork
@ 2018-03-29 0:20 ` Patchwork
2018-03-29 20:49 ` ✗ Fi.CI.CHECKPATCH: " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2018-03-29 0:20 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
URL : https://patchwork.freedesktop.org/series/40839/
State : warning
== Summary ==
Series 40839v1 series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
https://patchwork.freedesktop.org/api/1.0/series/40839/revisions/1/mbox/
---- Possible new issues:
Test debugfs_test:
Subgroup read_all_entries:
pass -> DMESG-WARN (fi-ilk-650)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-a-frame-sequence:
fail -> PASS (fi-cfl-s3)
Subgroup read-crc-pipe-c-frame-sequence:
fail -> PASS (fi-cfl-s3)
---- Known issues:
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail -> PASS (fi-cfl-s3) fdo#100368
Test kms_frontbuffer_tracking:
Subgroup basic:
pass -> FAIL (fi-cnl-y3) fdo#103167
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:426s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:440s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:379s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:532s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:298s
fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:514s
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:509s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:522s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:508s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:414s
fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:563s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:510s
fi-cnl-y3 total:285 pass:258 dwarn:0 dfail:0 fail:1 skip:26 time:583s
fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:418s
fi-gdg-551 total:285 pass:176 dwarn:0 dfail:0 fail:1 skip:108 time:319s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:533s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:403s
fi-ilk-650 total:285 pass:224 dwarn:1 dfail:0 fail:0 skip:60 time:424s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:467s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:430s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:474s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:461s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:509s
fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:661s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:437s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:531s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:498s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:506s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:426s
fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:442s
fi-snb-2520m total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:577s
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:403s
Blacklisted hosts:
fi-cnl-psr total:285 pass:256 dwarn:3 dfail:0 fail:0 skip:26 time:513s
fi-glk-j4005 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:489s
4668e88d66074a81aae645e0db0391e7ea9afe8a drm-tip: 2018y-03m-28d-20h-45m-29s UTC integration manifest
b67c98399777 drm/i915/debugfs: Print sink PSR status
9cccb64694f4 drm/i915/psr: Set DPCD PSR2 enable bit when needed
1c7cd16261ad drm/i915/psr: Cache sink synchronization latency
5a0735899e2a drm/i915/psr: Use PSR2 macro for PSR2
d4917260c5dc drm/i915/psr: Do not override PSR2 sink support
1aed83cc161c drm/i915/psr/cnl: Enable Y-coordinate support in source
bbb38da76ef1 drm/i915/psr: Tie PSR2 support to Y coordinate requirement
94b7edc3476d drm/i915/psr: Nuke aux frame sync
36672bef768d drm: Add DP last received PSR SDP VSC register and bits
83dbb7136992 drm: Add DP PSR2 sink enable bit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8526/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
` (10 preceding siblings ...)
2018-03-29 0:20 ` ✗ Fi.CI.BAT: " Patchwork
@ 2018-03-29 20:49 ` Patchwork
2018-03-29 21:07 ` ✓ Fi.CI.BAT: success " Patchwork
2018-03-30 1:20 ` ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2018-03-29 20:49 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
URL : https://patchwork.freedesktop.org/series/40839/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9ae66e05586d drm: Add DP PSR2 sink enable bit
ea5ff834dac7 drm: Add DP last received PSR SDP VSC register and bits
c4ff90984726 drm/i915/psr: Nuke aux frame sync
45b2682dc7e8 drm/i915/psr: Tie PSR2 support to Y coordinate requirement
4cc799de37d9 drm/i915/psr/cnl: Enable Y-coordinate support in source
-:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:4061:
+#define EDP_Y_COORDINATE_VALID (1<<26) /* GLK and CNL+ */
^
-:27: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#27: FILE: drivers/gpu/drm/i915/i915_reg.h:4062:
+#define EDP_Y_COORDINATE_ENABLE (1<<25) /* GLK and CNL+ */
^
-:35: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:7069:
+#define VSC_DATA_SEL_SOFTWARE_CONTROL (1<<25) /* GLK and CNL+ */
^
total: 0 errors, 0 warnings, 3 checks, 43 lines checked
5c9248d38cda drm/i915/psr: Do not override PSR2 sink support
bf021489296c drm/i915/psr: Use PSR2 macro for PSR2
82122405ae92 drm/i915/psr: Cache sink synchronization latency
20e02342f2b0 drm/i915/psr: Set DPCD PSR2 enable bit when needed
2ec83428a832 drm/i915/debugfs: Print sink PSR status
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
` (11 preceding siblings ...)
2018-03-29 20:49 ` ✗ Fi.CI.CHECKPATCH: " Patchwork
@ 2018-03-29 21:07 ` Patchwork
2018-03-30 1:20 ` ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2018-03-29 21:07 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
URL : https://patchwork.freedesktop.org/series/40839/
State : success
== Summary ==
Series 40839v1 series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
https://patchwork.freedesktop.org/api/1.0/series/40839/revisions/1/mbox/
---- Known issues:
Test gem_exec_suspend:
Subgroup basic-s3:
incomplete -> PASS (fi-skl-6700k2) fdo#104108
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS (fi-cnl-y3) fdo#103191
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:432s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:443s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:380s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:535s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:295s
fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:515s
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:511s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:523s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:509s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:411s
fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:559s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:512s
fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:589s
fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:424s
fi-gdg-551 total:285 pass:176 dwarn:0 dfail:0 fail:1 skip:108 time:316s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:538s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:405s
fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:421s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:467s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:433s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:472s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:472s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:510s
fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:666s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:440s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:536s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:506s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:493s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:430s
fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:451s
fi-snb-2520m total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:566s
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:408s
Blacklisted hosts:
fi-cnl-psr total:285 pass:256 dwarn:3 dfail:0 fail:0 skip:26 time:533s
fi-glk-j4005 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:484s
9829fcd7ae99d5955bb76a8fb8060e63339d7c9d drm-tip: 2018y-03m-29d-19h-56m-48s UTC integration manifest
2ec83428a832 drm/i915/debugfs: Print sink PSR status
20e02342f2b0 drm/i915/psr: Set DPCD PSR2 enable bit when needed
82122405ae92 drm/i915/psr: Cache sink synchronization latency
bf021489296c drm/i915/psr: Use PSR2 macro for PSR2
5c9248d38cda drm/i915/psr: Do not override PSR2 sink support
4cc799de37d9 drm/i915/psr/cnl: Enable Y-coordinate support in source
45b2682dc7e8 drm/i915/psr: Tie PSR2 support to Y coordinate requirement
c4ff90984726 drm/i915/psr: Nuke aux frame sync
ea5ff834dac7 drm: Add DP last received PSR SDP VSC register and bits
9ae66e05586d drm: Add DP PSR2 sink enable bit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8540/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
` (12 preceding siblings ...)
2018-03-29 21:07 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-03-30 1:20 ` Patchwork
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2018-03-30 1:20 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
URL : https://patchwork.freedesktop.org/series/40839/
State : success
== Summary ==
---- Known issues:
Test kms_flip:
Subgroup 2x-flip-vs-absolute-wf_vblank:
pass -> FAIL (shard-hsw) fdo#100368
Test kms_rotation_crc:
Subgroup sprite-rotation-90:
pass -> FAIL (shard-apl) fdo#103925
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
shard-apl total:3495 pass:1830 dwarn:1 dfail:0 fail:8 skip:1655 time:12881s
shard-hsw total:3495 pass:1782 dwarn:1 dfail:0 fail:2 skip:1709 time:11604s
shard-snb total:3495 pass:1374 dwarn:1 dfail:0 fail:3 skip:2117 time:7006s
Blacklisted hosts:
shard-kbl total:3495 pass:1959 dwarn:1 dfail:0 fail:7 skip:1528 time:9240s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8540/shards.html
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