[Qemu-devel] [PATCH v4 0/5] target/ppc: add hash MMU support for the POWER9 PowerNV machine

From: "Cédric Le Goater" <clg@kaod.org>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	David Gibson <david@gibson.dropbear.id.au>
Cc: "Suraj Jitindar Singh" <sjitindarsingh@gmail.com>,
	"Cédric Le Goater" <clg@kaod.org>
Subject: [Qemu-devel] [PATCH v4 0/5] target/ppc: add hash MMU support for the POWER9 PowerNV machine
Date: Tue, 24 Apr 2018 13:30:40 +0200	[thread overview]
Message-ID: <20180424113045.25687-1-clg@kaod.org> (raw)

Hello,

This adds support for the Hash Page Table MMU mode on POWER9 PowerNV
machines. The Radix Tree mode support for the host is still to be done
but we are getting close. 

Thanks,

C. 

Changes since v3:

 - removed spapr_hpt_base() ops
 - split hash MMU definitions patch

Cédric Le Goater (5):
  target/ppc: return a nil HPT base address on sPAPR machines
  target/ppc: add basic support for PTCR on POWER9
  target/ppc: add hash MMU definitions for ISA v3.0
  target/ppc: add hash MMU support for PowerNV POWER9 machines
  target/ppc: generalize check on radix when in HV mode

 hw/ppc/spapr_hcall.c        |  5 +++--
 target/ppc/cpu.h            |  2 ++
 target/ppc/helper.h         |  1 +
 target/ppc/misc_helper.c    | 12 +++++++++++
 target/ppc/mmu-book3s-v3.c  | 23 +++++++++++++++++++--
 target/ppc/mmu-book3s-v3.h  | 15 +++++++++++++-
 target/ppc/mmu-hash64.c     | 50 +++++++++++++++++++++++++++++++++++++--------
 target/ppc/mmu-hash64.h     | 39 +++++++++++++++++++++++++++++++++--
 target/ppc/mmu_helper.c     | 33 ++++++++++++++++++++++++++++--
 target/ppc/translate.c      |  3 +++
 target/ppc/translate_init.c | 18 ++++++++++++++++
 11 files changed, 184 insertions(+), 17 deletions(-)

-- 
2.13.6